SPIROC : Silicon PM Readout ASIC

Transcription

1 SPIROC : Silicon PM Readout ASIC Stéphane Callier, Frédéric Dulucq, Julien Fleury, Gisèle Martin-Chassard, Christophe de La Taille, Ludovic Raux IN2P3/OMEGA-LAL Orsay

2 18 june 8 C. de La Taille SPIROC : SiPM readout ASIC NDIP8 Aix les Bains 2 CALICE : imaging caorimetry After LHC : New imaging calorimetry at the ILC Improve jets measurement by Particle flow algorithm CALICE : 281 phys., 47 labs, 12 countries. Chairperson : JC Brient HCAL TCMT beam ECAL SiW ECAL W/Sci SiPM ECAL Sci SiPM AHCAL RPC DHCAL

3 18 june 8 C. de La Taille SPIROC : SiPM readout ASIC NDIP8 Aix les Bains 3 CALICE AHCAL testbeam prototype Hadronic calorimeter prototype for the ILC : 1 cubic metre, 38 layers, 2cm steel plates 8 tiles with SiPMs fabricated by MePHY group FLC_SiPM ASIC Mephy SiPM Mechanics and front end boards: DESY Front end ASICs: LAL Also used with W/Sci SiPM japanese ECAL with MPPCs

4 18 june 8 C. de La Taille SPIROC : SiPM readout ASIC NDIP8 Aix les Bains 4 ILC Challenges for electronics Requirements for electronics Large dynamic range (15 bits) Auto-trigger on ½ MIP On chip zero suppress Front-end embedded in detector Ultra-low power : («25µW/ch) 1 8 channels Compactness «Tracker electronics with calorimetric performance» No chip = no detector!! Ultra-low POWER is the KEY issue W layer ASIC Si wafers ILC : 25µW/ch FLC_PHY3 18ch 1*1mm 5mW/ch ATLAS LAr FEB 128ch 4*5mm 1 W/ch

5 18 june 8 C. de La Taille SPIROC : SiPM readout ASIC NDIP8 Aix les Bains 5 The front-end ASICs : the ROC chips SPIROC Analog HCAL (SiPM) 36 ch. 32mm² June 7 Technological prototypes : full scale modules (~2m) EUDET EU funding (6-9) ECAL, AHCAL, DHCAL B=5T HARDROC Digital HCAL (RPC, µmegas or GEMs) 64 ch. 16mm² Sept 6 SKIROC ECAL (Si PIN diode) 36 ch. 2mm² Nov 6

6 18 june 8 C. de La Taille SPIROC : SiPM readout ASIC NDIP8 Aix les Bains 6 Second generation chip for SiPM SPIROC : Silicon Photomul. Integrated Readout Chip 36 channels Charge measurement Time measurement Autotrigger on MIP or spe Sparsified readout compatible with EUDET 2 nd generation DAQ Chips daisy-chained Pulsed power -> 25 µw/ch Fabricated in SiGe AMS.35 µm Submitted in june 7 Chip area : 3 mm2

7 18 june 8 C. de La Taille SPIROC : SiPM readout ASIC NDIP8 Aix les Bains 7 SPIROC main features Internal input 8-bit DAC (-5V) for individual SiPM gain adjustment Energy measurement : 14 bits 2 gains (1-1) + 12 bit ADC 1 pe 2 pe Variable shaping time from 5ns to 1ns pe/noise ratio : 11 Auto-trigger on 1/3 pe (5fC) pe/noise ratio on trigger channel : 24 Fast shaper : ~1ns Auto-Trigger on ½ pe Time measurement : 12-bit Bunch Crossing ID 12 bit TDC step~1 ps Analog memory for time and charge measurement : depth = 16 Low consumption : ~25µW per channel (in power pulsing mode) Individually addressable calibration injection capacitance Embedded bandgap for voltage references Embedded 1 bit DAC for trigger threshold and gain selection Multiplexed analog output for physics prototype DAQ 4k internal memory and Daisy chain readout

8 18 june 8 C. de La Taille SPIROC : SiPM readout ASIC NDIP8 Aix les Bains 8 SPIROC : One channel schematic 1.5pF.1pF-1.5pF Slow Shaper Analog memory IN test IN 15pF 8-bit DAC Low gain Preamplifier.1pF-1.5pF High gain Preamplifier 5-1ns Slow Shaper 5-1ns 15ns HOLD Fast Shaper Discri Depth 16 Depth 16 Trigger Gain selection Charge measurement READ Variable delay Depth 16 Gain Flag TDC 12-bit Wilkinson ADC Conversion 8 µs -5V DAC output 4-bit threshold adjustment Common to the 36 channels 1-bit DAC TDC ramp 3ns/5 µs Time measurement

9 ValidHoldAnalogb 16 RazRangN Chipsat ReadMesureb gain ExtSigmaTM (OR36) Acquisition NoTrig StartAcqt SlowClock Wilkinson ADC Discri output TM (Discri trigger) Hit channel register 16 x 36 x 1 bits Channel Trigger discri Output 36 BCID 16 x 8 bits gain 36 ValGain (low gain or high Gain) Conversion ADC readout StartConvDAQb TransmitOn RamFull Channel 1 Trigger discri Output Wilkinson ADC Discri output 36 EndRamp (Discri ADC Wilkinson) FlagTDC + Ecriture RAM OutSerie EndReadOut StartReadOut Rstb.. OR36 ADC ramp Startrampb (wilkinson ramp) Clk4MHz ASIC TDC ramp StartRampTDC Chip ID register 8 bits ValDimGray 12 bits ChipID 8 ValDimGray 12 RAM DAQ 18 june 8 C. de La Taille SPIROC : SiPM readout ASIC NDIP8 Aix les Bains 9

10 18 june 8 C. de La Taille SPIROC : SiPM readout ASIC NDIP8 Aix les Bains 1 SPIROC layout 36 8bit 5V DAC 36 Preamp Shaper discri 36*16 Analog memory 36*2 Wilkinson ADC SRAM Readout Bandgap Dual DAC

11 18 june 8 C. de La Taille SPIROC : SiPM readout ASIC NDIP8 Aix les Bains 11 Simulated waveforms User: raux Date: Feb 9, 27 Time: 2:34:15 PM CET Y (mv) Y1 (mv) Y2 (mv) Y3 (mv) Y4 (mv) out_pa_hg out_pa_lg out_fs out_ssh_hg Expressions Simulation obtained with SiPM gain = 1 6 _ 1 pe = 16 fc High gain Preamplifier response Low gain Preamplifier response Fast shaper 12mV/pe Tp=15ns Noise/pe ratio = 25 High gain Slow shaper 1mV/pe Tp=5ns Noise/pe ratio = out_ssh_lg Low gain Slow shaper Tp=5ns.25 1mV/pe Noise/pe ratio = time (us).75 1.

12 18 june 8 C. de La Taille SPIROC : SiPM readout ASIC NDIP8 Aix les Bains 12 Input DAC 8 bit, 5V range LSB=2mV 36 DACs : one per channel Ultra low power (1µW) : no power pulsing Can sink 1 µa leakage current Linearity : ± 2% Voltage (V) 5 4,5 4 3,5 3 2,5 2 1,5 1,5 DAC linearity DAC,3,2,1 -,1 -,2 -,3 -,

13 18 june 8 C. de La Taille SPIROC : SiPM readout ASIC NDIP8 Aix les Bains 13 Trigger and gain selection DAC measurement Linearity : typ ±.2% 2,5 Trigger DAC 2,5 Gain selection DAC 2 1,5 Linearity 2 1,5 1 1,5,1,8,6,4,2 -,2 -,4 -,6 -,8 -,1 y = -,198623x + 2, R 2 =, ,5 Résiduals (V),4,3,2,1 -,1 -,2 -,3 -,4 y = -, x + 2, R 2 =,

14 18 june 8 C. de La Taille SPIROC : SiPM readout ASIC NDIP8 Aix les Bains 14 Input preamp Bi-gain low noise preamp Reused from SKIROC Low noise charge preamp capacitively coupled = voltage preamp Gain adjustable with 4 bits common to all preamps : Cf=.2,.4,.8, 1.6 pf Positive input pulse 8 mv/pe in HI Gain Noise : 1.4 nv/sqrt(hz) Power : 2 mw (unpulsed) Low gain at preamp level 1.5pF coupling capacitor.8 mv/pe, MAX : 2 pe (3pC) Si PM High voltage on the cable shielding +HV 15pF.1pF-1.5pF 8-bit DAC ASIC

15 18 june 8 C. de La Taille SPIROC : SiPM readout ASIC NDIP8 Aix les Bains 15 Analog waveforms High gain channel output 68fC ( ~4 gain=1 6) in SPIROC Charge measurement Vout=3mV Noise=1mV Gain=45mV/pC Auto trigger Set up: Cf=4fF Tau=5ns pe/noise~7 (expected ~11)

16 18 june 8 C. de La Taille SPIROC : SiPM readout ASIC NDIP8 Aix les Bains 16 Gain uniformity Pedestal uniformity Avg = 1.16V Rms = 1.8 mv Gain uniformity Rms 1% 45 mv/pc (Cf=.2pF tau=5ns) Noise : ~ 1mV Gain uniformity DC voltage (V) 1,17 1,165 1,16 1,155 1,15 46,5 pedestal Channel output (mv/pc) ,5 1 1,5 Cf (pf) Vout (mv) 46 45, , , Channel

17 18 june 8 C. de La Taille SPIROC : SiPM readout ASIC NDIP8 Aix les Bains 17 S-curves Trigger efficiency versus Threshold (1UDAC=2mV) S-curves trigger efficiency Measured Noise ~8mV (expected ~ 5mV) DAC value

18 18 june 8 C. de La Taille SPIROC : SiPM readout ASIC NDIP8 Aix les Bains 18 Trigger linearity 5% trigger efficiency vs Qinj Cf=2fF; tau=5ns 1 5% trigger efficiency DAC value Qinj (fc)

19 18 june 8 C. de La Taille SPIROC : SiPM readout ASIC NDIP8 Aix les Bains 19 Crosstalk and trigger time walk Very low Cross-Talk :.3% (long distance cross talk due to slow shaper voltage reference: If this voltage decoupled with 1µF, it becomes negligible ~.4%) Trigger time walk: ~1ns 12 1 trigger time walk vs injected charge time (in ns) charge (in fc)

20 18 june 8 C. de La Taille SPIROC : SiPM readout ASIC NDIP8 Aix les Bains 2 12 bit Wilkinson ADC performance (stupid) bug in internal ADC : cannot be tested Similar to ADC in sister chip SKIROC 1 ADC/channel 12 bits 8µs Fixed in SPIROC2 Count (#) - total is SKIROC ADC dispersion - channel 18 Noise in low gain shaper rms =.9UADC (33µV) MIP = 3 UADC ADC count (#) Pedestal value vs Channel number Skiroc Pedestal Dispersion (Internal ADC)-Gain 1 18 Count (#) - total is ADC bins (#) mean: std :.883 Noise in high gain shaper rms = 4UADC (1.4mV) MIP= 3UADC SKIROC ADC dispersion - channel channel number (#) ADC bins (#) mean: std : 4.629

21 18 june 8 C. de La Taille SPIROC : SiPM readout ASIC NDIP8 Aix les Bains 21 Single photoelectron spectrum Spiroc1 can already replace FLC_SiPM (multiplexed analog output) Beni (DESY)

22 18 june 8 C. de La Taille SPIROC : SiPM readout ASIC NDIP8 Aix les Bains 22 Conclusion SPIROC is a versatile readout chip for SiPM photodetectors It provides Charge measurement from 1 pe to 2 pe in two linear scales with a signal to noise ratio of 1 Time measurement to better than 1 ns Auto-trigger on ½ pe with internal 1 bit DAC Ultra low power 5V 8bit input DAC for SiPM gain adjustment 25 µw/ch with 1% ILC Power pulsing On chip Wilkinson ADC and RAM for daisy chain readout It will be produced in large scale in 29 for the EUDET AHCAL module More information on MAROC, HaRDROC, SPIROC, SKIROC, PARISROC on

23 Backup slides 18 june 8 C. de La Taille SPIROC : SiPM readout ASIC NDIP8 Aix les Bains 23

24 18 june 8 C. de La Taille SPIROC : SiPM readout ASIC NDIP8 Aix les Bains 24 Barrel HCAL architecture 1/16 of barrel half AHCAL Slab 6 HBUs in a row Front end ASICs embedded Interfaces accessible HBU HCAL Base Unit 12 x 12 tiles HLD HCAL Layer Distributor SPIROC 4 on a HBU HEB HCAL Endcap Board Hosts mezzanine modules: DIF, CALIB and POWER Power: 4 µw / channel Heat: T grad..3k/2m Time constant: 6 d P.Goettlicher (DESY)

25 18 june 8 C. de La Taille SPIROC : SiPM readout ASIC NDIP8 Aix les Bains 25 Integrated layer design Sector wall Reflector Foil 1µm Top Plate fixing ASIC TQFP-1 1mm high Polyimide Foil 1µm PCB HBU Interface 5µm gap 8µm Top Plate Spacer 6µm steel 1.7mm DESY Component Area: SiPM 9µm high Bottom Plate Bolt with inner Tile HBU height: 6µm M3 thread 3mm 6.1mm welded to bottom plate (4.9mm without covers => absorber) integrated M.Reinecke (DESY) Absorber Plates (steel)

26 18 june 8 C. de La Taille SPIROC : SiPM readout ASIC NDIP8 Aix les Bains 26 Slow shaper & SCA Slow shaper from HaRDROC Variable peaking time : 5-15 ns 3 bits common to all channels High Gain = 1 mv/pe Noise = 9 µv Low gain = 1 mv/pe 25 Slow Shaper 5-1ns Analog memory Depth 16 Backup : analog T&H from HaRDROC Hold capacitor : 2pF ->.5 pf Needs external hold signal Multiplexed analog 5MHz Allows readout with DAQ delay (ns) 2 y = 2,8821x + 13,41 R 2 =, DTC code

27 18 june 8 C. de La Taille SPIROC : SiPM readout ASIC NDIP8 Aix les Bains 27 TDC New block 12 bits 3 ns full scale 1 ps LSB (not accuracy!) «common start» = BC Time stored in SCA together with charge Can also be readout with backup analog Discri Fast ramp 3ns Trigger Depth 16 T

28 Wilkinson ADC Taken from MAROC New: adjustable resolution : 8-1 or 12 bits 4 MHz clock 6-1 µs conversion time Power dissipation : 35µW INL versus Vin 2 1,5 1,5 INL (ADC count) -,5-1 -1,5-2 -2,5 1,3 1,6 1,9 2,2 2,5 Vin(V) 18 june 8 C. de La Taille SPIROC : SiPM readout ASIC NDIP8 Aix les Bains 28

29 18 june 8 C. de La Taille SPIROC : SiPM readout ASIC NDIP8 Aix les Bains 29 Digital part Inspired from HaRDROC Internal or external Trigger OR36 output Discriminator Validation fast input 4kbyte RAM «Open collector» output signals LVDS clocks Start conversion Start/end readout