FDD7N25LZ N-Channel UniFET TM MOSFET 250 V, 6.2 A, 550 mω Features

Transcription

1 FDD7N25LZ N-Channel UniFET TM MOSFET 250 V, 6.2 A, 550 mω Features R DS(on) = 430 mω = 0 V, I D = 3. A Low Gate Charge (Typ. 2 nc) Low C rss (Typ. 8 pf) 00% Avalanche Tested Improved dv/dt Capability ESD Improved Capability RoHS Compliant Applications LCD/LED/PDP TV Consumer Appliances Lighting Uninterruptible Power Supply AC-DC Power Supply Description November 203 UniFET TM MOSFET is Fairchild Semiconductor s high voltage MOSFET family based on planar stripe and DMOS technology. This MOSFET is tailored to reduce on-state resistance, and to provide better switching performance and higher avalanche energy strength. This device family is suitable for switching power converter applications such as power factor correction (PFC), flat panel display (FPD) TV power, ATX and electronic lamp ballasts. D D G S D-PAK G MOSFET Maximum Ratings T C = 25 o C unless otherwise noted. S Symbol Parameter FDD7N25LZTM Unit V DSS Drain to Source Voltage 250 V S Gate to Source Voltage ±20 V I D Drain Current - Continuous (T C = 25 o C) Continuous (T C = 00 o C) 3.7 A I DM Drain Current - Pulsed (Note ) 25 A E AS Single Pulsed Avalanche Energy (Note 2) 5 mj I AR Avalanche Current (Note ) 5.5 A E AR Repetitive Avalanche Energy (Note ) 5.6 mj dv/dt Peak Diode Recovery dv/dt (Note 3) 0 V/ns P D Power Dissipation (T C = 25 o C) 56 W - Derate Above 25 o C 0.45 W/ o C T J, T STG Operating and Storage Temperature Range -55 to +50 o C T L Maximum Lead Temperature for Soldering, /8 from Case for 5 Seconds 300 o C Thermal Characteristics Symbol Parameter FDD7N25LZTM Unit R θjc Thermal Resistance, Junction to Case, Max. 2.2 o C/W R θja Thermal Resistance, Junction to Ambient, Max. 0

2 Package Marking and Ordering Information Part Number Top Mark Package Packing Method Reel Size Tape Width Quantity FDD7N25LZTM FDD7N25LZ DPAK Tape and Reel 330 mm 6 mm 2500 units Electrical Characteristics T C = 25 o C unless otherwise noted. Symbol Parameter Test Conditions Min. Typ. Max. Unit Off Characteristics BV DSS Drain to Source Breakdown Voltage I D = 250 μa, = 0 V, T C = 25 o C V ΔBV DSS Breakdown Voltage Temperature / ΔT J Coefficient I D = 250 μa, Referenced to 25 o C V/ o C I DSS Zero Gate Voltage Drain Current V DS = 250 V, = 0 V - - V DS = 200 V, T C = 25 o C μa I GSSF Gate to Body Leakage Current, Forward = 20 V, V DS = 0 V μa I GSSR Gate to Body Leakage Current, Reverse = -20 V, V DS = 0 V μa On Characteristics (th) Gate Threshold Voltage = V DS, I D = 250 μa V V R GS = 0 V, I D = 3. A DS(on) Static Drain to Source On Resistance Ω = 5 V, I D = 3. A g FS Forward Transconductance V DS = 20 V, I D = 3. A S Dynamic Characteristics C iss Input Capacitance pf V DS = 25 V, = 0 V, C oss Output Capacitance pf f = MHz C rss Reverse Transfer Capacitance pf Q g(tot) Total Gate Charge at 0V V DS = 250 V I D = 6.2 A, nc Q gs Gate to Source Gate Charge = 0 V nc Q gd Gate to Drain Miller Charge (Note 4) nc Switching Characteristics t d(on) Turn-On Delay Time ns t r Turn-On Rise Time V DD = 250 V, I D = 6.2 A, ns t d(off) Turn-Off Delay Time = 0 V, R G = 25 Ω ns t f Turn-Off Fall Time (Note 4) ns Drain-Source Diode Characteristics I S Maximum Continuous Drain to Source Diode Forward Current A I SM Maximum Pulsed Drain to Source Diode Forward Current A V SD Drain to Source Diode Forward Voltage = 0 V, I SD = 6.2 A V t rr Reverse Recovery Time = 0 V, I SD = 6.2 A, ns Q rr Reverse Recovery Charge di F /dt = 00 A/μs μc Notes:. Repetitive rating: pulse-width limited by maximum junction temperature. 2. L = 6 mh, I AS = 6.2 A, V DD = 50 V, R G = 25 Ω, starting T J = 25 C. 3. I SD 6.2 A, di/dt 200 A/μs, V DD BV DSS, starting T J = 25 C. 4. Essentially independent of operating temperature typical characteristics. 2

3 Typical Performance Characteristics ID, Drain Current[A] Figure. On-Region Characteristics = 0.0V 7.0V 5.0V 3.5V 3.0V 2.5V *Notes:. 250μs Pulse Test 2. T C = 25 o C V DS, Drain-Source Voltage[V] Figure 2. Transfer Characteristics. V DS = 20V μs Pulse Test , Gate-Source Voltage[V] Figure 3. On-Resistance Variation vs. Figure 4. Body Diode Forward Voltage Drain Current and Gate Voltage Variation vs. Source Current and Temperature.5 ID, Drain Current[A] o C -55 o C 25 o C RDS(on) [Ω], Drain-Source On-Resistance = 0V = 20V * Note : T J = 25 o C I D, Drain Current [A] Figure 5. Capacitance Characteristics 000 IS, Reverse Drain Current [A] 0 50 o C 25 o C Notes:. = 0V μs Pulse Test V SD, Body Diode Forward Voltage [V] Figure 6. Gate Charge Characteristics 0 Capacitances [pf] 00 0 Ciss = Cgs + Cgd (Cds = shorted) Coss = Cds + Cgd Crss = Cgd V DS, Drain-Source Voltage [V] C iss C oss * Note:. = 0V 2. f = MHz C rss VGS, Gate-Source Voltage [V] V DS = 50V V DS = 25V V DS = 200V * Note : I D = 6.2A Q g, Total Gate Charge [nc] 3

4 Typical Performance Characteristics (Continued) BVDSS, [Normalized] Drain-Source Breakdown Voltage Figure 7. Breakdown Voltage Variation vs. Temperature = 0V 2. I D = 250uA T J, Junction Temperature [ o C] Figure 9. Maximum Safe Operating Area μs 30μs RDS(on), [Normalized] Drain-Source On-Resistance Figure 8. On-Resistance Variation vs. Temperature = 0V 2. I D = 3.A T J, Junction Temperature [ o C] Figure 0. Maximum Drain Current vs. Case Temperature 6 5 ID, Drain Current [A] Operation in This Area is Limited by R DS(on) ms 0ms 0.. T C = 25 o C 2. T J = 50 o C 3. Single Pulse V DS, Drain-Source Voltage [V] DC ID, Drain Current [A] T C, Case Temperature [ o C] Figure. Transient Thermal Response Curve Z Thermal θjc (t), Thermal Response Response [Z [ θjc ] o C/W] Single pulse. Z θjc (t) = 2.2 o C/W Max. 2. Duty Factor, D=t /t 2 3. T JM - T C = P DM * Z θjc (t) t, Rectangular Pulse Duration [sec] P DM t t 2 4

5 I G = const. Figure 2. Gate Charge Test Circuit & Waveform V DS R L V DS 90% R G V DD V 0 DUT 0% t d(on) t r t d(off) tf t on t off Figure 3. Resistive Switching Test Circuit & Waveforms Figure 4. Unclamped Inductive Switching Test Circuit & Waveforms 5

6 R G DUT I SD Driver + V DS _ Same Type as DUT L V DD dv/dt controlled by RG I SD controlled by pulse period ( Driver ) Gate Pulse Width D = Gate Pulse Period 0V I FM, Body Diode Forward Current I SD ( DUT ) di/dt I RM Body Diode Reverse Current V DS ( DUT ) Body Diode Recovery dv/dt V SD V DD Body Diode Forward Voltage Drop Figure 5. Peak Diode Recovery dv/dt Test Circuit & Waveforms 6

7 Mechanical Dimensions Figure 6. TO252 (D-PAK), Molded, 3-Lead, Option AA&AB Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor s online packaging area for the most recent package drawings: 7

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