100 db Range (10 na to 1 ma) Logarithmic Converter AD8305 *

Transcription

1 db Range ( na to ma) Logarithmic Converter AD85 * FEATURES Optimized for Fiber Optic Photodiode Interfacing Measures Current over 5 Decades Law Conformance. db from na to ma Single- or Dual-Supply Operation ( V to V Total) Full Log-Ratio Capabilities Nominal Slope of mv/db ( mv/decade) Nominal Intercept of na (Set by External Resistor) Optional Adjustment of Slope and Intercept Complete and Temperature Stable Rapid Response Time for a Given Current Level Miniature 6-Lead Chip Scale Package (LFCSP mm mm) Low Power: ~5 ma Quiescent Current APPLICATIONS Optical Power Measurement Wide Range Baseband Logarithmic Compression Measurement of Current and Voltage Ratios Optical Absorbance Measurement k V BIAS I PD VSUM FUNCTIONAL BLOCK DIAGRAM.5V.5V 8k BIAS.5V GENERATOR k SCAL V BE.k I Q LOG TEMPERATURE 5 Q + COMPENSATION VNEG V I P PD. log VPOS V BE 6.69k ( ) na GENERAL DESCRIPTION The AD85 is an inexpensive microminiature logarithmic converter optimized for determining optical power in fiber optic systems. It uses an advanced implementation of a classic translinear (junction based) technique to provide a large dynamic range in a versatile and easily used form. A single-supply voltage of between V and V is adequate; dual supplies may optionally be used. The low quiescent current (typically 5 ma) permits use in battery-operated applications. The input current, I PD, of na to ma applied to the pin is the collector current of an optimally scaled NPN transistor, which converts this current to a voltage (V BE ) with a precise logarithmic relationship. A second such converter is used to handle the reference current (I REF ) applied to pin. These input nodes are biased slightly above ground (.5 V). This is generally acceptable for photodiode applications where the anode does not need to be grounded. Similarly, this bias voltage is easily accounted for in generating I REF. The output of the logarithmic front end is available at Pin. The basic logarithmic slope at this output is nominally mv/ decade ( mv/db). Thus, a db range corresponds to an output change of V. When this voltage (or the buffer output) is applied to an ADC that permits an external reference voltage to be employed, the AD85 s voltage reference output of.5 V at Pin can be used to improve the scaling accuracy. Suitable ADCs include the AD78 (serial -bit), AD78 (serial *Protected by U.S. Patent No.,6,5 and 5,59,8; other patents pending. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. 8-bit), and AD78 (parallel, 8-bit or -bit). Other values of the logarithmic slope can be provided using a simple external resistor network. The logarithmic intercept (also known as the reference current) is nominally positioned at na by the use of the externally generated current, I REF, of ma, provided by a kw resistor connected between, at.5 V, and the reference input, at.5 V. The intercept can be adjusted over a wide range by varying this resistor. The AD85 can also operate in a logratio mode, with the numerator current applied to and the denominator current applied to. A buffer amplifier is provided for driving a substantial load, for use in raising the basic slope of mv/db to higher values, as a precision comparator (threshold detector), or in implementing low-pass filters. Its rail-to-rail output stage can swing to within mv of the positive and negative supply rails, and its peak current sourcing capacity is 5 ma. It is a fundamental aspect of translinear logarithmic converters that the small signal bandwidth falls as the current level diminishes, and the low frequency noise-spectral density increases. At the na level, the bandwidth of the AD85 is about 5 khz, and increases in proportion to I PD up to a maximum value of about 5 MHz. Using the buffer amplifier, the increase in noise level at low currents can be addressed by using it to realize lowpass filters of up to three poles. The AD85 is available in a 6-lead LFCSP package and is specified for operation from C to +85 C. One Technology Way, P.O. Box 96, Norwood, MA 6-96, U.S.A. Tel: 78/9-7 Fax: 78/6-87 Analog Devices, Inc. All rights reserved.

2 AD85 SPECIFICATIONS (V P = 5 V, V N = V, T A = 5 C, R REF = k, and connected to, unless otherwise noted.) Parameter Conditions Min Typ Max Unit INPUT INTERFACE Pin,, Pin, Specified Current Range, I PD Flows toward Pin n m A Input Current Min/Max Limits Flows toward Pin m A Reference Current, I REF, Range Flows toward Pin n m A Summing Node Voltage Internally Preset; May be Altered by User V Temperature Drift C < T A < +85 C.5 mv/ C Input Offset Voltage V V SUM, V V SUM + mv LOGARITHMIC OUTPUT Pin 9, Logarithmic Slope 9 mv/dec C < T A < +85 C 85 5 mv/dec Logarithmic Intercept..7 na C < T A < +85 C..5 na Law Conformance Error na < I PD < ma.. db Wideband Noise I PD > ma.7 mv Hz Small Signal Bandwidth I PD > ma.7 MHz Maximum Output Voltage.7 V Minimum Output Voltage Limited by V N = V. V Output Resistance kw REFERENCE OUTPUT Pin, Voltage wrt Ground V C < T A < +85 C..6 V Maximum Output Current Sourcing (Grounded Load) ma Incremental Output Resistance Load Current < ma W OUTPUT BUFFER Pin, ; Pin, SCAL; Pin, Input Offset Voltage + mv Input Bias Current Flowing out of Pin or. ma Incremental Input Resistance 5 MW Output Range R L = kw to ground V P. V Incremental Output Resistance Load Current < ma.5 W Peak Source/Sink Current 5 ma Small Signal Bandwidth GAIN = 5 MHz Slew Rate. V to.8 V Output Swing 5 V/ms POWER SUPPLY Pin 8, VPOS; Pin 6 and Pin 7, VNEG Positive Supply Voltage (V P V N ) V 5 V Quiescent Current ma Negative Supply Voltage (Optional) (V P V N ) V 5.5 V NOTES Other values of logarithmic intercept can be achieved by adjusting R REF. Output noise and incremental bandwidth are functions of input current, measured using output buffer connected for GAIN =.

3 AD85 ABSOLUTE MAXIMUM RATINGS Supply Voltage V P V N V Input Current ma Internal Power Dissipation mw JA C/W Maximum Junction Temperature C Operating Temperature Range C to +85 C Storage Temperature Range C to +5 C Lead Temperature Range (Soldering 6 sec) C ORDERING GUIDE Temperature Package Package Model Range Description Option AD85ACP C to +85 C 6-Lead LFCSP CP-6 AD85ACP-REEL7 7" Tape and Reel AD85-EVAL Evaluation Board NOTES Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. With package die paddle soldered to thermal pad containing nine vias connected to inner and bottom layers. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD85 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. PIN CONFIGURATION AD85 SCAL 9 VSUM 5 VNEG 6 VNEG 7 VPOS PIN INDICATOR TOP VIEW PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Function Top of a Resistive Divider Network that Offsets V LOG to Position the Intercept. Normally connected to ; may also be connected to ground when bipolar outputs are to be provided. Reference Output Voltage of.5 V. Accepts (Sinks) Reference Current, I REF. Accepts (Sinks) Photodiode Current, I PD. Usually connected to photodiode anode such that photo current flows into. 5 VSUM Guard Pin. Used to shield the current line and for optional adjustment of the and I REF node potential. 6, 7 VNEG Optional Negative Supply, V N. (This pin is usually grounded; for details of usage, see the Applications section). 8 VPOS Positive Supply, (V P V N ) V. 9 Output of the Logarithmic Front End. Buffer Amplifier Noninverting Input. SCAL Buffer Amplifier Inverting Input. Buffer Output. 6 Analog Ground.

4 AD85 Typical Performance Characteristics (V P = 5 V, V N = V, R REF = k, T A = 5 C, unless otherwise noted.).6. T A = C, C, +5 C, +7 C, +85 C V N = V..5 T A = C, C, +5 C, +7 C, +85 C V N = V V LOG V C +5 C +85 C C +7 C ERROR db(mv/db) C +85 C C +5 C +7 C..5 n n n m m. n n n m m TPC. V LOG vs. I PD for Multiple Temperatures TPC. Law Conformance Error vs. I PD (at I REF = ma) for Multiple Temperatures, Normalized to 5 C.8.6 C T A = C, C, +5 C, +7 C, +85 C V N = V..5 T A = C, C, +5 C, +7 C, +85 C V N = V V LOG V C +7 C +5 C +85 C ERROR db(mv/db) C +7 C C +85 C..5 C n n n m m I REF A TPC. V LOG vs. I REF for Multiple Temperatures. n n n m m I REF A TPC 5. Law Conformance Error vs. I REF (at I PD = ma) for Multiple Temperatures, Normalized to 5 C V LOG V na na A A A ma ERROR db(mv/db) A A ma A na na n n n m m.5 n n n m m TPC. V LOG vs. I PD for Multiple Values of I REF (Decade Steps from na to ma) TPC 6. Law Conformance Error vs. I PD for Multiple Values of I REF (Decade Steps from na to ma)

5 AD V LOG V na na A A ma A ERROR db(mv/db) A A ma na na A.. n n n m m I REF A.5 n n n m m I REF A TPC 7. V LOG vs. I REF for Multiple Values of I PD (Decade Steps from na to ma) TPC. Law Conformance Error vs. I REF for Multiple Values of I PD (Decade Steps from na to ma) ERROR db(mv/db) V, V +5V, V +9V, V +V,.5V +5V, 5V +V, V V OUT V A TO ma: T-RISE = < s, T-FALL = < s A TO A: T-RISE = < s, T-FALL = < s A TO A: T-RISE = s, T-FALL = 5 s na TO A: T-RISE = 5 s, T-FALL = s na TO na: T-RISE = s, T-FALL = s.5 n n n m m TPC 8. Law Conformance Error vs. I PD for Various Supply Conditions (see Annotations) TIME s TPC. Pulse Response I PD to V OUT (G = )..6 V SUM V mv..... V OUT V na TO na: T-RISE = s, T-FALL = s na TO A: T-RISE = s, T-FALL = 5 s A TO A: T-RISE = 5 s, T-FALL = < s A TO A: T-RISE = s, T-FALL = < s A TO ma: T-RISE = < s, T-FALL = < s... n n n m m TPC 9. V V SUM vs. I PD TIME s TPC. Pulse Response I REF to V OUT (G = ) 5

6 AD85 na na A V OUT ma A A NORMALIZED RESPONSE db 6 9 A V = 5 A V =.5 A V = A V = 5 k k k M M M FREQUENCY Hz TPC. Small Signal AC Response (5% Sine Modulation), from I PD to V OUT (G = ) for I PD in Decade Steps from na to ma, I REF = ma k k M M M FREQUENCY Hz TPC 6. Small Signal AC Response of the Buffer for Various Closed-Loop Gains (R L = k W C L < pf) NORMALIZED RESPONSE db na na ma A A A V OS DRIFT mv MEAN + MEAN 5 k k k M M M FREQUENCY Hz TPC. Small Signal AC Response (5% Sine Modulation), from I REF to V OUT (G = ) for I REF in Decade Steps from na to ma, I PD = ma TEMPERATURE C TPC 7. Buffer Input Offset Drift vs. Temperature ( to Either Side of Mean) na 5 na Vrms/ Hz A A mvrms. A. k k k M M FREQUENCY Hz n n m m TPC 5. Spot Noise Spectral Density at V OUT (G = ) vs. Frequency for I PD in Decade Steps from na to ma TPC 8. Total Wideband Noise Voltage at V OUT vs. I PD (G = ) 6

7 AD85..5 T A = 5 C 5 ERROR db(mv/db) MEAN + MEAN V REF DRIFT mv MEAN + MEAN.5. n n n m m TEMPERATURE C 8 9 TPC 9. Law Conformance Error Distribution ( to Either Side of Mean) TPC. V REF Drift vs. Temperature ( to Either Side of Mean)..5 MEAN 7 C T A = C, 7 C 5 ERROR db(mv/db) C DRIFT mv 5 5 MEAN + MEAN.5 7 C 5. n n n m m TEMPERATURE C 8 9 TPC. Law Conformance Error Distribution ( to Either Side of Mean) TPC. V REF V Drift vs. Temperature ( to Either Side of Mean) ERROR db(mv/db) MEAN MEAN +85 C T A = C, +85 C V DRIFT mv 5 MEAN + MEAN C n n n m m TEMPERATURE C 8 9 TPC. Law Conformance Error Distribution ( to Either Side of Mean) TPC. V Drift vs. Temperature ( to Either Side of Mean) 7

8 AD85 Vy DRIFT mv/dec MEAN + MEAN COUNT TEMPERATURE C INTERCEPT na TPC 5. Slope Drift vs. Temperature ( to Either Side of Mean of mv/decade) TPC 8. Distribution of Logarithmic Intercept (Nominally na when R REF = kw ±.%) Sample >, MEAN Iz DRIFT pa 5 5 COUNT 5 5 MEAN TEMPERATURE C V REF V TPC 6. Intercept Drift vs. Temperature ( to Either Side of Mean of na) TPC 9. Distribution of V REF (R L = kw) Sample >, COUNT COUNT SLOPE mv/dec V V SUM VOLTAGE V TPC 7. Distribution of Logarithmic Slope (Nominally mv/decade) Sample >, TPC. Distribution of Offset Voltage (V V SUM ) Sample >, 8

9 AD85 GENERAL STRUCTURE The AD85 addresses a wide variety of interfacing conditions to meet the needs of fiber optic supervisory systems, and will also be useful in many nonoptical applications. These notes explain the structure of this unique style of translinear log amp. Figure is a simplified schematic showing the key elements. PHOTODIODE.5V INPUT CURRENT 8k I PD.5V.5V Q BIAS GENERATOR VSUM k V BE.5V I REF Q VNEG (NORMALLY GROUNDED) V BE V BE V BE TEMPERATURE COMPENSATION (SUBTRACT AND DIVIDE BY T K.k 6.69k A/dec 5 Figure. Simplified Schematic The photodiode current I PD is received at Pin. The voltage at this node is essentially equal to those on the two adjacent guard pins, VSUM and, due to the low offset voltage of the JFET op amp. Transistor Q converts the input current I PD to a corresponding logarithmic voltage, as shown in Equation. A finite positive value of V SUM is needed to bias the collector of Q for the usual case of a single-supply voltage. This is internally set to.5 V, that is, one fifth of the reference voltage of.5 V appearing on Pin. The resistance at the VSUM pin is nominally 6 kw; this voltage is not intended as a general bias source. The AD85 also supports the use of an optional negative supply voltage, V N, at Pin VNEG. When V N is.5 V or more negative, VSUM may be connected to ground; thus and assume this potential. This allows operation as a voltage-input logarithmic converter by the inclusion of a series resistor at either or both inputs. Note that the resistor setting I REF will need to be adjusted to maintain the intercept value. It should also be noted that the collector-emitter voltages of Q and Q are now the full V N, and effects due to self-heating will cause errors at large input currents. The input dependent V BE of Q is compared with the reference V BE of a second transistor, Q, operating at I REF. This is generated externally, to a recommended value of ma. However, other values over a several-decade range can be used with a slight degradation in law conformance (TPC ). Theory The base-emitter voltage of a BJT (bipolar junction transistor) can be expressed by Equation, which immediately shows its basic logarithmic nature: V kt/ qin I / I () = ( ) BE C S where I C is its collector current, I S is a scaling current, typically only 7 A, and kt/q is the thermal voltage, proportional to absolute temperature (PTAT) and is 5.85 mv at K. The current, I S, is never precisely defined and exhibits an even stronger temperature dependence, varying by a factor of roughly a billion between 5 C and +85 C. Thus, to make use of the BJT as an accurate logarithmic element, both of these temperature dependencies must be eliminated. The difference between the base-emitter voltages of a matched pair of BJTs, one operating at the photodiode current I PD and the second operating at a reference current I REF, can be written as: VBE VBE kt/ q In IC/ IS kt/ q In / IS = In ( ) kt/ qlog ( IPD / ) 59. 5mV log I / I T K = ( ) ( ) = ( PD REF )( = ) The uncertain and temperature dependent saturation current I S, which appears in Equation, has thus been eliminated. To eliminate the temperature variation of kt/q, this difference voltage is processed by what is essentially an analog divider. Effectively, it puts a variable under Equation. The output of this process, which also involves a conversion from voltage-mode to currentmode, is an intermediate, temperature-corrected current: () ILOG IY log IPD / () = ( ) where I Y is an accurate, temperature-stable scaling current that determines the slope of the function (the change in current per decade). For the AD85, I Y is ma, resulting in a temperatureindependent slope of ma/decade, for all values of I PD and I REF. This current is subsequently converted back to a voltage-mode output, V LOG, scaled mv/decade. It is apparent that this output should be zero for I PD = I REF, and would need to swing negative for smaller values of input current. To avoid this, I REF would need to be as small as the smallest value of I PD. However, it is impractical to use such a small reference current as na. Accordingly, an offset voltage is added to V LOG to shift it upward by.8 V when Pin is directly connected to. This has the effect of moving the intercept to the left by four decades, from ma to na: ILOG IY log IPD / IINTC () = ( ) where I INTC is the operational value of the intercept current. To disable this offset, Pin should be grounded, then the intercept I INTC is simply I REF. Since values of I PD < I INTC result in a negative V LOG, a negative supply of sufficient value is required to accommodate this situation (discussed later). The voltage V LOG is generated by applying I LOG to an internal resistance of.55 kw, formed by the parallel combination of a 6.69 kw resistor to ground and the. kw resistor to the pin. When the pin is unloaded and the intercept repositioning is disabled by grounding, the output current I LOG generates a voltage at the pin of: = ILOG 55. k W = ma. 55 k W log ( IPD/ ) (5) V log I / I = Y ( PD REF ) where V Y = mv/decade, or mv/db. Note that any resistive loading on will lower this slope and also result in an overall scaling uncertainty due to the variability of the on-chip resistors. Consequently, this practice is not recommended. V LOG may also swing below ground when dual supplies (V P and V N ) are used. When V N =.5 V or larger, the input pins and may now be positioned at ground level by simply grounding VSUM. 9

10 AD85 Managing Intercept and Slope When using a single supply, should be directly connected to to allow operation over the entire five-decade input current range. As noted previously, this introduces an accurate offset voltage of.8 V at the pin, equivalent to four decades, resulting in a logarithmic transfer function that can be written as: ( ) LOG Y PD REF V = V log I / I = VY log ( IPD/ IINTC ) where I INTC = I REF / Thus, the effective intercept current I INTC is only one tenthousandth of I REF, corresponding to na when using the recommended value of I REF = ma. The slope can be reduced by attaching a resistor to the pin. This is strongly discouraged, in view of the fact that the on-chip resistors will not ratio correctly to the added resistance. Also, it is rare that one would want to lower the basic slope of mv/db; if this is needed, it should be effected at the low impedance output of the buffer, which is provided to avoid such miscalibration and also allow higher slopes to be used. The AD85 buffer is essentially an uncommitted op amp with rail-to-rail output swing, good load-driving capabilities and a unity-gain bandwidth of > MHz. In addition to allowing the introduction of gain, using standard feedback networks and thereby increasing the slope voltage V Y, the buffer can be used to implement multipole low-pass filters, threshold detectors, and a variety of other functions. Further details of these can be found in the AD8 data sheet. Response Time and Noise Considerations The response time and output noise of the AD85 are fundamentally a function of the signal current I PD. For small currents, the bandwidth is proportional to I PD, as shown in TPC. The output low frequency voltage-noise spectral-density is a function of I PD (TPC 5) and also increases for small values of I REF. Details of the noise and bandwidth performance of translinear log amps can be found in the AD8 Data Sheet. APPLICATIONS The AD85 is easy to use in optical supervisory systems and in similar situations where a wide ranging current is to be converted to its logarithmic equivalent, which is represented in decibel terms. Basic connections for measuring a single-current input are shown in Figure, which also includes various nonessential components, as will be explained. (6) k V BIAS k I PD k VSUM.5V.5V BIAS 8k.5V GENERATOR k SCAL V BE.k I Q LOG TEMPERATURE 5 + Q COMPENSATION VNEG +5V VPOS V BE 6.69k I PD.5 log ( na) k 8k C FLT Figure. Basic Connections for Fixed Intercept Use The V difference in voltage between the and pins in conjunction with the external kw resistor R REF provide a reference current I REF of ma into Pin. Connecting pin to raises the voltage at by.8 V, effectively lowering the intercept current I INTC by a factor of to position it at na. A wide range of other values for I REF, from under na to over ma, may be used. The effect of such changes is shown in TPC. Any temperature variation in R REF must be taken into account when estimating the stability of the intercept. Also, the overall noise will increase when using very low values of I REF. In fixedintercept applications, there is little benefit in using a large reference current, since this only compresses the low current end of the dynamic range when operated from a single supply, here shown as 5 V. The capacitor between VSUM and ground is recommended to minimize the noise on this node and to help provide a clean reference current. Since the basic scaling at is. V/decade, and thus a swing of V at the buffer output would correspond to decades, it will often be useful to raise the slope to make better use of the railto-rail voltage range. For illustrative purposes, the circuit in Figure provides an overall slope of.5 V/decade (5 mv/db). Thus, using I REF = ma, V LOG runs from. V at I PD = na to. V at I PD = ma while the buffer output runs from.5 V to.5 V, corresponding to a dynamic range of db (electrical, that is, 6 db optical power). The optional capacitor from to ground forms a single-pole low-pass filter in combination with the.55 kw resistance at this pin. For example, using a C FLT of nf, the db corner frequency is.5 khz. Such filtering is useful in minimizing the output noise, particularly when I PD is small. Multipole filters are more effective in reducing the total noise; examples are provided in the AD8 data sheet.

11 AD85 The dynamic response of this overall input system is influenced by the external RC networks connected from the two inputs (, ) to ground. These are required to stabilize the input systems over the full current range. The bandwidth changes with the input current due to the widely varying pole frequency. The RC network adds a zero to the input system to ensure stability over the full range of input current levels. The network values shown in Figure will usually suffice, but some experimentation may be necessary when the photodiode capacitance is high. Although the two current inputs are similar, some care is needed to operate the reference input at extremes of current (< na) and temperature (< C). Modifying the RC network to.7 nf and kw will allow operation to C at na. By inspecting the transient response to perturbations in I REF at representative current levels, the capacitor value can be adjusted to provide fast rise and fall times with acceptable settling. To fine tune the network zero, the resistor value should be adjusted. CALIBRATION The AD85 has a nominal slope and intercept of mv/decade and na, respectively. These values are untrimmed and the slope alone may vary as much as 7.5% over temperature. For this reason, it is recommended that a simple calibration be done to achieve increased accuracy. V LOG V UNCALIBRATED ERROR MEASURED OUTPUT IDEAL OUTPUT CALIBRATED ERROR n n n m m Figure. Using Two-Point Calibration to Increase Measurement Accuracy Figure shows the improvement in accuracy when using a twopoint calibration method. To perform this calibration, apply two known currents, I and I, in the linear operating range between na and ma. Measure the resulting output, V and V, respectively, and calculate the slope m and intercept b. m V V / log I log I (7) [ ] = ( ) ( ) ( ) b V m log I (8) = ( ) The same calibration could be performed with two known optical powers, P and P. This allows for calibration of the entire measurement system while providing a simplified relationship between the incident optical power and V LOG voltage. m V V / P P (9) = ( ) ( ) b = V m P () ERROR db(mv/db) The Uncalibrated Error line in Figure was generated assuming that the slope of the measured output was mv/decade when in fact it was actually 9 mv/decade. Correcting for this discrepancy decreased measurement error up to db. USING A NEGATIVE SUPPLY Most applications of the AD85 require only a single supply of. V to 5.5 V. However, to provide further versatility, dual supplies may be employed, as illustrated in Figure. RREF k V BIAS k I PD + V F R S k VSUM V N.5V.5V I q + I SIG 8k.5V k Q Q VNEG I SIG = I PD + I REF 5V VPOS V BE BIAS GENERATOR V BE.k I LOG TEMPERATURE + COMPENSATION V NEG.5V C 6.69k R S.5 log 5 V N V F SCAL I q + I SIGMAX ( ) I PD na k 8k C FLT Figure. Negative Supply Application The use of a negative supply, V N, allows the summing node to be placed at ground level whenever the input transistor (Q in Figure ) has a sufficiently negative bias on its emitter. When V NEG =.5 V, the V CE of Q and Q will be the same as for the default case when VSUM is grounded. This bias need not be accurate, and a poorly defined source can be used. The source does however need to be able to support the quiescent current as well as the and signal current. For example, it may be convenient to utilize a forward-biased junction voltage of about.7 V or a Schottky barrier voltage of a little over.5 V. The effect of supply on the dynamic range and accuracy can be seen in TPC 8. With the summing node at ground, the AD85 may now be used as a voltage-input log amp at either the numerator input,, or the denominator input,, by inserting a suitably scaled resistor from the voltage source to the relevant pin. The overall accuracy for small input voltages is limited by the voltage offset at the inputs of the JFET op amps. The use of a negative supply also allows the output to swing below ground, thereby allowing the intercept to correspond to a midrange value of I PD. However, the voltage V LOG remains referenced to the ACOM pin, and while it does not swing negative for default operating conditions, it is free to do so. Thus, adding a resistor from to the negative supply lowers all values of, which raises the intercept. The disadvantage of this method is that the slope is reduced by the shunting of the external resistor, and the poorly defined ratio of onchip and off-chip resistances causes errors in both the slope and the intercept.

12 AD85 +5V VPOS REFERENCE DETECTOR +5V P REF k I REF I PD.5V k Q 8k Q.5 V V BE + BIAS GENERATOR TEMPERATURE COMPENSATION.k I LOG SCAL 5.k 8.k nf.k 8nF ( ) I PD.5 log + I REF SIGNAL DETECTOR P SIG k VSUM.5V VNEG V BE 6.69k Figure 5. Optical Absorbance Measurement LOG-RATIO APPLICATIONS It is often desirable to determine the ratio of two currents, for example, in absorbance measurements. These are commonly used to assess the attenuation of a passive optical component, such as an optical filter or variable optical attenuator. In these situations, a reference detector is used to measure the incident power entering the component. The exiting power is then measured using a second detector and the ratio is calculated to determine the attenuation factor. Since the AD85 is fundamentally a ratiometric device, having nearly identical logging systems for both numerator and denominator (I PD and I REF, respectively), it can greatly simplify such measurements. Figure 5 illustrates the AD85 s log-ratio capabilities in optical absorbance measurements. Here a reference detector diode is used to provide the reference current, I REF, proportional to the optical reference power level. A second detector measures the transmitted signal power, proportional to I PD. The AD85 calculates the logarithm of the ratio of these two currents, as shown in Equation, and which is reformulated in power terms in Equation. Both of these equations include the internal factor of, introduced by the output offset applied to V LOG via pin. If the true (nonoffset) log ratio shown in Equation is preferred, should be grounded to remove the offset. As already noted, the use of a negative supply at Pin VNEG will allow both V LOG and the buffer output to swing below ground, and also allow the input pins and to be set to ground potential. Thus, the AD85 may also be used to determine the log ratio of two voltages. Figure 5 also illustrates how a second order Sallen-Key low-pass filter can be realized using two external capacitors and one resistor. Here, the corner frequency is set to khz and the filter Q is chosen to provide an optimally flat (overshoot-free) pulse response. To scale this frequency either up or down, simply scale the capacitors by the appropriate factor. Note that one of the resistors needed to realize this filter is the output resistance of.55 kw present at Pin. While this will not ratio exactly to the external resistor, which may slightly alter the Q of the filter, the effect on pulse response will be negligible for most purposes. Note that the gain of the buffer (.5) is an integral part of this illustrative filter design; in general, the filter may be redesigned for other closed-loop gains. The transfer characteristics can be expressed in terms of optical power. If we assume that the two detectors have equal responsivities, the relationship is V = 5. Vlog P / P () ( ) OUT SIG REF Using the identity log (AB) = log A + log B and defining the attenuation as log (P SIG / P REF ), the overall transfer characteristic can be written as = 5mV db a () where a = log ( P P ) SIG REF Figure 6 illustrates the linear-in-db relationship between the absorbance and the output of the circuit in Figure 5. V LOG V ATTENUATION db Figure 6. Example of an Absorbance Transfer Function

13 AD85 REVERSING THE INPUT POLARITY Some applications may require interfacing to a circuit that sources current rather than sinks current, such as connecting to the cathode side of a photodiode. Figure 7 shows the use of a current mirror circuit. This allows for simultaneous monitoring of the optical power at the cathode, and a data recovery path using a transimpedance amplifier at the anode. The modified Wilson mirror provides a current gain very close to unity and a high output resistance. Figure 8 shows measured transfer function and law conformance performance of the AD85 in conjunction with this current mirror interface. MAT MAT I PD 5V. F k TIA k.5v V V I IN I PD na TO ma 6 5. F DATA PATH AD85 VSUM VNEG VNEG VPOS SCAL 5V V OUT =. log (I PD /na) 9 OUTPUT Figure 7. Wilson Current Mirror for Cathode Interfacing V LOG V V +5V 5V. n n n m m +5V +V Figure 8. Log Output and Error Using Current Mirror with Various Supplies 5V ERROR db(mv/db) These measures are needed to minimize the risk of leakage current paths. With.5 V as the nominal bias on the pin, a leakage-path resistance of GW to ground would subtract.5 na from the input, which amounts to an error of. db for a source current of na. Additionally, the very high output resistance at the input pins and the long cables commonly needed during characterization allow 6 Hz and RF emissions to introduce substantial measurement errors. Careful guarding techniques are essential to reduce the pickup of these spurious signals. KEITHLEY 6 KEITHLEY 6 TRIAX CONNECTORS (SIGNAL AND GUARD VSUM SHIELD GROUND) VNEG AD85 CHARACTERIZATION BOARD VPOS VSUM DC MATRIX/DC SUPPLIES/DMM Figure 9. Primary Characterization Setup The primary characterization setup shown in Figure 9 is used to measure V REF, the static (dc) performance, logarithmic conformance, slope and intercept, the voltages appearing at pins VSUM, and, and the buffer offset and V REF drift with temperature. To ensure stable operation over the full current range of I REF and temperature extremes, filter components of C =.7 nf and R = kw are used at pin to ground. In some cases, a fixed resistor between pins and was used in place of a precision current source. For the dynamic tests, including noise and bandwidth measurements, more specialized setups are required. OUTPUT +IN AD88 B EVALUATION BOARD A AD88 PROVIDES DC OFFSET HP 577A NETWORK ANALYZER INPUT R INPUT A INPUT B BNC-T 6 5 AD85 SCAL CHARACTERIZATION METHODS During the characterization of the AD85, the device was treated as a precision current-input logarithmic converter, since it is not practical for several reasons to generate accurate photocurrents by illuminating a photodiode. The test currents were generated either by using well calibrated current sources, such as the Keithley 6, or by using a high value resistor from a voltage source to the input pin. Great care is needed when using very small input currents. For example, the triax output connection from the current generator was used with the guard tied to VSUM. The input trace on the PC board was guarded by connecting adjacent traces to VSUM. VSUM VNEG VNEG VPOS V S. F Figure. Configuration for Buffer Amplifier Bandwidth Measurement Figure shows the configuration used to measure the buffer amplifier bandwidth. The AD88 evaluation board includes

14 AD85 provisions to offset V LOG at the buffer input, allowing measurements over the full range of I PD using a single supply. The network analyzer input impedances were set to MW. OUTPUT HP 577A NETWORK ANALYZER INPUT R INPUT A INPUT B The configuration in Figure is used to measure the noise performance. Batteries provide both the supply voltage and the input current in order to minimize the introduction of spurious noise and ground loop effects. The entire evaluation system, including the current setting resistors, is mounted in a closed aluminum enclosure to provide additional shielding to external noise sources. LECROY 9 CH A 9 TDS5 CH POWER SPLITTER 6 5 +IN AD88 B EVALUATION BOARD A R k R k AD85 VSUM VNEG VNEG VPOS Figure. Configuration for Logarithmic Amplifier Bandwidth Measurement SCAL 9 +V S. F The setup shown in Figure was used for frequency response measurements of the logarithmic amplifier section. The AD88 output is offset to.5 V dc and modulated to a depth of 5% at frequency. R is chosen (over a wide range of values up to. GW) to provide I PD. The buffer was used to deload from the measurement system. HP 89A SOURCE TRIGGER CHANNEL CHANNEL k k R k 6 5 AD SCAL VSUM VNEG VNEG VPOS 9. F Figure. Configuration for Logarithmic Amplifier Pulse Response Measurement Figure shows the setup used to make the pulse response measurements. As with the bandwidth measurement, the is connected directly to and the buffer amplifier is configured for unity gain. The buffer s output is connected through a short cable to the TDS5 scope with input impedance set to MW. The LeCroy s output is offset to create the initial pedestal current for a given value of R, the pulse then creates one-decade current step. +V S 6 5 EVALUATION BOARD An evaluation board is available for the AD85, the schematic for which is shown in Figure 6. It can be configured for a wide variety of experiments. The buffer gain is factory-set to unity, providing a slope of mv/decade, and the intercept is set to na. Table I describes the various configuration options. ALKALINE D CELL + k k R k SCAL AD85 VSUM VNEG VNEG VPOS ALKALINE D CELL. F Figure. Configuration for Noise Spectral Density Measurement

15 Table I. Evaluation Board Configuration Options AD85 Component Function Default Condition P Supply Interface. Provides access to supply pins, VNEG,, and VPOS. P = Installed P, R8, R9, R, Monitor Interface. By adding W resistors to R8, R9, R, R, R7, and R8, P = Not Installed R, R7, R8 the,, VSUM,, and pin voltages can be monitored R8 = R9 = R = Open (Size 6) using a high impedance probe. R7 = R8 = Open (Size 6) R, R, R, R6, R, Buffer Amplifier/Output Interface. The logarithmic slope of the AD85 R = R6 = W (Size 6) C, C7, C9, C can be altered using the buffer s gain-setting resistors, R and R. R, R, R = R = Open (Size 6) and C allow variation in the buffer loading. R6, C7, C9, and C are R = R = W (Size 6) provided for a variety of filtering applications. C = C7 = Open (Size 6) C9 = C = Open (Size 6) = = Installed R, R7, R9, R Intercept Adjustment. The voltage dropped across resistor R determines the R = kw (Size 6) intercept reference current, nominally set to ma using a kw % resistor. R7 = R9 = W (Size 6) R7 and R9 can be used to adjust the output-offset voltage at the output. R = Open (Size 6) R, R5, C, Supply Decoupling. C = C =. F C, C5, C6 (Size 6) C5 = C6 =. F (Size 6) R = R5 = W (Size 6) C VSUM Decoupling Capacitor. C = nf (Size 6) R, R6, C, C8 Input Compensation. Provides essential HF compensation at the input pins, R = R6 = kw (Size 6) and. C = C8 = nf (Size 6),, PD, Input Interface. The test board is configured to accept a current through the = = Installed LK, R5 SMA connector labeled. An SC-style packaged photodiode can be PD = Not Installed used in place of the SMA for optical interfacing. By removing R and LK = Installed adding a W short for R5, a second current can be applied to the input R5 = Open (Size 6) (also SMA) for evaluating the AD85 in log-ratio applications. J SC-Style Photodiode. Allows for direct mounting of SC style photodiodes. J = Not Installed 5

16 AD85 Figure. Component Side Layout Figure 5. Component Side Silkscreen 6

17 AD85 R7 R8 R5 R R7 R k R9 R k I % REF 6 5 AD85 SCAL R R C R6 C C9 R R R R8 SC-STYLE PD C I PD VSUM VNEG VNEG VPOS C7 R LK C R9 R6 C8 k C. F R5 R C. F AGND VSUM C6. F C5. F AGND VNEG VPOS VSUM 5 P 6 P Figure 6. Evaluation Board Schematic 7

18 AD85 OUTLINE DIMENSIONS 6-Lead Leadframe Chip-Scale Package [LFCSP] mm mm Body (CP-6) Dimensions shown in millimeters. BSC SQ.6 MAX.5.. PIN INDICATOR PIN INDICATOR MAX..9.8 SEATING PLANE TOP VIEW BSC SQ.8 MAX.65 NOM.5 MAX. NOM. REF.5.5 BSC.5 REF BOTTOM VIEW COMPLIANT TO JEDEC STANDARDS MO--VEED-.5. SQ.5.5 MIN 8

19 AD85 Revision History Location Page / Data Sheet changed from REV. to. Changes to TPC Changes to TPC Changes to Figure Changes to Figure Updated OUTLINE DIMENSIONS

20 PRINTED IN U.S.A. C5 /(A)