Design Problem 1 Solutions

Transcription

1 CS/EE 260 Digital Computers: Organization and Logical Design Design Problem 1 Solutions Jon Turner 2/6/02 General notes for design problems. The design problems are intended to give you the opportunity to apply what you ve learned in the course to larger problems and to gain some experience with the kind of CAD tools used by professional digital systems designers. You should strive to find the best possible design for the given problem and to make your solutions complete, easy for someone else to understand and well-documented. The work you turn in should include copies of your design notes, explaining how you arrived at a particular design, as well as the actual design itself. Schematics should be well-organized, with components arranged so that it is easy to see what is connected to what. VHDL code should be organized neatly, with appropriate use of indenting, mnemonic signal names and comments to explain various sections of code. Simulation output should be complete and should include notations highlighting any particular items of interest. Unusual simulation output should be noted and explained. This is your opportunity to demonstrate that you have mastered the material and can apply it to solve creative design challenges. You will be judged on the professionalism you demonstrate in the work that you turn in, not just on whether you ve met the minimum requirements for the problem. 1. (30 points) Design and simulate a palindrome detection circuit. Specifically, your circuit will have five inputs a0,...,a4 and five outputs x0,...,x4. Output xi should be high, if the bit string a0,...,ai is a palindrome (reads the same, forwards and backwards). Write logic equations for each of the outputs and find a design for the circuit that uses the smallest possible number of gates (use only inverters plus 2 input AND gates and OR gates). Use the schematic editor to create a schematic of the circuit and perform a functional simulation that shows what the output is under all possible input conditions. Turn in a copy of your design notes, the schematic and the simulation output. Make sure that the text on all the printouts is clearly legible. There is an easy way to create the required input pattern using the HDL Bencher tool. By double-clicking on any cell in the main waveform display area, you can bring up a pattern box. Clicking on the word pattern gives you a dialog box that you can use to create repeating patterns. Use this to create a repeating 0101 pattern for a0, pattern for a1, for a2, and so forth. The specification requires that output xi should be high, if the bit string a0,...,ai is a palindrome, that is, if a0=ai, a1=ai-1, and so forth. Two signals are equal if they are either both high or both low. Since the circuit has five inputs and five outputs, the logic equations for the outputs are - 1 -

2 x0= 1 x1= a0 a1+ a 0 a 1 x2= a0 a2+ a 0 a 2 x3= (a0 a3+ a 0 a 3) (a1 a2+ a 1 a 2) x4= (a0 a4+ a 0 a 4) (a1 a3+ a 1 a 3) The schematic shown below implements these logic circuits directly. Identifying text strings have been added next to the input and output pins for improved legibility

3 The simulation results for the circuit are shown below. Two points are highlighted with cursors as examples. At the first cursor position, the input is the binary string 00100, which is a palindrome. Also, the first bit forms a palindrome and the first two bits form a palindrome, so the output is At the second cursor position, the input is the binary string 10101, which is a palindrome. Also, the first bit forms a palindrome and the first three bits form a palindrome, so the output is

4 2. (30 points) Design and perform a behavioral simulation of a range-detect circuit. Your circuit has four inputs a3, a2, a1 and a0 which will be treated as a singed binary value in 2scomplement notation (bit a3 is the sign bit). Your circuit will have 3 outputs. Output x is high if the input value is in the range 8 to 3, output y should be high if the input value is in the range 3 to +1 and output z should be high if the input value is in the range +2 to +5. Create a truth table for the outputs and use this to determine the required set of logic equations. Try to find the simplest equations you can (the ones that will produce a design with the minimum number of gates) and design a circuit that implements the equations (use only inverters plus 2 input AND gates and OR gates). Enter your schematic using the schematic editor and demonstrate that it works correctly by performing a behavioral simulation. Make sure that your input goes through all the possible input values for the circuit. Turn in a copy of your design notes the schematic and the simulation output. Make sure that the text on all the printouts is clearly legible. The truth table shown below lists the 16 different input combinations in numerical order, with the rows labeled with the corresponding numerical value. This makes it easy to see which input combinations define each of the three ranges. The logic equations were determined by inspection of the truth table, taking advantage of all opportunities to group sub-expressions to reduce the complexity of the resulting circuit. a 3 a 2 a 1 a 0 xyz -8= = = = = = = = = = = = = = = = x=a 3 (a 1 + a 2) y=a 3 a 2 (a 0 + a 1 ) + a 3a 2a 1 z=a 3(a 2 a 1 + a 2a 1 ) - 4 -

5 The schematic that appears below, implements the given logic equations directly

6 The results from the behavioral simulation appear below. Note that the input values are represented in numerical order, to make it obvious that the output signal values are correct. The input signals were combined into one composite signal using the combine signals item in the Tools menu. To make this work properly, the signals have to be arranged from most significant bit (top) to least significant bit, before combining the signals. The output values are shown as signed decimal values by selecting the decimal option from the Format=>Radix menu