CMOS ASYNCHRONOUS COMMUNICATIONS INTERFACE ADAPTER

Transcription

1 CALIFORNIA MICRO DEICES CMOS ASYNCHRONOUS COMMUNICATIONS INTERFACE ADAPTER FEATURES CMOS process technology for low power coumption 5 programmable baud rates (5 to 9,2 baud) External 6X clock input for notandard baud rates to 25, baud Programmable interrupt and status registers Fullduplex or halfduplex operating modes Selectable 5, 6, 7, 8 or 9 bit tramission rates Programmable word length, parity generation and detection, and number of stop bits Programmable parity optio odd, even, none, mark or space Includes data set and modem control signals False start bit detection Serial echo mode Four operating frequencies, 2, 3 and 4 MHz GENERAL DESCRIPTION The CM D is an Asynchronous Communicatio Interface Adapter which offers m any versatile features for interfacing 65/68 microprocessors to serial communication data sets and modems. The s most significant feature is its internal baud rate generator, allowing programmable baud rate selection from 5 to 9,2 baud. This full range o f baud rates is derived from a single standard.8432 M H z external crystal. F or notandard baud rates up to 25, baud, an external 6X clock input is provided. In addition to its powerful communicatio control features, the offers the advantages o f C M D s leading edge CM OS technology, i.e., increased noise immunity, higher reliability, and greatly reduced pow er coumption. Block Diagram <2 R/W CSO CS RS RS RES DB DB7 2 California Micro Devices Corp. All rights reserved. C794 6/co 2 5 Topaz Street, Milpitas, California 9535 A Tel: (48) A Fax: (48) A

2 CALIFORNIA MICRO DEICES Absolute Maximum Ratings: (See Note) Rating Supply oltage Input oltage Operating Temperature Storage Temperature Symbol vdd w ta Ts This device contai input protection agait damage due to high static voltages or electric fields; however, precautio should be taken to avoid application of voltages higher than the maximum rating. Note: Exceeding these ratings may cause permanent damage, functional operation under these conditio is not implied. alue.3 to to DD C to + 85 C 55 C to +5 C DC Characteristics: DD = 5. ± 5 %, =, TA = 4 C to +85 C Industrial, C to +7 Commercial P aram eter Input High oltage (Except XTAL) Input High oltage (XTAJL only) Input Low oltage (Except XTAL) Input Low oltage (XTAL only) Input Leakage Current (w = to DD), Input Only Pi ThreeState Leakage Current, (m =.4 to 2.4) Output Low oltage (IOL = 3.2mA) Output High oltage (IOH = 2/iA) Supply Current f = MHz (No Load) f = 2MHz f = 3MHz f = 4MHz Power Dissipation (Inputs ^ or DD, No Loads), Operating (DD = 5.5, f = MHz) Standby (Static) Input Capacitance (f = MHz) Output Capacitance (f = MHz) Symbol Min Max IH DD +.3 ^!HX jl,u IlN I'rsi OL oh Iqd Unit.8.9 ±. ±..4 fik ma E.O ma ma ma ma. raw /iw 2.4 I dd I dd I dd Pd P dsb C in C qut pf pf AC Characteristics Processor Interface Timing: DD = 5. ± 5 %, B =, TA 4 C to +85 C Industrial, C to!7 C Commercial Parameter Cycle Phase Phase Phase Time 2 Pulse Width High 2 Pulse Width Low 2 Traition Symbol Max Min 2 Max Min Max Unit f *ACR 6 *CYC PWH Wl 4 Min Max Min 2 Read Timing Select, R/W* Setup Select, R/W* Hold Data Bus Delay Data Bus Hold *CAR tcdr *!«Write Timing Select R/W* Setup *ACW 65 Select R/W* Hold tcaw Data Bus Setup ^DCW W Data Bus Hold 2 California Micro Devices Corp. All rights reserved Topaz Street, M ilpitas, California A Tel: (48) A Fax: (48) A icro.com s/oo

3 CALIFORNIA MICRO DEICES AC Characteristics Tramit/Receive Timing: DD = 5. ±5%, M =, TA = 4 C to +85 C Industrial, C to +7 C Commercial Parameter Symbol Min Max Min Max Min Max Min Max Unit Tramit/Receive Clock Cycle Time *CCY Tramit/Receive Clock High Time *CH Tramit/Receive Clock Low Time ^CL XTAL to TxD Propagation Delay *D D Propagation Delay (RTS*, DTR*) ^DLY IRQ* Propagation Delay (Clear) t'.ro () The baud rate with external clocking is Baud Rate = 6 x tf.j.y (2) Propagation Delay is a function of external RC time cotant. Figure. Read Timing Note: oltage ievels shown are.4, IH ;> 2.4. Figure 2. Write Timing 2 California Micro Devices Corp. All rights reserved. S/oo 2 5 Topaz Street, Milpitas, California 9535 A Tel: (48) A Fax: (48) A 3

4 A CALIFORNIA MICRO DEICES Timing Diagrams (cont.) NOTE:, TxD Is /6 TxC rale, 2. XTAL input voltage IL <.5, ih.j; 3.5. Figure 3. Tramit Timing External Clock Figure 4. Interrupt and Output Timing RkC (INPUT) NOTE:. RxD rate Is /6 RxC rate. 2. oltage levels shown are il «.4, ih m 2.4. Figure 5 Receive External Clock Timing Test and Crystal Specificatio. Temperature stability ±.% (4 C to +85 C) 2. Characteristics at 25 C ± 2 C a. Frequency (MHz).8432 b. Frequency tolerance (±%).2 c. Resonance mode Series d. Equivalent resistance (ohm) 4 max. e. Drive level (mw) 2 f. Shunt capacitance (pf) 7 max. g. Oscillation mode Fundamental Clock Generation ^ XTAL 6 EXTERNAL XTAL CLO CK ~ ~ XTAL2 OPEN XTAL2 C IRCUIT 3pF... 6 INTERNAL CLOCK EXTERNAL CLOCK Test Load 5. OPEN DRAIN OUTPUT TEST LOAD oo PIN * Denotes inverted signal. 2 California Micro Devices Corp. All rights reserved Topaz Street, Milpitas, California 9535 A Tel: (48) A Fax: (48) A 5/

5 CALIFORNIA MICRO DEICES Signal Description (Microprocessor Interface) Signal Description (Communication Interface) Reset (RES*) Tramit Data (TxD) Reset clears all internal registers during system initialization. TxD is an output line used to trafer NRZ (NonRetumtoZero) data to a modem. The LSB (Least Significant Bit) of the Tramit Data Register is the first data bit tramitted. The rate of data tramission (baud rate) is determined by the selected baud rate. Interrupt Request (IRQ*) The Interrupt Request (IRQ*) output signal is generated by the Interrupt Control Logic. IRQ* is normally held to a high level and goes low when an interrupt occurs. IRQ* is an opendrain output, thus allowing the IRQ* signal to be wireored to a common microprocessorlnterrupt input line. Read/Write (R/W*) The R/W* signal is generated by the microprocessor and is used to control the trafer of data between the and the microprocessor. When R/W* is in the high state (Logic ) and the chip is selected, data is traferred from the to the microprocessor (Read operation). Conversely, when R/W* is in the low state (Logic ), data is traferred from the processor to the (Write operation). Receive Data (RxD) RxD is an input line used to receive NRZ input data from a modem. The LSB is always the first data bit received. Received data will always be at the s internally programmed baud rate or the baud rate of an externally generated receiver clock. The baud rate is a selection which is made by programming the Control Register. See Figure 6, Control Register Format. ' Receive Clock (RxC) Input Clock (2) RxC serves as a bidirectional "pin" which can be either the 6X Clock Input or the receiver 6X Clock Output. The 6X Clock Output mode results if the internal baud rate generator is selected for External Receiver Clocking. See Figure 6, Control Register Format. The 4>2 clock is used to trigger all data trafers between the microprocessor and the. Request to Send (RTS*) Data Bus (DBDB7) RTS* is an output line used as a control function to the modem. The state of RTS* is determined by the contents of the Command Register. Refer to Figure 7, Command Register Format. The eight bidirectional Data Bus lines are used to trafer data between the and the microprocessor. During a Read operation, data is traferred from the to the microprocessor. During a Write operation, the Data Bus lines serve as high impedance inputs over which data is traferred from the microprocessor to the. The Data Bus lines are in the high impedance state when the is uelected. Chip Select (CSO, CS*) The two Chip Select lines are normally connected to the processor address lines either directly or through decoders. To access a selected, CSO must be high (Logic ) and CS* must be low (Logic ). " ' " Register Select (RSO, RSI) The two Register Select lines are normally connected to the processor address lines. This allows the processor to select the various internal registers. Refer to Table for internal register select coding. RSO W rite Tramit Data Register Programmed Reset (Data is "Don t Care") NOTE: If Command Register Bit is a high (Logic ) and a change of state on DCD* occurs, IRQ* will be set, and the Status Register Bit 5 will reflect the new level. The state of DCD* does not affect Tramitter operation, but must be low (Logic ) for the Receiver to operate. Clear to Send (CTS*) CTS is an input used to control Tramitter operation. The Tramitter is enabled when CTS* is low (Logic ), and is automatically disabled when CTS* is high (Logic ). Table. Register Select Coding RSI Data Carrier Detect (DCD*) DCD* is an input line used to indicate carrierdetect output status from the modem. A low level indicates the modem earner signal is present, and a high level indicates the modem carrier signal is not present. DCD* is a high impedance input and must not be used as a noconnect. That is, if unused, this pin must be driven high or low, but not switched. Read Data Terminal Ready (DTR*) Receiver Data Register DTR is an output line used to indicate status to the modem, and is controlled by the processor via Bit of the Command Register. DTR* low (Logic ) indicates the is enabled, while DTR* high (Logic ) indicates the device is disabled. Status Register Data Set Ready (DSR*) Command Register Control Register Note that only the Command and Control Registers can be accessed during both Read and Write operatio. Programmed Reset operation does not cause data trafer, but is used to clear (reset) all internal registers. Programmed Reset is used in a slightly different way as compared to the hardware Reset (RES*). These differences are described under each individual register description. DSR* is an input line used to indicate modem status to the. DSR* low (Logic ) indicates the modem is "ready", while a high (Logic ) indicates the modem is in a "not ready" state. Like DCD, DSR is a high impedance input and must not be used as a noconnect. If unused, this line must be driven either high or low, but not switched. NOTE: If Command Register Bit is high (Logic ) and a change of state on DSR* occurs, IRQ* will be set, and Status Register Bit 6 will reflect the new level. The state of DSR* does not affect either Tramitter or Receiver operation. * D e n o tes in v e rte d sig n al. 2 California Micro Devices Corp. All rights reserved. s/co 25 Topaz Street, M ilpitas, California A Tel: (48) A Fax: (48) A w w w.calm icro.com 5

6 ACALIFORNIA MICRO DEICES 7 S STOP BITS = Stop Bit = 2 Stop Bits Stop B it if Word Length = 8 Bits and Parity* /j Stop Bits it W ord Length = 5 B its and No Parity WORD LENGTH BIT 6 5 DATA WORD LENGTH RECEIER CLOCK SOURCE = External Receiver C lock } = Baud Rate Generator BAUD RATE GENERATOR 6x EXTERNAL CLOCK 5 BAUO ,58 5 t t 'T h is allow s fo r 9bit tramission (8 data bits plus parity). HARDWARE RESET PROGRAM RESET Figure 6 Control Register Format PARITY CHECK CONTROLS BIT OPERATION Parity Disabled No Parity Bit Generated No Parity Bit Received t Odd Parity Receiver and Tramitter Even Parity Receiver and Tram itter t M ark Parity B it Tramitted, Parity Check Disabled Space Parity Bit Tram itted, Parity Check Disabled NO RM A L/ECH O MOOE FOR RECEIER = Norm al = Echo (B its 2 and 3 m ust be "") BIT 3 2 TRANSMIT INTERRUPT DATA TERMINAL READY = Disable Receiver and All Interrupts (DTR high) = Enable Receiver and All Interrupts (DTR low) RECEIER INTERRUPT ENABLE = IRQ Interrupt Enabled from Bit 3 of Status Register = IRQ Interrupt Disabled TRANSM ITTER CONTROLS RTS LEEL TRANSMITTER Disabled High O ff Enabled Low On Disabled Low On Disabled Low Tramit BRK HARDWARE RESET PROGRAM RESET Figure 7 Command Register Format * Denotes inverted signal. 2 California Micro Devices Corp. All rights reserved Topaz Street, Milpitas, California 9535 A Tel: (48) A Fax: (48) A 5/oo

7 A CALIFORNIA MICRO DEICES External Crystal Pi (XTAL, XTAL2) These two crystal pi are normally used to connect an external crystal (.8432 MHz) to the internal baud rate generator. This crystal is used to derive the full range of available baud rates. For notandard baud rates, an externally generated clock may be connected to the XTAL pin. In this case, the XTAL2 pin must float. Internal Functio Figure 8 shows the Tramitter/Receiver sectio of the. Bits 3 of the Control Register are used to select the "divisor" which in turn generates the selected baud rate for the Tramitter. Should the Receiver clock be using the same baud rate as the Tramitter, then RxC becomes an output pin and can be used to slave other circuits to the Command Register The Command Register is used to control Tramit/Receive functio. Refer to Figure 7, Command Register Format, for detailed operation and programming information. Tramit and Receive Data Registers The Tramit and Receive Data Registers are used as temporary data storage within the. Tramit Data Register characteristics are as follows: Bit is always the leading bit during any tramission. Unused data bits are always the highorder bits in the data word. These unused highorder bits are "don t care during data tramission. Receive Register characteristics are as follows: Bit is always the leading bit during any tramission. Unused data bits are always the highorder bits and are "zeros" for the receiver. Parity bits are not stored in the Receive Register. The parity bits are stripped off after being used for external parity checking. Therefore, received data in the Receive Data Register will have all parity and unused highorder bits as "zeros". Figure 9 shows an example of a tramitted or received data word which contai eight data bits, a parity bit and a single stop bit. Status Register The Status Register indicates to the processor the status of various functio. Refer to Figure for detailed Status Register operation and programming information. MARK" "MARK" Figure 8, Tramitter/Receiver Clock Circuits P / DATA BITS Control Register The Control Register selects the various operating modes for the G66SC5. Note that the Baud Rate Generator, word length, number of stop bits and Receiver Clock Source are all controlled by the Control Register. Refer to Figure 6, Control Register Format, for detailed operation and programming information. PARITY B IT START BIT STOP BIT Figure 9. Serial Data Stream Example STATUS SET BY CLEARED BY Parity E rro r' = No E rror = Error Self C le a rin g Fram ing E rror" = No E rror = Error Self C le aring O v e rru n ' = No E rror = Error S e lfc le a rin g Receive Data R egister Full = N ot Full = Full Read Receive Data Register Tram it Data R egister Em pty = Not Em pty Em pty W rite Tramit Data Register DCD = DCD Low = DCD High N ot Resettable Reflects DCD State DSR = DSR Low = DSR H igh N ot Resettable Reflects DSR State IRQ = No In te rru p t = Interru pt Read Status Register 'N O IN TERR U PT G EN E R A T E D FO R T H E SE C O N D IT IO N S "C L E A R E O AU TO M A TIC A LLY A FT ER A R E A D O F R D R A N D T h E N EXT E R R O R F R E E R E C E IP T O F OATA HARDWARE RESET PROGRAM R69CT Figure. Status Register Format * Denotes inverted signal. 2 California Micro Devices Corp. All rights reserved. s/oo 2 5 Topaz Street, M ilpitas, California A Tel: (48) A Fax: (48) A ww w.calinicro.com 7

8 CALIFORNIA MICRO DEICES Pin Function Table CSO, CS RES <t>2 R/W IRQ RSO, RS XTAL, XTAL2 TxD RxD Chip Select Reset Input Clock Read/Write Interrupt Request Register Selects Crystal Inputs Tramit Data Receive Data RxC RTS CTS DTR DSR DCD DBDB7 d d ss Receive Clock Request to Send Clear to Send Data Terminal Ready Data Set Ready Data Carrier Detect Data Bus Positive Power Supply (+5. volts) Internal Logic Ground Pin Configuration vss d 28 I D R/W c s o d 2 27 Z 3 <62 c s i d 3 26 Z 3 IRQ RES d 4 25 Z 3 DB7 RxC d 5 24 H I DB6 XTAL d 6 23 I D DB5 7 XTAL2 d 22! DB4 H T 5 d 8 2 H J DB3 C TS d S 2 Z D DB2 T xd d 9 Z D DB D TR d 8 Z J DB RxD d DSR RSO d 3 6 Z 3 DCD r s i c r do RES RxC 4 * XTAL 6 XTAL2 7 RTS 8 CTS 9 TxD DTR CM I CO b CO o * <o co i l l 5 tr II O P S q IQ Q 25 DB7 24 DB6 23 DBS 22 D 4 2 DB3 2 DB2 9 DB 2 California Micro Devices Corp. All rights reserved Topaz Street, Milpitas, California 9535 A Tel: (4 8 ) A Fax: (48) A 5 /

9 ACALIFORNIA MICRO DEICES Packaging Information Ceramic Package Plastic & Cerdip Package A _ 28PIN P A C K A G E [ 26 [ 2 27 [ 3 26 [ «25 C ! T o r 28 z r 2 27 c O j 3 26 C l 4 25 <L 8 " c g : T S Y M B O L IN C H E S M IL L IM E T E R S M IN M A X M IN M A X A _ b bi c D E e BSC 2.54 BSC L Li Q S S 5 _.3 _ S2.5.3 _ E a 5 5 H Plastic Leaded C hip C arrier 28LEAD CARRIER SYM INCHES MILLIMETERS BOL MIN MAX MIN MAX A A C 2.5 D, D D2.3 REF 7.62 BSC E E E e.5 TYP.27 TYP J.2 _.5 J M N P.3.2, N NO. LEADS 2 California Micro Devices Corp. All rights reserved. s/oo 2 5 Topaz Street, Milpitas, California 9535 A Tel: (48) A Fax: (48) A 9

10 CALIFORNIA MICRO DEICES Ordering Information Description C Special G Standard Product Identification Number Pacxage JG 65SC5 P Plastic E Leaded C hip Carrier C C eram ic L Lsadless C hip C arrier D C erd ip X Dice Temperature/Processing None C to 7 C I 4 C to 85=C Performance Designator D esignators selected for speed and power specificatio. t M H z 3 3 MHz 2 2 MHz 4 4 MHz Warning MOS Circuits are subject to damage from static discharge. Internal static discharge circuits are provided to minimize part damage due to environmental static electrical charge build ups. Industry established recommendatio for handling MOS circuits include:. Ship and store product in conductive shipping tubes or in conductive foam plastic. Never ship or store product in nonconductive plastic containers or nonconductive plastic foam material, 2. Handle MOS parts only at conductive work statio. 3. Ground all assembly and repair tools. P I Disclaimer No respoibility is assumed by California Micro Devices Corp. for use of this product aor for any infringements o f patents and trademarks or other rights of third parties resulting from its use. No licee is granted under any patents, patent rights or trademarks o f California M icro Devices Corp. California Micro Devices Corp. reserves & right to make changes in specificatio at any time w ithout notice. NOTES: 2 California Micro Devices Corp. All rights reserved. 25 Topaz Street, Milpitas, California 9535 A Tel: (48) A Fax: (48) A 5 /