MPC5125. MPC5125 Microcontroller Data Sheet. Freescale Semiconductor Data Sheet: Technical Data. Document Number: MPC5125 Rev.

Transcription

1 Freescale Semiconductor Data Sheet: Technical Data Document Number: MPC5125 Rev. 3, 11/2009 MPC5125 MPC5125 Microcontroller Data Sheet 324 TEPBGA 23 mm x 23 mm The MPC5125 integrates a high performance e300 CPU core based on the Power Architecture Technology with a rich set of peripheral functions focused on communications and systems integration. Major features of the MPC5125 are as follows: e300 Power Architecture processor core (enhanced version of the MPC603e core), operates as fast as 400 MHz Low power design Display interface unit (DU) DDR1, DDR2, low-power mobile DDR (LPDDR), and 1.8 V/3.3 V SDR memory controllers 32 KB on-chip SRAM USB 2.0 TG controller with ULP interface DMA subsystem Flexible multi-function external memory bus (EMB) interface NAND flash controller (NFC) LocalPlus interface () 10/100Base Ethernet MMC/SD/SD card host controller (SDHC) Programmable serial controller (PSC) nter-integrated circuit ( 2 C) communication interfaces Controller area network (CAN) J1850 byte data link controller (BDLC) interface n-chip real-time clock (RTC) n-chip temperature sensor C dentification module (M) This document contains information on a product under development. Freescale reserves the right to change or discontinue this product without notice. Freescale Semiconductor, nc., All rights reserved.

2 1 rdering nformation MPC5125 Block Diagrams Pin Assignments ball TEPBGA Pin Assignments Pin Muxing and Reset States Power and Ground Supply Summary Electrical and Thermal Characteristics DC Electrical Characteristics Absolute Maximum Ratings Recommended perating Conditions DC Electrical Specifications Electrostatic Discharge Power Dissipation Thermal Characteristics scillator and PLL Electrical Characteristics System scillator Electrical Characteristics RTC scillator Electrical Characteristics System PLL Electrical Characteristics e300 Core PLL Electrical Characteristics AC Electrical Characteristics verview AC perating Frequency Data Resets External nterrupts S (DDR) Table of Contents NFC FEC USB ULP MMC/SD/SD Card Host Controller (SDHC) DU CAN C J PSC GPs and Timers Fusebox EEE (JTAG) System Design nformation Power Up/Down Sequencing System and CPU Core AV DD Power Supply Filtering Connection Recommendations Pullup/Pulldown Resistor Requirements Pulldown Resistor Requirements for TEST Pin JTAG JTAG_TRST e300 CP / BDM nterface Package nformation Package Parameters Mechanical Dimensions Product Documentation Revision History Freescale Semiconductor

3 rdering nformation 1 rdering nformation Qualification status Core code MPC 5125 YVN 400 R Device number Temperature range Package identifier perating frequency (MHz) Tape and reel status Temperature Range Y = 40 C to 125 C, junction Package dentifier VN = 324 TEPBGA Pb-free perating Frequency 400 = 400 MHz Tape and Reel Status R = Tape and reel (blank) = Trays Note: Not all options are available on all devices. Refer to Table 1. Figure 1. MPC5125 rderable Part Number Description Table 1 shows the orderable part numbers for the MPC5125. Table 1. MPC5125 rderable Part Numbers Qualification Status P = Pre qualification M = Fully spec. qualified, general market flow S = Fully spec. qualified, automotive flow Freescale Part Number 1 Package Description Speed (MHz) perating Temperature 2 Max 3 (f MAX ) Min (T L ) Max (T H ) MPC5125YVN400 MPC TEPBGA package Lead-free (PbFree) 400 MHz core 200 MHz bus NTES: 1 All packaged devices are PPC5125, rather than MPC125, until product qualifications are complete. 2 The lowest ambient operating temperature (T A ) is referenced by T L ; the highest junction temperature is referenced by T H. 3 Maximum speed is the maximum frequency allowed including frequency modulation (FM). 40 C 125 C Freescale Semiconductor 3

4 MPC5125 Block Diagrams 2 MPC5125 Block Diagrams Figure 2 shows a simplified MPC5125 block diagram. Functionally Multiplexed Display SDR, Mobile DDR, DDR1/2 Memory EMB NFC DU Multi-Port Memory Controller FEC1 FEC2 TempSensor Fuse PMC 66 MHz P BUS 200 MHz CSB Bus (64 bits) MPC KB SRAM e300 Power Architecture 32 KB instruction / 32 KB data cache 200 MHz AHB (32 bits) USB1 ULP USB2 ULP DMA 64-Channel JTAG/CP Clock/Reset PC WDT GPT 2 GP 2 2 C 3 CAN 4 J1850 SDHC 2 PSC 10 RTC Figure 2. Simplified MPC5125 Block Diagram 4 Freescale Semiconductor

5 Pin Assignments 3 Pin Assignments This section details pin assignments ball TEPBGA Pin Assignments Figure 3 shows the 324-ball TEPBGA pin assignments A VSS VSS EMB_A D01 EMB_A D00 GP01 GP02 RTC_X TAL RTC_X TAL SYS_X TAL SYS_X TAL AVDD_ SPLL PSC0_ 1 PSC0_ 2 VDD_ PSC1_ 4 CAN2_ TX HRESE T_B SRESE T_B 2C1_S DA MCAS_ B MWE_B VSS B VSS EMB_A D05 EMB_A D03 EMB_A D02 J1850_ TX GP00 VSS CAN2_ RX VDD_ AVSS_ SC_T MPS_S PLL AVSS_ CPLL VDD_ PSC0_ 3 PSC1_ 2 CAN1_ TX TD VDD_ 2C1_S CL VDD MEM MA15 MA14 MA11 C EMB_A D11 EMB_A D09 EMB_A D07 EMB_A D06 VDD_ J1850_ RX GP03 HB_M DE_B CAN1_ RX AVDD_ SC_T MPS PSC0_ 0 PSC1_ 0 PSC1_ 1 VDD_ TD TCK PRES ET_B MCKE MRAS_ B MA12 VDD MEM MA09 D TMPS_ ANAVZ EMB_A D10 VDD_ AVDD_ FUSEW R EMB_A D04 PSC_M CLK_N VSS VBAT SPLL_A NAVZ AVDD_ CPLL PSC0_ 4 VSS PSC1_ 3 TEST TMS TRST_ B VDD MEM MCS_B VDD MEM MA13 MA08 MA06 E EMB_A D15 EMB_A D13 EMB_A D12 EMB_A D08 MA10 MA07 MA04 MA03 F EMB_A D21 VDD_ EMB_A D16 VSS MA02 MA05 VSS MA01 G EMB_A D25 EMB_A D18 EMB_A D17 VDD_ TP DWN VEW VDD MEM MA00 MBA2 MCK_B H EMB_A D28 VDD_ EMB_A D20 EMB_A D14 MBA0 MBA1 VDD MEM MCK J EMB_A D31 EMB_A D26 EMB_A D23 EMB_A D19 VSS VDD VDD VDD VDD VSS MDT MDQ31 MDQ30 MDQ29 K EMB_A X00 VSS EMB_A D24 EMB_A D22 VSS VSS VSS VSS VSS VDD MVTT3 MDQ28 VSS MDM3 L _A X03 EMB_A X02 EMB_A D29 VSS VDD VSS VSS VSS VSS VDD VSS MDQ26 MDQ27 MDQS3 M _C S0_B VDD_ EMB_A D30 EMB_A D27 VDD VSS VSS VSS VSS VDD MVTT2 MDQ23 MDQ24 MDQ25 N NFC_R B _ E_B _R WB EMB_A X01 VSS VSS VSS VSS VSS VDD MVREF MDQ20 VSS MDQ22 P NFC_C E0_B VSS _A CK_B VSS VSS VDD VDD VDD VDD VSS VDD MEM MDQ18 MDQS2 MDQ21 R SDHC1 _D2 SDHC1 _D3 VDD C LK MVTT1 MDQ16 VDD MEM MDM2 T SDHC1 _CLK SDHC1 _CMD SDHC1 _D0 SDHC1 _D1 VDD MEM MDQ13 MDQ17 MDQ19 U FEC1_ CRS VSS FEC1_ CL 2C2_S DA MDQ07 MDQS1 VSS MDQ15 V FEC1_ MDC FEC1_ MD VDD_ 2C2_S CL VDD MEM MDQ10 MDM1 MDQ14 W FEC1_ TX_CL K FEC1_ TX_ER FEC1_ TXD_1 FEC1_ TXD_0 VDD_ USB1_ STP USB1_ DR VSS USB1_ DATA1 VSS DU_HS YNC VSS DU_LD 08 DU_LD 13 VDD_ DU_LD 21 VSS MVTT0 VDD MEM MDQ06 MDQ11 MDQ12 Y FEC1_ TXD_3 VSS FEC1_ TX_EN FEC1_ RXD_2 FEC1_ RX_ER USB1_ DATA6 USB1_ DATA5 USB1_ CLK USB1_ DATA0 DU_LD 01 DU_LD 03 DU_LD 07 DU_LD 10 DU_LD 14 DU_LD 17 DU_LD 22 DU_VS YNC MDQ01 MDM0 MDQ05 VDD MEM MDQ09 AA FEC1_ TXD_2 FEC1_ RXD_3 FEC1_ RXD_1 VDD_ USB1_ NEXT VSS USB1_ DATA4 DU_DE VDD_ DU_LD 02 DU_LD 04 VDD_ DU_LD 11 VDD_ DU_LD 16 VDD_ DU_LD 23 VSS MDQ02 MDQS0 MDQ04 MDQ08 AB VSS FEC1_ RXD_0 FEC1_ RX_DV FEC1_ RX_CL K USB1_ DATA7 USB1_ DATA3 USB1_ DATA2 DU_CL K DU_LD 00 DU_LD 05 DU_LD 06 DU_LD 09 DU_LD 12 DU_LD 15 DU_LD 18 DU_LD 19 DU_LD 20 VDD_ MDQ00 VDD MEM MDQ03 VSS Figure 3. Ball Map for the MPC TEPBGA Package Freescale Semiconductor 5

6 6 3.2 Pin Muxing and Reset States Table 2 provides the pinout listing for the MPC5125. Pin Pad Control Register 1 and ffset 2 Table 2. MPC5125 Pin Multiplexing Alternate Function 3 Functions 4 Peripheral 5 Direction Power Domain Notes Pin Pin Assignments Freescale Semiconductor MPC5125 Microcontroller Data Sheet Data Sheet, Rev. 3 GP00 GP01 GP02 GP03 RTC_XTAL RTC_XTAL HB_MDE GP00 GP01 GP02 GP03 RTC_XTAL RTC_XTAL HB_MDE GP1 GP1 GP1 GP1 RTC RTC RTC Analog Visible Signal VBAT VBAT VBAT VBAT Dedicated input can be used to receive an external wakeup. Dedicated input can be used to receive an external wakeup. Dedicated input can be used to receive an external wakeup. Dedicated input can be used to receive an external wakeup. B6 A5 A6 C7 VBAT A8 VBAT A7 VBAT n Hibernation mode, this pin provides a signal to shut down an external power supply. C8

7 Freescale Semiconductor 7 MPC5125 Microcontroller Data Sheet Data Sheet, Rev. 3 Pin SPLL_ANAVZ TMPS_ANAVZ SYS_XTAL SYS_XTAL MCS MCAS MRAS Pad Control Register 1 and ffset 2 _CN- TRL_MEM _CN- TRL_MEM _CN- TRL_MEM MVREF SPLL_ANAVZ TMPS_ANAVZ SYS_XTAL SYS_XTAL MCS0 MCAS MRAS MVREF Table 2. MPC5125 Pin Multiplexing (continued) Alternate Function 3 Functions 4 Peripheral 5 Direction SysClock SysClock Power Domain Notes Pin D9 D1 SYS_PLL _AVDD SYS_PLL _AVDD A9 A10 VDD MEM D18 VDD MEM A20 VDD MEM C19 VDD MEM N19 Pin Assignments

8 8 Pin Pad Control Register 1 and ffset 2 MVTT0 MVTT0 Table 2. MPC5125 Pin Multiplexing (continued) Alternate Function 3 Functions 4 Peripheral 5 Direction Power Domain Notes Pin VDD MEM W18 Pin Assignments Freescale Semiconductor MPC5125 Microcontroller Data Sheet Data Sheet, Rev. 3 MVTT1 MVTT2 MVTT3 MWE MDQ00 MDQ01 MDQ02 _CN- TRL_MEM _CN- TRL_MEM _CN- TRL_MEM _CN- TRL_MEM MVTT1 MVTT2 MVTT3 MWE MDQ00 MDQ01 MDQ02 VDD MEM R19 VDD MEM M19 VDD MEM K19 VDD MEM A21 VDD MEM AB19 VDD MEM Y18 VDD MEM AA19

9 Freescale Semiconductor 9 MPC5125 Microcontroller Data Sheet Data Sheet, Rev. 3 Pin MDQ03 MDQ04 MDQ05 MDQ06 MDQ07 MDQ08 MDQ09 MDQ10 Pad Control Register 1 and ffset 2 _CN- TRL_MEM _CN- TRL_MEM _CN- TRL_MEM _CN- TRL_MEM _CN- TRL_MEM _CN- TRL_MEM _CN- TRL_MEM _CN- TRL_MEM MDQ03 MDQ04 MDQ05 MDQ06 MDQ07 MDQ08 MDQ09 MDQ10 Table 2. MPC5125 Pin Multiplexing (continued) Alternate Function 3 Functions 4 Peripheral 5 Direction Power Domain Notes Pin VDD MEM AB21 VDD MEM AA21 VDD MEM Y20 VDD MEM W20 VDD MEM U19 VDD MEM AA22 VDD MEM Y22 VDD MEM V20 Pin Assignments

10 10 Pin MDQ11 Pad Control Register 1 and ffset 2 _CN- TRL_MEM MDQ11 Table 2. MPC5125 Pin Multiplexing (continued) Alternate Function 3 Functions 4 Peripheral 5 Direction Power Domain Notes Pin VDD MEM W21 Pin Assignments Freescale Semiconductor MPC5125 Microcontroller Data Sheet Data Sheet, Rev. 3 MDQ12 MDQ13 MDQ14 MDQ15 MDQ16 MDQ17 MDQ18 _CN- TRL_MEM _CN- TRL_MEM _CN- TRL_MEM _CN- TRL_MEM _CN- TRL_MEM _CN- TRL_MEM _CN- TRL_MEM MDQ12 MDQ13 MDQ14 MDQ15 MDQ16 GPT1[0] MDQ17 GPT1[1] MDQ18 GPT1[2] GPT1 GPT1 GPT1 VDD MEM W22 VDD MEM T20 VDD MEM V22 VDD MEM U22 VDD MEM R20 VDD MEM T21 VDD MEM P20

11 Freescale Semiconductor 11 MPC5125 Microcontroller Data Sheet Data Sheet, Rev. 3 Pin MDQ19 MDQ20 MDQ21 MDQ22 MDQ23 MDQ24 MDQ25 MDQ26 Pad Control Register 1 and ffset 2 _CN- TRL_MEM _CN- TRL_MEM _CN- TRL_MEM _CN- TRL_MEM _CN- TRL_MEM _CN- TRL_MEM _CN- TRL_MEM _CN- TRL_MEM MDQ19 GPT1[3] MDQ20 GPT1[4] MDQ21 GPT1[5] MDQ22 GPT1[6] MDQ23 GPT1[7] MDQ24 GP21 MDQ25 GP22 MDQ26 GP23 Table 2. MPC5125 Pin Multiplexing (continued) Alternate Function 3 Functions 4 Peripheral 5 Direction GPT1 GPT1 GPT1 GPT1 GPT1 GP1 GP1 GP1 Power Domain Notes Pin VDD MEM T22 VDD MEM N20 VDD MEM P22 VDD MEM N22 VDD MEM M20 VDD MEM M21 VDD MEM M22 VDD MEM L20 Pin Assignments

12 12 Pin MDQ27 Pad Control Register 1 and ffset 2 _CN- TRL_MEM MDQ27 GP24 Table 2. MPC5125 Pin Multiplexing (continued) Alternate Function 3 Functions 4 Peripheral 5 Direction GP1 Power Domain Notes Pin VDD MEM L21 Pin Assignments Freescale Semiconductor MPC5125 Microcontroller Data Sheet Data Sheet, Rev. 3 MDQ28 MDQ29 MDQ30 MDQ31 MDM0 MDM1 MDM2 _CN- TRL_MEM _CN- TRL_MEM _CN- TRL_MEM _CN- TRL_MEM _CN- TRL_MEM _CN- TRL_MEM _CN- TRL_MEM MDQ28 GP25 MDQ29 GP26 MDQ30 GP27 MDQ31 GP28 MDM0 MDM1 MDM2 GP29 GP1 GP1 GP1 GP1 GP1 VDD MEM K20 VDD MEM J22 VDD MEM J21 VDD MEM J20 VDD MEM Y19 VDD MEM V21 VDD MEM R22

13 Freescale Semiconductor 13 MPC5125 Microcontroller Data Sheet Data Sheet, Rev. 3 Pin MDM3 MDQS0 MDQS1 MDQS2 MDQS3 MBA0 MBA1 MBA2 Pad Control Register 1 and ffset 2 _CN- TRL_MEM _CN- TRL_MEM _CN- TRL_MEM _CN- TRL_MEM _CN- TRL_MEM _CN- TRL_MEM _CN- TRL_MEM _CN- TRL_MEM MDM3 GP30 MDQS0 MDQS1 MDQS2 GP31 MDQS3 GP32 MBA0 MBA1 MBA2 Table 2. MPC5125 Pin Multiplexing (continued) Alternate Function 3 Functions 4 Peripheral 5 Direction GP1 GP1 GP2 Power Domain Notes Pin VDD MEM K22 VDD MEM AA20 VDD MEM U20 VDD MEM P21 VDD MEM L22 VDD MEM H19 VDD MEM H20 VDD MEM G21 Pin Assignments

14 14 Pin MA00 Pad Control Register 1 and ffset 2 _CN- TRL_MEM MA00 Table 2. MPC5125 Pin Multiplexing (continued) Alternate Function 3 Functions 4 Peripheral 5 Direction Power Domain Notes Pin VDD MEM G20 Pin Assignments Freescale Semiconductor MPC5125 Microcontroller Data Sheet Data Sheet, Rev. 3 MA01 MA02 MA03 MA04 MA05 MA06 MA07 _CN- TRL_MEM _CN- TRL_MEM _CN- TRL_MEM _CN- TRL_MEM _CN- TRL_MEM _CN- TRL_MEM _CN- TRL_MEM MA01 MA02 MA03 MA04 MA05 MA06 MA07 VDD MEM F22 VDD MEM F19 VDD MEM E22 VDD MEM E21 VDD MEM F20 VDD MEM D22 VDD MEM E20

15 Freescale Semiconductor 15 MPC5125 Microcontroller Data Sheet Data Sheet, Rev. 3 Pin MA08 MA09 MA10 MA11 MA12 MA13 MA14 MA15 Pad Control Register 1 and ffset 2 _CN- TRL_MEM _CN- TRL_MEM _CN- TRL_MEM _CN- TRL_MEM _CN- TRL_MEM _CN- TRL_MEM _CN- TRL_MEM _CN- TRL_MEM MA08 MA09 MA10 MA11 MA12 MA13 MA14 MA15/MCS1 Table 2. MPC5125 Pin Multiplexing (continued) Alternate Function 3 Functions 4 Peripheral 5 Direction Power Domain Notes Pin VDD MEM D21 VDD MEM C22 VDD MEM E19 VDD MEM B22 VDD MEM C20 VDD MEM D20 VDD MEM B21 VDD MEM B20 Pin Assignments

16 16 Pin MCK Pad Control Register 1 and ffset 2 _CN- TRL_MEM MCK Table 2. MPC5125 Pin Multiplexing (continued) Alternate Function 3 Functions 4 Peripheral 5 Direction Power Domain Notes Pin VDD MEM H22 Pin Assignments Freescale Semiconductor MPC5125 Microcontroller Data Sheet Data Sheet, Rev. 3 MCK MCKE MDT _CLK _E_B _RWB _CS0_B _CN- TRL_MEM _CN- TRL_MEM _CN- TRL_MEM 0x04 0x05 0x06 0x07 MCK MCKE MDT _CLK TPA1 GP04 _E PSC3_3 GP05 _R/W PSC3_4 GP06 _CS0 GP07 GP1 PSC3 GP1 PSC3 GP1 GP1 VDD MEM G22 VDD MEM C18 VDD MEM J19 VDD_ R4 VDD_ N2 VDD_ N3 VDD_ M1

17 Freescale Semiconductor 17 MPC5125 Microcontroller Data Sheet Data Sheet, Rev. 3 Pin _ACK_B _AX03 EMB_AD00 EMB_AD01 EMB_AD02 EMB_AD03 EMB_AD04 Pad Control Register 1 and ffset 2 0x08 0x09 0x2C 0x2B 0x2A 0x29 0x28 Table 2. MPC5125 Pin Multiplexing (continued) Alternate Function 3 Functions 4 Peripheral 5 Direction _ACK/_BURST NFC_CE1 _CS1 GP08 _AX03/_TS NFC_CE2 _CS2 _AD00/NFC_AD00 RST_CNF_LC0 _AD01/NFC_AD01 RST_CNF_LC1 _AD02/NFC_AD02 RST_CNF_BMS _AD03/NFC_AD03 RST_CNF_DBW0 _AD04/NFC_AD04 RST_CNF_DBW1 NFC GP1 NFC Power Domain Notes Pin VDD_ P3 VDD_ L1 VDD_ VDD_ VDD_ VDD_ VDD_ : Reset configuration Boot RM Location 0 : Reset configuration Boot RM Location 1 : Reset configuration Boot Mode Select : Reset configuration Port Size 0 : Reset configuration Port Size 1 A4 A3 B4 B3 D5 Pin Assignments

18 18 Pin EMB_AD05 Pad Control Register 1 and ffset 2 0x27 Table 2. MPC5125 Pin Multiplexing (continued) Alternate Function 3 Functions 4 Peripheral 5 Direction _AD05/NFC_AD05 RST_CNF_CREPLL6 Power Domain Notes Pin VDD_ : Reset configuration Core PLL Multiplication Factor 0 B2 Pin Assignments Freescale Semiconductor MPC5125 Microcontroller Data Sheet Data Sheet, Rev. 3 EMB_AD06 EMB_AD07 EMB_AD08 EMB_AD09 EMB_AD10 EMB_AD11 EMB_AD12 0x26 0x25 0x24 0x23 0x22 0x21 0x20 _AD06/NFC_AD06 RST_CNF_CREPLL5 _AD07/NFC_AD07 RST_CNF_CREPLL4 _AD08/NFC_AD08 PSC3_2 RST_CNF_SPMF0 GP28 _AD09/NFC_AD09 PSC3_1 RST_CNF_SPMF1 GP27 _AD10/NFC_AD10 PSC3_0 RST_CNF_SPMF2 GP26 _AD11/NFC_AD11 PSC2_4 RST_CNF_SPMF3 GP25 _AD12/NFC_AD12 PSC2_3 RST_CNF_PREDV0 GP24 PSC3 GP1 PSC3 GP1 PSC3 GP1 PSC2 GP1 PSC2 GP1 VDD_ VDD_ VDD_ VDD_ VDD_ : Reset configuration Core PLL Multiplication Factor 1 : Reset configuration Core PLL Multiplication Factor 2 : Reset configuration System PLL Multiplication Factor 0 : Reset configuration System PLL Multiplication Factor 1 : Reset configuration System PLL Multiplication Factor 2 C4 C3 E4 C2 D2 VDD_ : Reset configuration C1 VDD_ : Reset configuration E3

19 Freescale Semiconductor 19 MPC5125 Microcontroller Data Sheet Data Sheet, Rev. 3 Pin EMB_AD13 EMB_AD14 EMB_AD15 EMB_AD16 EMB_AD17 EMB_AD18 EMB_AD19 EMB_AD20 Pad Control Register 1 and ffset 2 0x1F 0x1E 0x1D 0x1C 0x1B 0x1A 0x19 0x18 Table 2. MPC5125 Pin Multiplexing (continued) Alternate Function 3 Functions 4 Peripheral 5 Direction _AD13/NFC_AD13 PSC2_2 RST_CNF_PREDV1 GP23 _AD14/NFC_AD14 PSC2_1 RST_CNF_PREDV2 GP22 _AD15/NFC_AD15 PSC2_0 RST_CNF_SYSSCEN GP21 _AD16/_A01/NFC_WE _AD17/_A02/NFC_RE RST_CNF_PLL_LCK _AD18/_A03/NFC_CLE RST_CNF_MX _AD19/_A04/NFC_ALE RST_CNF_WA _AD20/_A05 GP20 PSC2 GP1 PSC2 GP1 PSC2 GP1 GP1 Power Domain Notes Pin VDD_ : Reset configuration E2 VDD_ : Reset configuration H4 VDD_ : Reset configuration E1 VDD_ F3 VDD_ : Reset configuration G3 VDD_ : Reset configuration G2 VDD_ : Reset configuration J4 VDD_ H3 Pin Assignments

20 20 Pin EMB_AD21 Pad Control Register 1 and ffset 2 0x17 Table 2. MPC5125 Pin Multiplexing (continued) Alternate Function 3 Functions 4 Peripheral 5 Direction _AD21/_A06 GP19 GP1 Power Domain Notes Pin VDD_ F1 Pin Assignments Freescale Semiconductor MPC5125 Microcontroller Data Sheet Data Sheet, Rev. 3 EMB_AD22 EMB_AD23 EMB_AD24 EMB_AD25 EMB_AD26 EMB_AD27 EMB_AD28 0x16 0x15 0x14 0x13 0x12 0x11 0x10 _AD22/_A07 RST_CNF TS GP18 _AD23/_A08 GP17 _AD24/_A09 GP16 _AD25/_A10 GP15 _AD26/_A11 GP14 _AD27/_A12 GP13 _AD28/_A13 GP12 GP1 GP1 GP1 GP1 GP1 GP1 GP1 VDD_ : Reset configuration K4 VDD_ J3 VDD_ K3 VDD_ G1 VDD_ J2 VDD_ M4 VDD_ H1

21 Freescale Semiconductor 21 MPC5125 Microcontroller Data Sheet Data Sheet, Rev. 3 Pin EMB_AD29 EMB_AD30 EMB_AD31 EMB_AX00 EMB_AX01 EMB_AX02 NFC_CE0_B NFC_RB Pad Control Register 1 and ffset 2 0x0F 0x0E _ST 0x0D _ST 0x0C 0x0B 0x0A 0x02D 0x02E _ST _AD29/_A14 GP11 _AD30/_A15 CAN_CLK GP10 _AD31/_A16 PSC_MCLK_N GP09 _AX00/_ALE _AX01/_TSZ0 _CS4 _AX02/_TSZ1 NFC_CE3 _CS3 NFC_CE0 GP29 NFC_R/B GP30 Table 2. MPC5125 Pin Multiplexing (continued) Alternate Function 3 Functions 4 Peripheral 5 Direction GP1 GP1 GP1 NFC GP1 NFC GP1 Power Domain Notes Pin VDD_ L3 VDD_ M3 VDD_ J1 VDD_ K1 VDD_ N4 VDD_ L2 VDD_ P1 VDD_ When booting from the NFC, the NFC_RB pin needs an external pullup resistor. N1 Pin Assignments

22 22 Pin DU_CLK Pad Control Register 1 and ffset 2 0x02F DU_CLK PSC4_0 USB1_DATA0 _AX04 Table 2. MPC5125 Pin Multiplexing (continued) Alternate Function 3 Functions 4 Peripheral 5 Direction DU PSC4 USB1 Power Domain Notes Pin VDD_ AB8 Pin Assignments Freescale Semiconductor MPC5125 Microcontroller Data Sheet Data Sheet, Rev. 3 DU_DE DU_HSYNC DU_VSYNC DU_LD00 DU_LD01 DU_LD02 DU_LD03 0x030 0x031 0x032 0x033 _ST 0x034 0x035 0x036 DU_DE PSC4_1 USB1_DATA1 _AX05 DU_HSYNC PSC4_2 USB1_DATA2 _AX06 DU_VSYNC PSC4_3 USB1_DATA3 GP31 CAN3_RX CLK_UT2 DU_LD00 GP32 CAN3_TX CLK_UT3 DU_LD01 GP33 DU_LD02 PSC4_4 USB1_DATA4 _AX07 DU_LD03 PSC5_0 USB1_DATA5 _AX08 DU PSC4 USB1 DU PSC4 USB1 DU PSC4 USB1 GP1 CAN3 DU DU GP2 CAN3 DU DU GP2 DU PSC4 USB1 DU PSC5 USB1 VDD_ AA8 VDD_ W11 VDD_ Y17 VDD_ AB9 VDD_ Y10 VDD_ AA10 VDD_ Y11

23 Freescale Semiconductor 23 MPC5125 Microcontroller Data Sheet Data Sheet, Rev. 3 Pin DU_LD04 DU_LD05 DU_LD06 DU_LD07 DU_LD08 DU_LD09 DU_LD10 DU_LD11 Pad Control Register 1 and ffset 2 0x037 0x038 0x039 0x03A _ST 0x03B _ST 0x03C 0x03D 0x03E DU_LD04 PSC5_1 USB1_DATA6 _AX09 DU_LD05 PSC5_2 USB1_DATA7 GP34 DU_LD06 PSC5_3 USB1_STP GP35 DU_LD07 PSC5_4 USB1_CLK GP36 CAN4_RX PSC6_0 DU_LD08 GP37 CAN4_TX PSC6_1 DU_LD09 GP38 DU_LD10 PSC6_2 USB1_NEXT GP39 DU_LD11 PSC6_3 USB1_DR GP40 Table 2. MPC5125 Pin Multiplexing (continued) Alternate Function 3 Functions 4 Peripheral 5 Direction DU PSC5 USB1 DU PSC5 USB1 GP2 DU PSC5 USB1 GP2 DU PSC5 USB1 GP2 CAN4 PSC6 DU GP2 CAN4 PSC6 DU GP2 DU PSC6 USB1 GP2 DU PSC6 USB1 GP2 Power Domain Notes Pin VDD_ AA11 VDD_ AB10 VDD_ AB11 VDD_ Y12 VDD_ W13 VDD_ AB12 VDD_ Y13 VDD_ AA13 Pin Assignments

24 24 Pin DU_LD12 Pad Control Register 1 and ffset 2 0x03F DU_LD12 PSC6_4 USB2_DATA0 GPT2[0] Table 2. MPC5125 Pin Multiplexing (continued) Alternate Function 3 Functions 4 Peripheral 5 Direction DU PSC6 USB2 GPT2 Power Domain Notes Pin VDD_ AB13 Pin Assignments Freescale Semiconductor MPC5125 Microcontroller Data Sheet Data Sheet, Rev. 3 DU_LD13 DU_LD14 DU_LD15 DU_LD16 DU_LD17 DU_LD18 DU_LD19 0x040 0x041 0x042 0x043 _ST 0x044 _ST 0x045 0x046 DU_LD13 PSC7_0 USB2_DATA1 GPT2[1] DU_LD14 PSC7_1 USB2_DATA2 GPT2[2] DU_LD15 PSC7_2 USB2_DATA3 GPT2[3] CLK_UT0 2C3_SCL DU_LD16 GP41 CLK_UT1 2C3_SDA DU_LD17 GP42 DU_LD18 PSC7_3 USB2_DATA4 GPT2[4] DU_LD19 PSC7_4 USB2_DATA5 GPT2[5] DU PSC7 USB2 GPT2 DU PSC7 USB2 GPT2 DU PSC7 USB2 GPT2 DU 2 C2 DU GP2 DU 2 C3 DU GP2 DU PSC7 USB2 GPT2 DU PSC7 USB2 GPT2 VDD_ W14 VDD_ Y14 VDD_ AB14 VDD_ AA15 VDD_ Y15 VDD_ AB15 VDD_ AB16

25 Freescale Semiconductor 25 MPC5125 Microcontroller Data Sheet Data Sheet, Rev. 3 Pin DU_LD20 DU_LD21 DU_LD22 DU_LD23 2C2_SCL 2C2_SDA 2C1_SCL 2C1_SDA Pad Control Register 1 and ffset 2 0x047 0x048 0x049 0x04A 0x4B _ST 0x4C _ST 0x4F _ST 0x50 _ST DU_LD20 PSC8_0 USB2_DATA6 GPT2[6] DU_LD21 PSC8_1 USB2_DATA7 GPT2[7] DU_LD22 PSC8_2 USB2_DR GP43 DU_LD23 PSC8_3 USB2_NEXT GP44 2C2_SCL PSC8_4 USB2_CLK GP45 2C2_SDA PSC9_4 USB2_STP GP46 2C1_SCL PSC9_2 CAN3_RX GP49 2C1_SDA PSC9_3 CAN3_TX GP50 Table 2. MPC5125 Pin Multiplexing (continued) Alternate Function 3 Functions 4 Peripheral 5 Direction DU PSC8 USB2 GPT2 DU PSC8 USB2 GPT2 DU PSC8 USB2 GP2 DU PSC8 USB2 GP2 2 C2 PSC8 USB2 GP2 2 C2 PSC9 USB2 GP2 2 C1 PSC9 CAN3 GP2 2 C1 PSC9 CAN3 GP2 Power Domain Notes Pin VDD_ AB17 VDD_ W16 VDD_ Y16 VDD_ AA17 VDD_ V4 VDD_ U4 VDD_ B18 VDD_ A19 Pin Assignments

26 26 Pin Pad Control Register 1 and ffset 2 CAN1_RX CAN1_RX Table 2. MPC5125 Pin Multiplexing (continued) Alternate Function 3 Functions 4 Peripheral 5 Direction CAN1 Power Domain Notes Pin VBAT Dedicated input can be used to receive an external wakeup. C9 Pin Assignments Freescale Semiconductor MPC5125 Microcontroller Data Sheet Data Sheet, Rev. 3 CAN2_RX CAN1_TX CAN2_TX FEC1_TXD_2 FEC1_TXD_3 FEC1_RXD_2 FEC1_RXD_3 0x4D _ST 0x4E _ST 0x51 0x52 0x53 0x54 CAN2_RX CAN1_TX PSC9_0 2C2_SCL GP47 CAN2_TX PSC9_1 2C2_SDA GP48 FEC1_TXD_2 PSC2_0 USB2_DATA0 GP51 FEC1_TXD_3 PSC2_1 USB2_DATA1 GP52 FEC1_RXD_2 PSC2_2 USB2_DATA2 GP53 FEC1_RXD_3 PSC2_3 USB2_DATA3 GP54 CAN2 CAN1 PSC9 2 C2 GP2 CAN2 PSC9 2 C2 GP2 FEC1 PSC2 USB2 GP2 FEC1 PSC2 USB2 GP2 FEC1 PSC2 USB2 GP2 FEC1 PSC2 USB2 GP2 VBAT Dedicated input can be used to receive an external wakeup. B8 VDD_ B15 VDD_ A16 VDD_ AA1 VDD_ Y1 VDD_ Y4 VDD_ AA2

27 Freescale Semiconductor 27 MPC5125 Microcontroller Data Sheet Data Sheet, Rev. 3 Pin FEC1_CRS FEC1_TX_ER FEC1_RXD_1 FEC1_TXD_1 FEC1_MDC 0x55 0x56 0x57 0x58 0x59 FEC1_RX_ER 0x5A FEC1_MD FEC1_RXD_0 Pad Control Register 1 and ffset 2 0x5B _ST 0x5C FEC1_CRS PSC2_4 USB2_DATA4 GP55 FEC1_TX_ER PSC3_0 USB2_DATA5 GP56 Table 2. MPC5125 Pin Multiplexing (continued) Alternate Function 3 Functions 4 Peripheral 5 Direction FEC1_RXD_1/RM_RX1 PSC3_1 USB2_DATA6 GP57 FEC1_TXD_1/RM_TX1 PSC3_2 USB2_DATA7 GP58 FEC1_MDC/RM_MDC PSC3_3 USB2_DR GP59 FEC1_RX_ER/RM_RX_ER PSC3_4 USB2_NEXT GP60 FEC1_MD/RM_MD USB2_CLK GP61 FEC1_RXD_0/RM_RX0 USB2_STP GP62 FEC1 PSC2 USB2 GP2 FEC1 PSC3 USB2 GP2 FEC1 PSC3 USB2 GP2 FEC1 PSC3 USB2 GP2 FEC1 PSC3 USB2 GP2 FEC1 PSC3 USB2 GP2 FEC1 USB2 GP2 FEC1 USB2 GP2 Power Domain Notes Pin VDD_ U1 VDD_ W2 VDD_ AA3 VDD_ W3 VDD_ V1 VDD_ Y5 VDD_ V2 VDD_ AB2 Pin Assignments

28 28 Pin FEC1_TXD_0 Pad Control Register 1 and ffset 2 0x5D _ST Table 2. MPC5125 Pin Multiplexing (continued) Alternate Function 3 Functions 4 Peripheral 5 Direction FEC1_TXD_0/RM_TX0 NFC_R/B1 GP63 FEC1 NFC GP2 Power Domain Notes Pin VDD_ W4 Pin Assignments Freescale Semiconductor MPC5125 Microcontroller Data Sheet Data Sheet, Rev. 3 FEC1_TX_CLK 0x5E FEC1_RX_CLK 0x5F FEC1_RX_DV FEC1_TX_EN FEC1_CL USB1_DATA0 USB1_DATA1 _ST _ST 0x60 _ST 0x61 0x62 _ST 0x63 0x64 FEC1_TX_CLK/RM_REF_CLK PSC0_0 GP04 FEC1_RX_CLK PSC0_1 NFC_R/B2 GP05 FEC1_RX_DV/RM_CRS_DV PSC0_2 NFC_R/B3 GP06 FEC1_TX_EN/RM_TX_EN PSC0_3 GP07 FEC1_CL PSC0_4 GP08 USB1_DATA0 PSC1_0 FEC2_RXD_1/RM_RX1 USB1_DATA1 PSC1_1 FEC2_TXD_1/RM_TX1 FEC1 PSC0 GP1 FEC1 PSC0 GP1 FEC1 PSC0 NFC GP1 FEC1 PSC0 GP1 FEC1 PSC0 GP1 USB2 PSC1 FEC2 USB2 PSC1 FEC2 VDD_ W1 VDD_ AB4 VDD_ AB3 VDD_ Y3 VDD_ U3 VDD_ Y9 VDD_ W9

29 Freescale Semiconductor 29 MPC5125 Microcontroller Data Sheet Data Sheet, Rev. 3 Pin USB1_DATA2 USB1_DATA3 USB1_DATA4 USB1_DATA5 USB1_DATA6 USB1_DATA7 USB1_STP USB1_CLK Pad Control Register 1 and ffset 2 0x65 0x66 0x67 0x68 0x69 0x6A _ST 0x6B _ST 0x6C _ST Table 2. MPC5125 Pin Multiplexing (continued) Alternate Function 3 Functions 4 Peripheral 5 Direction USB1_DATA2 PSC1_2 FEC2_MDC/RM_MDC USB1_DATA3 PSC1_3 FEC2_RX_ER/RM_RX_ER USB1_DATA4 PSC1_4 FEC2_MD/RM_MD USB1_DATA5 PSC4_0 FEC2_RXD_0/RM_RX0 USB1_DATA6 PSC4_1 FEC2_TXD_0/RM_TX0 USB1_DATA7 PSC4_2 FEC2_TX_CLK/RM_REF_CLK USB1_STP PSC4_3 FEC2_RX_CLK USB1_CLK PSC4_4 FEC2_RX_DV/RM_CRS_DV USB2 PSC1 FEC2 USB2 PSC1 FEC2 USB2 PSC1 FEC2 USB2 PSC4 FEC2 USB2 PSC4 FEC2 USB2 PSC4 FEC2 USB2 PSC4 FEC2 USB2 PSC4 FEC2 Power Domain Notes Pin VDD_ AB7 VDD_ AB6 VDD_ AA7 VDD_ Y7 VDD_ Y6 VDD_ AB5 VDD_ W6 VDD_ Y8 Pin Assignments

30 30 Pin USB1_NEXT Pad Control Register 1 and ffset 2 0x6D Table 2. MPC5125 Pin Multiplexing (continued) Alternate Function 3 Functions 4 Peripheral 5 Direction USB1_NEXT FEC2_TX_EN/RM_TX_EN GP09 USB2 FEC2 GP1 Power Domain Notes Pin VDD_ AA5 Pin Assignments MPC5125 Microcontroller Data Sheet Data Sheet, Rev. 3 USB1_DR SDHC1_CLK SDHC1_CMD SDHC1_D0 SDHC1_D1 0x6E _ST 0x6F 0x70 0x71 0x72 USB1_DR FEC2_CL GP10 SDHC1_CLK NFC_CE1 FEC2_TXD_2 GP11 SDHC1_CMD PSC5_0 FEC2_TXD_3 GP12 SDHC1_D0 PSC5_1 FEC2_RXD_2 GP13 SDHC1_D1_RQ PSC5_2 FEC2_RXD_3 _CS5 USB2 FEC2 GP1 SDHC SDHC1 NFC FEC2 GP1 SDHC1 PSC5 FEC2 GP1 SDHC1 PSC5 FEC2 GP1 SDHC1 PSC5 FEC2 VDD_ W7 VDD_ T1 VDD_ T2 VDD_ T3 VDD_ T4 Freescale Semiconductor SDHC1_D2 SDHC1_D3 0x73 0x74 SDHC1_D2 PSC5_3 FEC2_CRS _CS6 SDHC1_D3_CD PSC5_4 FEC2_TX_ER _CS7 SDHC1 PSC5 FEC2 SDHC1 PSC5 FEC2 VDD_ R1 VDD_ R2

31 Freescale Semiconductor 31 MPC5125 Microcontroller Data Sheet Data Sheet, Rev. 3 Pin PSC_MCLK_N 0x75 PSC0_0 PSC0_1 PSC0_2 PSC0_3 PSC0_4 PSC1_0 PSC1_1 Pad Control Register 1 and ffset 2 _ST 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C PSC_MCLK_N GP14 PSC0_0 SDHC2_CMD GPT1[0] GP15 PSC0_1 SDHC2_D0 GPT1[1] GP16 PSC0_2 SDHC2_D1_RQ GPT1[2] GP17 PSC0_3 SDHC2_D2 GPT1[3] GP18 PSC0_4 SDHC2_D3_CD GPT1[4] CAN1_TX PSC1_0 SDHC2_CLK GPT1[5] CAN2_TX PSC1_1 CAN_CLK GPT1[6] RQ0 Table 2. MPC5125 Pin Multiplexing (continued) Alternate Function 3 Functions 4 Peripheral 5 Direction GP1 PSC0 SDHC2 GPT1 GP1 PSC0 SDHC2 GPT1 GP1 PSC0 SDHC2 GPT1 GP1 PSC0 SDHC2 GPT1 GP1 PSC0 SDHC2 GPT1 CAN1 PSC1 SDHC2 GPT1 CAN2 PSC1 GPT1 Power Domain Notes Pin VDD_ D6 VDD_ C11 VDD_ A12 VDD_ A13 VDD_ B13 VDD_ D11 VDD_ C12 VDD_ C13 Pin Assignments

32 32 Pin PSC1_2 Pad Control Register 1 and ffset 2 0x7D PSC1_2 TPA2 GPT1[7] RQ1 Table 2. MPC5125 Pin Multiplexing (continued) Alternate Function 3 Functions 4 Peripheral 5 Direction PSC1 GPT1 Power Domain Notes Pin VDD_ B14 Pin Assignments MPC5125 Microcontroller Data Sheet Data Sheet, Rev. 3 PSC1_3 PSC1_4 J1850_TX J1850_RX 0x7E 0x7F 0x80 _ST 0x81 _ST TCK PSC1_3 CKSTP_N NFC_R/B2 GP19 PSC1_4 CKSTP_UT NFC_CE2 GP20 J1850_TX NFC_CE3 2C1_SCL J1850_RX NFC_R/B3 2C1_SDA TCK PSC1 NFC GP1 PSC1 MFC GP1 J1850 NFC 2 C1 J1850 NFC 2 C1 JTAG JTAG VDD_ D13 VDD_ A15 VDD_ B5 VDD_ C6 VDD_ 5. This pin contains an enabled internal Schmitt trigger. C16 Freescale Semiconductor TD TD TD TD JTAG JTAG VDD_ 3. This JTAG pin has an internal pullup P-FET, and cannot be configured. C15 VDD_ B16

33 Freescale Semiconductor 33 MPC5125 Microcontroller Data Sheet Data Sheet, Rev. 3 Pin Pad Control Register 1 and ffset 2 TMS TRST HRESET PRESET SRESET TMS TRST HRESET PRESET SRESET Table 2. MPC5125 Pin Multiplexing (continued) Alternate Function 3 Functions 4 Peripheral 5 Direction JTAG JTAG System Control Power Domain Notes Pin VDD_ VDD_ VDD_ VDD_ VDD_ 3. This JTAG pin has an internal pullup P-FET, and cannot be configured. 3. This JTAG pin has an internal pullup P-FET, and cannot be configured. 1. This pin is an input or open-drain output, and have internal pull-up P-FETs. This pin can not be configured. 5. This pin contains an enabled internal schmitt-trigger. 1. This pin is an input or open-drain output, and have internal pull-up P-FETs. This pin can not be configured. 2. This pin is an input only. This pin cannot be configured. 5. This pin contains an enabled internal schmitt-trigger. 1. This pin is an input or open-drain output, and have internal pull-up P-FETs. This pin can not be configured. 5. This pin contains an enabled internal schmitt-trigger. D15 D16 A17 C17 A18 Pin Assignments

34 34 Pin Pad Control Register 1 and ffset 2 Table 2. MPC5125 Pin Multiplexing (continued) Alternate Function 3 Functions 4 Peripheral 5 Direction Test/Debug Power Domain Notes Pin Pin Assignments MPC5125 Microcontroller Data Sheet Data Sheet, Rev. 3 l TEST TEST VDD_ 2. This pin is an input only. This pin cannot be configured. 4. This test pin must be tied to VSS. NTES: 1 Pins controlled by the _ST register have a Schmitt trigger input; pins controlled by the register do not. Pins controlled by the _CNTRL_MEM register access their alternate function by setting the _CNTRL_MEM[16BT] bit. This setting applies to all pins controlled by _CNTRL_MEM. Pins not controlled by these registers are indicated with a. 2 ffset from CNTRL_BASE (default is 0xFF40_A000). 3 Except where noted in the Notes column, is the primary (default) function for each pin after reset. 4 Alternate functions are chosen by setting the values of the [FUNCMUX] bitfields inside the Control module. [FUNCMUX] = 00 (default) [FUNCMUX] = 01 [FUNCMUX] = 10 [FUNCMUX] = 11 For selecting alternate functions, the and _ST registers function the same. When no function is available on a pin s given ALTn function (value of [FUNCMUX] ), it is shown as. 5 Module included on the MCU. D14 Freescale Semiconductor

35 3.2.1 Power and Ground Supply Summary Pin Assignments Table 3. MPC TEPBGA Power/Ground Pin Name Function Description Voltage 1 Package Pin Locations V DD Supply voltage e300 core and peripheral logic 1.4 V J10, J11, J12, J13, K14, L9, L14, M9, M14, N14, P10, P11, P12, P13 V DD_ Supply voltage buffers 3.3 V A14, B9, B12, B17, C5, C14, D3, F2, G4, H2, M2, R3, V3, W5, W15, AA4, AA9, AA12, AA14, AA16, AB18 V DD MEM Supply voltage memory 2 NTES: 1 Nominal voltages. 2 Dependent on external memory type. See Table 5. B19, C21, D17, D19, G19, H21, P19, R21, T19, V19, W19, Y21, AB20 AV DD_FUSEWR Power 3.3 V D4 AV DD_CPLL Analog power 3.3 V D10 AV DD_SPLL Analog power 3.3 V A11 AV DD_SC_TMPS Analog power 3.3 V C10 V BAT Power 3.3 V D8 AV SS_CPLL Analog ground 0 V B11 AV SS_SC_TMPS_SPLL Analog grounddouble-bonded AVSS_SC_TMPS and AVSS_SPLL 0 V B10 MV REF Analog input Voltage reference for SSTL input pads 2 N19 MV TT0 MV TT1 MV TT2 MV TT3 Analog input SSTL(DDR2) termination (DT) voltage Analog input SSTL(DDR2) termination (DT) voltage Analog input SSTL(DDR2) termination (DT) voltage Analog input SSTL(DDR2) termination (DT) voltage 2 W18 2 R19 2 M19 2 K19 V SS Ground 0 V A1, A2, A22, B1, B7, D7, D12, F4, F21, J9, J14, K2, K[9:13], K21, L4, L[10:13], L19, M[10:13], N[9:13], N21, P2, P4, P9, P14, U2, U21, W8, W10, W12, W17, Y2, AA6, AA18, AB1, AB22 NTE This table indicates only the pins with a permanently enabled internal pullup, pulldown, or Schmitt trigger. Most digital pins can be configured to enable internal pullup, pulldown, or Schmitt trigger. See the MPC5125 Reference Manual (MPC5125RM), Control chapter. Freescale Semiconductor 35

36 Electrical and Thermal Characteristics 4 Electrical and Thermal Characteristics 4.1 DC Electrical Characteristics Absolute Maximum Ratings The tables in this section describe the MPC5125 DC electrical characteristics. Table 4 gives the absolute maximum ratings. Table 4. Absolute Maximum Ratings 1 Characteristic Sym Min Max Unit SpecD Supply voltage e300 core and peripheral logic V DD V D1.1 Supply voltage buffers V DD_, V DD MEM V D1.2 nput reference voltage (DDR/DDR2) MV REF V D1.15 Termination Voltage (DDR2) MV TT V D1.16 Supply voltage system APLL AV DD_SPLL V D1.3 Supply voltage system oscillator and temperature sensor AV DD_SC_TMPS V D1.4 Supply voltage e300 APLL AV DD_CPLL V D1.5 Supply voltage RTC (hibernation) V BAT V D1.6 Supply voltage FUSE programming AV DD_FUSEWR V D1.7 nput voltage (V DD_ ) V in 0.3 V DD_ V D1.9 nput voltage (V DD MEM ) V in 0.3 V DD MEM V D1.10 nput voltage (V BAT ) V in 0.3 V BAT V D1.11 nput voltage overshoot V inos 1 V D1.12 nput voltage undershoot V inus 1 V D1.13 Storage temperature range T st g o C D1.14 NTES: 1 Absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage Recommended perating Conditions Table 5 gives the recommended operating conditions. Table 5. Recommended perating Conditions Characteristic Sym Min 1 Typ Max 1 Unit SpecD Supply voltage e300 core and peripheral logic V DD V D2.1 State retention voltage e300 core and peripheral logic V D Freescale Semiconductor

37 Electrical and Thermal Characteristics Table 5. Recommended perating Conditions (continued) Characteristic Sym Min 1 Typ Max 1 Unit SpecD Supply voltage standard / buffers V DD_ V D2.3 Supply voltage memory / buffers (DDR) V DD MEM_DDR V D2.4 Supply voltage memory buffers (DDR2, LPDDR, Mobile SDR) Supply voltage memory buffers (SDR) nput reference voltage (DDR/DDR2) MV REF 0.49 V DD MEM V DD MEM_DDR V D2.5 V DD MEM_LPDDR V DD MEM_SDR V D V DD MEM 0.51 V DD MEM V D2.6 Termination voltage (DDR2) MV TT MV REF 0.04 MV REF MV REF V D2.7 Supply voltage system APLL AV DD_SPLL V D2.8 Supply voltage system oscillator and temperature sensor AV DD_SC_TMPS V D2.9 Supply voltage e300 APLL AV DD_CPLL V D2.10 Supply voltage RTC (hibernation) V BAT V D2.11 Supply voltage FUSE programming AV DD_FUSEWR V D2.12 nput voltage standard buffers V in 0 V DD_ V D2.14 nput voltage memory buffers (DDR) nput voltage memory buffers (DDR2) nput voltage memory buffers (SDR) nput voltage memory buffers (LPDDR) V in_ddr 0 V in_ddr2 0 V in_sdr 0 V in_lpddr 0 V DD MEM_DDR V DD MEM_DDR2 V DD MEM_SDR V DD MEM_LPDDR V D2.15 V D2.16 V D2.20 V D2.18 Ambient operating temperature range T A o C D2.17 NTES: 1 These are recommended and tested operating conditions. Proper device operation outside these conditions is not guaranteed. 2 The State Retention voltage can be applied to VDD after the device is placed in deep-sleep mode. 3 VBAT should not be supplied by a battery of voltage less than 3.0 V DC Electrical Specifications Table 6 gives the DC electrical characteristics for the MPC5125 at recommended operating conditions. Table 6. DC Electrical Specifications Characteristic Condition Sym Min Max Unit SpecD nput high voltage nput type = TTL V DD_ V H 0.51 V DD_ V D3.1 nput high voltage nput type = TTL V H MV REF V D3.2 V DD MEM_DDR Freescale Semiconductor 37

38 Electrical and Thermal Characteristics nput high voltage nput high voltage nput high voltage nput type = TTL V H MVREF V D3.3 V DD MEM_DDR2 nput type = TTL V H 0.7 V DD V DD MEM_LPDDR MEM_LPDDR nput type = TTL V H 0.7 V DD V DD MEM_SDR MEM_SDR V D3.4 V D3.33 nput high voltage nput type = Schmitt V DD_ V H 0.65 V DD_ V D3.5 nput high voltage SYS_XTAL crystal mode 1 CV H Vxtal V D3.6 bypass mode 2 (V DD_ / 2) nput high voltage RTC_XTAL crystal mode 3 bypass mode 4 RV H (V BAT / 5) (V BAT / 2) V D3.7 nput low voltage nput type = TTL V DD_ V L 0.42 V DD_ V D3.8 nput low voltage nput low voltage nput low voltage nput low voltage nput type = TTL V DD MEM_DDR V L nput type = TTL V DD MEM_DDR2 V L nput type = TTL V DD MEM_LPDDR V L nput type = TTL V DD MEM_SDR V L MV REF 0.15 V D3.9 MV REF V D V DD MEM_LPDDR 0.3 V DD MEM_SDR V D3.11 V D3.34 nput low voltage nput type = Schmitt V DD_ V L 0.35 V DD_ V D3.12 nput low voltage nput low voltage nput leakage current SYS_XTAL crystal mode bypass mode RTC_XTAL crystal mode bypass mode Vin = 0 or V DD_ /V DD MEM_DDR/2 (depending on input type) 5 CV L RV L Vxtal 0.4 (V DD_ /2) 0.4 (V BAT /5) 0.5 (V BAT /2) 0.4 V D3.13 V D3.14 N µa D3.15 nput leakage current SYS_XTAL_N V in = 0 or V DD_ N 20 µa D3.16 nput leakage current RTC_XTAL_N V in = 0 or V DD_ N 1.0 µa D3.17 nput current, pullup PULLUP V DD_ V in = V L Npu µa D3.18 resistor 6 nput current, PULLDWN V DD_ V in = V H Npd µa D3.19 pulldown resistor 8 utput high voltage H is driver dependent 7 V DD_ V H 0.8 V DD_ V D3.20 utput high voltage H is driver dependent 7 V HDDR 1.94 V D3.21 V DD MEM_DDR utput high voltage H is driver dependent 7 V DD MEM_DDR2 V HDDR2 VDD MEM 0.28 utput high voltage H is driver dependent 7 Table 6. DC Electrical Specifications (continued) Characteristic Condition Sym Min Max Unit SpecD V DD MEM_LPDDR V HLPDD R VDD MEM 0.28 V D3.22 V D Freescale Semiconductor

39 Electrical and Thermal Characteristics utput high voltage H is driver dependent 7 V DD MEM_SDR V HSDR 0.8 VDD MEM V D3.35 utput low voltage L is driver dependent 7 V DD_ V L 0.2 V DD_ V D3.24 utput low voltage L is driver dependent 7 V LDDR 0.36 V D3.25 V DD MEM_DDR utput low voltage L is driver dependent 7 V DD MEM_DDR2 V LDDR V D3.26 utput low voltage L is driver dependent 7 V DD MEM_LPDDR V LLPDD R 0.28 V D3.27 utput low voltage L is driver dependent 7 V DD MEM_SDR V LSDR 0.2 V DD MEM V D3.36 DC injection current per pin 8 nput capacitance (digital pins) nput capacitance (analog pins) n-die termination (DDR2) Table 6. DC Electrical Specifications (continued) Characteristic Condition Sym Min Max Unit SpecD CS ma D3.29 C in 7 pf D3.30 C in 10 pf D3.31 R DT W D3.32 NTES: 1 This parameter is meant for those who do not use quartz crystals or resonators, but instead use CAN oscillators in crystal mode. n that case, V extal V xtal 400 mv criteria has to be met for oscillator s comparator to produce the output clock. 2 This parameter is meant for those who do not use quartz crystals or resonators, but instead use a signal generator clock to drive the clock in bypass mode. n this case, for the oscillator s comparator to produce the output clock, drive only the EXTAL pin. Do not connect anything to any other oscillator pin. 3 This parameter is meant for those who do not use quartz crystals or resonators, but instead use CAN oscillators in crystal mode to drive the clock. n that case, for the oscillator s comparator to produce the output clock, drive one of the XTAL_N or XTAL_UT pins. Do not connect anything to the other oscillator pins. 4 This parameter is meant for those who do not use quartz crystals or resonators, but instead use a signal generator clock to drive the clock in bypass mode. n that case, for the oscillator s comparator to produce the output clock, drive only the XTAL_N pin. Do not connect anything to any other oscillator pin. 5 Leakage current is measured with output drivers disabled and with pullups and pulldowns inactive. 6 Pullup current is measured at V L and pulldown current is measured at V H. 7 See Table 7 for the typical drive capability of a specific signal pin based on the type of output driver associated with that pin as listed in Table 2. 8 All injection current is transferred to V DD_ /V DD MEM. An external load is required to dissipate this current to maintain the power supply within the specified voltage range. Total injection current for all digital input-only and all digital input/output pins must not exceed 10 ma. Exceeding this limit can cause disruption of normal operation. Freescale Semiconductor 39

40 Electrical and Thermal Characteristics Table 7. General Pads 1 Drive Current, Slew Rate Pad Type Supply Voltage Drive Select/Slew Rate Control Rise time max (ns) Fall time max (ns) Current oh (ma) Current ol (ma) SpecD General V DD_ = 3.3 V Configuration 3 (11) D3.41 NTES: 1 General rise and fall times at drive load 50 pf. Configuration 2 (10) D3.42 Configuration 1 (01) D3.43 Configuration 0 (00) D Table 8. DDR Pads 1 Drive Current, Slew Rate Pad Type Supply Voltage Drive Select/ Slew Rate Control Rising slew max (ns) 2 Falling slew max (ns) 3 Current oh (ma) Current ol (ma) SpecD DDR V DD MEM = 2.5 V (DDR) Configuration 3 (011) D3.45 V DD MEM = 1.8 V (LPDDR and SDR) Configuration 0 (000) D3.46 Configuration 1 (001) D3.47 V DD MEM = 1.8 V (DDR2) Configuration 2 (010) D3.48 Configuration 6 (110) D3.49 V DD MEM = 3.3 V (SDR) Configuration 7 (111) D3.50 NTES: 1 DDRrise and fall times at 50 Ω transmission line impedance terminated to MV TT (0.5 V DD MEM ) + 4 pf load. 2 Rising slew rate measured between 0.5 V DD MEM 450 mv and 0.5 V DD MEM + 50 mv for all modes. 3 Falling slew rate measured between 0.5 V DD MEM + 50 mv and 0.5 V DD MEM 450 mv for all modes Electrostatic Discharge CAUTN This device contains circuitry that protects against damage due to high-static voltage or electrical fields. However, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages. perational reliability is enhanced if unused inputs are tied to an appropriate logic voltage level (GND or V DD ). Table 11 gives package thermal characteristics for this device. Table 9. ESD and Latch-Up Protection Characteristics Sym Rating Min Max Unit SpecD V HBM Human body model (HBM) JEDEC JESD22-A114-B 2000 V D4.1 V MM Machine model (MM) JEDEC JESD22-A V D4.2 V CDM Charge device model (CDM) JEDEC JESD22-C V D Freescale Semiconductor

41 4.1.5 Power Dissipation Electrical and Thermal Characteristics Power dissipation of the MPC5125 is caused by three different components: Dissipation of the internal or core digital logic (supplied by V DD ) Dissipation of the analog circuitry (supplied by AV DD_SPLL and AV DD_CPLL ) Dissipation of the logic (supplied by V DD MEM and V DD_ ) Table 10 details typical measured core and analog power dissipation figures for a range of operating modes. However, the dissipation due to the switching of the pins cannot be given in general, but must be calculated for each application case using the following formula: P = P int + N C VDD_ 2 f M Eqn. 1 where N is the number of output pins switching in a group M, C is the capacitance per pin, V DD_ is the voltage swing, f is the switching frequency, and P int is the power consumed by the unloaded stage. The total power consumption of the MPC5125 device must not exceed this value, which would cause the maximum junction temperature to be exceeded. P total = P core + P analog + P Eqn. 2 Table 10. Power Dissipation Core Power Supply (V DD_core ) 1 High-Performance Mode e300 = 400 MHz, CSB = 200 MHz Unit SpecD perational mw D5.1 Doze mw D5.3 Nap mw D5.2 Sleep mw D5.4 Deep-sleep 4 38 mw D5.5 RTC Power Supply (V BAT ) Hibernation 20 µw D5.6 PLL/SC Power Supplies (AV DD_SPLL, AV DD_CPLL, AV DD_SC_TMPS ) 5 perational 18 mw D5.7 Deep-sleep 55 µw D5.8 Unloaded Power Supplies (V DD_, V DD MEM ) 6 V DD_ V DD MEM perational mw D5.9 Deep-sleep 5 1 mw D5.10 NTES: 1 Typical core power is measured at V DD_core = 1.4 V, T J = 25 C. 2 perational power is measured while running an entirely cache-resident program with floating-point multiplication instructions in parallel with DDR write operation. Freescale Semiconductor 41

42 Electrical and Thermal Characteristics 3 Doze, Nap, and Sleep power are measured with the e300 core in Doze/Nap/Sleep mode; the system oscillator, system PLL, and core PLL active; and all other system modules inactive. 4 Deep-sleep power is measured with the e300 core in Sleep mode. The system oscillator, system PLL, core PLL, and other system modules are inactive. 5 PLL power is measured at AV DD_SPLL = AV DD_CPLL = AV DD_SC_TMPS = 3.3 V, T J = 25 C. 6 Unloaded typical power is measured at V DD_ = 3.3 V, V DD_MEM_ = 1.8 V, T J = 25 C. NTE The maximum power depends on the supply voltage, process corner, junction temperature, and the concrete application and clock configurations Thermal Characteristics Table 11. Thermal Resistance Data 1 Rating Conditions Sym Value Unit SpecD Thermal resistance junction-to-ambient natural convection 2 Single layer board 1s R θja 35 C/W D6.1 Thermal resistance junction-to-ambient natural Four layer board 2s2p R θja 25 C/W D6.2 convection 2 Thermal resistance junction-to-moving-air ambient 200 ft./min., single layer board 1s R θjma 29 C/W D6.3 Thermal resistance junction-to-moving-air ambient 200 ft./min., four layer board 2s2p R θjma 22 C/W D6.4 Thermal resistance junction-to-board 3 R θjb 16 C/W D6.5 Thermal resistance junction-to-case 4 R θjc 11 C/W D6.6 Junction-to-package-top natural convection 5 Natural convection Ψ JT 3 C/W D6.7 NTES: 1 Thermal characteristics are targets based on simulation that are subject to change per device characterization. 2 Junction-to-Ambient thermal resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board meets JEDEC specification for this package. 3 Junction-to-Board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC specification for the specified package. 4 Junction-to-Case at the top of the package determined using ML-STD 883 Method The cold plate temperature is used for the case temperature. Reported value includes the thermal resistance of the interface layer. 5 Thermal characterization parameter indicating the temperature difference between the package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT Heat Dissipation An estimation of the chip-junction temperature, T J, can be obtained from the following equation: T J = T A + ( R θja P D ) Eqn. 3 where: T A = ambient temperature for the package ( º C ) R θja = junction to ambient thermal resistance ( º C / W ) P D = power dissipation in package (W) 42 Freescale Semiconductor

43 Electrical and Thermal Characteristics The junction to ambient thermal resistance is an industry standard value, which provides a quick and easy estimation of thermal performance. Unfortunately, there are two values in common usage: the value determined on a single-layer board, and the value obtained on a board with two planes. For packages such as the PBGA, these values can be different by a factor of two. Which value is correct depends on the power dissipated by other components on the board. The value obtained on a single-layer board is appropriate for the tightly packed printed circuit board. The value obtained on the board with the internal planes is usually appropriate if the board has low power dissipation and the components are well separated. Historically, the thermal resistance has frequently been expressed as the sum of a junction to case thermal resistance and a case to ambient thermal resistance: R θja = R θjc + R θca Eqn. 4 where: R θja = junction to ambient thermal resistance ( º C / W ) R θjc = junction to case thermal resistance ( º C / W ) R θca = case to ambient thermal resistance ( º C / W ) R θjc is device related and cannot be influenced by the user. You control the thermal environment to change the case to ambient thermal resistance, R θca. For instance, you can change the air flow around the device, add a heat sink, change the mounting arrangement on printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. This description is most useful for ceramic packages with heat sinks where some 90% of the heat flow is through the case to the heat sink to ambient. For most packages, a better model is required. A more accurate thermal model can be constructed from the junction to board thermal resistance and the junction to case thermal resistance. The junction to case covers the situation where a heat sink is used or where a substantial amount of heat is dissipated from the top of the package. The junction to board thermal resistance describes the thermal performance when most of the heat is conducted to the printed circuit board. This model can be used for hand estimations or for a computational fluid dynamics (CFD) thermal model. To determine the junction temperature of the device in the application after prototypes are available, the thermal characterization parameter (Ψ JT ) can be used to determine the junction temperature with a measurement of the temperature at the top center of the package case using the following equation: T J = T T + ( Ψ JT P D ) Eqn. 5 where: T T = thermocouple temperature on top of package ( º C ) Ψ JT = thermal characterization parameter ( º C / W ) P D = power dissipation in package ( W ) The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple junction and over approximately one mm of wire extending from the junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire. 4.2 scillator and PLL Electrical Characteristics The MPC5125 system requires a system-level clock input SYS_XTAL. This clock input may be driven directly from an external oscillator or with a crystal using the internal oscillator. There is a separate oscillator for the independent real-time clock (RTC) system. The MPC5125 clock generation uses two phase-locked loop (PLL) blocks. Freescale Semiconductor 43