CONVENTIONAL phase-locked loops (PLL s) use frequency

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1 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 34, NO. 6, JUNE Superharmonic Injection-Locked Frequency Dividers Hamid R. Rategh, Student Member, IEEE, and Thomas H. Lee, Member, IEEE Abstract Injection-locked oscillators (ILO s) are investigated in a new theoretical approach. A first-order differential equation is derived for the noise dynamics of ILO s. A single-ended injection-locked frequency divider (SILFD) is designed in a 0.5- m CMOS technology operating at 1.8 GHz with more than 190 MHz locking range while consuming 3 mw of power. A differential injection-locked frequency divider (DILFD) is designed in a 0.5-m CMOS technology operating at 3 GHz and consuming 0.45 mw, with a 190 MHz locking range. A locking range of 370 MHz is achieved for the DILFD when the power consumption is increased to 1.2 mw. Index Terms Analog and digital frequency dividers, injectionlocked oscillators, radio-frequency integrated circuits. (a) I. INTRODUCTION CONVENTIONAL phase-locked loops (PLL s) use frequency dividers in their feedback path to achieve frequency multiplication. Most PLL s designed for wireless systems use flip-flop-based digital frequency dividers. These dividers are wide band and their power consumption increases with the frequency of operation. In frequency synthesizers used in modern wireless systems, frequency dividers consume a large percentage of the total power [2], [8]. Most often, offchip frequency dividers are used as the first stage in a stack of dividers in high-frequency PLL s [8]. The limitation on power and maximum frequency of operation of conventional digital frequency dividers is associated with the wide-band nature of these dividers. However, since most wireless systems are themselves narrow band, narrow-band analog frequency dividers may be used to reduce power and increase the maximum frequency of operation. Regenerative frequency dividers [Fig. 1(a)] are the most widely used analog frequency dividers [5] [7]. Frequency division in such a divider results from combining frequency multiplication in the feedback path with mixing at the input. Regenerative dividers can operate at frequencies higher than flip-flop-based dividers [13]. However, they require many functional blocks to guarantee frequency division [7]. As a result, regenerative frequency dividers are not the best solution for low-power systems. Parametric frequency dividers [Fig. 1(b)] are another group of analog frequency dividers used in microwave systems [3], [5], [15]. The frequency division principle of a parametric frequency divider relies on exciting a varactor at frequency and realizing a negative resistance that sustains a loop gain of unity at. High varactors and inductors are key Manuscript received October 5, 1998; revised February 22, The authors are with the Center for Integrated Systems, Stanford University, Stanford, CA USA ( hamid@smirc.stanford.edu). Publisher Item Identifier S (99) (b) Fig. 1. Analog frequency dividers: (a) regenerative frequency divider and (b) parametric frequency divider. elements in parametric frequency dividers [15]. Since high passive elements cannot be implemented in contemporary silicon technologies, parametric dividers are not amenable to integration. The third group, injection-locked frequency dividers (ILFD s), work by synchronizing an oscillator with an incident signal. Depending upon the ratio of the incident frequency to the oscillation frequency, three classes of injectionlocked oscillators (ILO s) may be defined: first-harmonic, subharmonic, and superharmonic ILO s. In a first-harmonic ILO, the oscillation frequency is the same as the fundamental frequency of the incident signal [1], while in a subharmonic ILO, the incident frequency is a subharmonic of the oscillation frequency [4], [9], [14], [20]. Likewise, in a superharmonic ILO, the incident frequency is a harmonic of the oscillation frequency. Uzunoglu et al. [16], [17] used synchronous oscillators (SO s) as frequency dividers, without providing a physical model for the frequency division functionality of SO s. The SO proposed in [17] is a nonlinear oscillator with a very large internal gain and a saturated output amplitude (voltage limited). High bias currents are required to provide the large gain and to operate SO s in a voltage-limited amplitude regime. Therefore, SO s are not appropriate for low-power systems. Unlike SO s, superharmonic ILO s can be designed as very low-power frequency dividers [10]. In this paper, we present a new method to calculate the locking range of ILO s. We also introduce two different mechanisms for failure of injection locking. A differential equation is derived that models the noise dynamics of ILO s /99$ IEEE

2 814 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 34, NO. 6, JUNE 1999 Fig. 2. Model for a free-running LC oscillator. We assume that all frequency components of far from the resonant frequency of the tank are filtered out, so the frequency of the output signal can be written as. Thus, we need only consider intermodulation terms with frequency, that is,. For an th-order superharmonic ILO (i.e., ), the intermodulation terms with possess a frequency equal to of the incident frequency. The signal, which is the component of with frequency, can be written as Fig. 3. Model for an injection-locked oscillator. Measurements on a single-ended ILFD (SILFD) are compared with simulations. The simulation results of a differential ILFD (DILFD) are reported as well. Using a complex exponential to replace sines and cosines, and applying the oscillation condition, the output signal can be written as (6) II. MODEL FOR INJECTION-LOCKED OSCILLATORS An LC oscillator can be modeled as a nonlinear block, followed by a frequency selective block (e.g., an RLC tank), in a positive feedback loop as shown in Fig. 2. The nonlinear block models all the nonlinearities in the oscillator, including any amplitude-limiting mechanism. To have a steady-state oscillation, a loop gain of unity should be maintained. We would like to express the oscillation condition in terms of gain and phase criteria for reasons that will be clear later. The gain condition is satisfied if the output amplitude is the same as the amplitude of in an open-loop excitation of the system at the oscillation frequency. The phase condition requires that the excess phase introduced in the loop at be zero. With an additional external signal (i.e., the incident signal), this same model can be used to model an ILO. This model is shown in Fig. 3. To investigate the injection-locking phenomenon in an ILO, we define (1) (2) (3) is the incident signal, is the output signal, is the phase difference between those two signals, and and are the resonant frequency and quality factor of the RLC tank, respectively. The output of the nonlinear block may contain various harmonic and intermodulation terms of and. As shown in Appendix A, we can write as (4) or The real and imaginary parts of (8) can be separated as (7) (8) (9) (10) Equations (9) and (10) are the fundamental equations for a superharmonic injection-locked oscillator. The simultaneous solution of these two equations specifies and for any incident amplitude and any incident frequency or, equivalently, for any offset frequency. Equation (10) can be rearranged as (11) is Adler s locking range figure of merit [1]. The fundamental equations, (9) and (10), are very general but provide limited intuition. However, as shown in the next section, for the special case of (i.e., divide-by-two) and a third-order nonlinearity (i.e., ), (9) and (10) can be solved analytically, which allows the development of design insight. each. is an intermodulation coefficient of (5) A. Special Case ( and Is a Third-Order Nonlinear Function) For the special case of and, the only unknown in (10) is the input output

3 RATEGH AND LEE: SUPERHARMONIC INJECTION-LOCKED FREQUENCY DIVIDERS 815 phase difference, which means the phase condition can be satisfied independently of the gain condition (12) On the other hand, satisfying the gain condition and solving (9) results in an expression for the oscillation amplitude Fig. 4. ILO model used for noise analysis. (13) As (12) suggests, the locking range can be increased by increasing either or the incident amplitude. Increasing in an LC oscillator is equivalent to using an inductor with a larger value ( ). The self-resonant frequency of the inductor puts a limit on the maximum inductor size and effectively limits the locking range by failing to satisfy the phase condition. The increase of the locking range with the incident amplitude is also limited. When the term under the square root in (13) becomes negative, the gain condition fails and limits the locking range. As a result, injection locking fails and the locking range is limited by failure of either the phase condition (phase limited) or the gain condition (gain limited). The effect of each limiting mechanism on the noise performance of an ILO is discussed in more detail in Section V-A. As mentioned before, the locking range in an ILO is a function of the incident amplitude. So, by injecting the incident signal into a high-impedance node, the required incident power can be reduced significantly. Due to the high impedance of the gate of MOS transistors, MOS transistors are a good candidate for injection-locked oscillators. The underlying assumption in the derivation of (9) and (10) is that the resonant frequency of the LC tank does not change as the incident frequency changes. However, to achieve a larger tuning range, the free-running oscillation frequency of the ILO can be modified such that it tracks the incident frequency [11], [12]. III. NOISE IN ILO s To investigate the phase noise performance of an ILO, we first consider the response of a first-harmonic ILO to a deterministic sinusoidal noise. For convenience, the model for an ILO is repeated in Fig. 4 with the noise added to the summing junction. The noise can be either from the incident signal or from the ILO itself. The incident signal, output signal, and sinusoidal noise are represented by their equivalent phasors in Fig. 5 and mathematically defined as (14) (15) (16) When the output signal is injection locked to the incident signal in the absence of noise, the input output phase difference is constant. However, when sinusoidal noise Fig. 5. Phasor representation of signals in Fig. 4. with an offset frequency is added to the system, is no longer constant and the instantaneous output frequency is defined as (17) It is the variation of that generates phase noise in the output signal. As shown in Appendix B, can be approximated as (18) is the difference between the incident frequency and the free-running frequency,, and The input output phase difference can be written as (19) is the input output phase difference in the absence of noise and is a constant [ from (45)] and is the time-variant portion of. because. Hence (18) can be simplified to (20) (21) If, meaning that the incident frequency is not at the edge of a phase-limited locking range, can be approximated as (22)

4 816 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 34, NO. 6, JUNE 1999 Fig. 6. Noise transfer function of an ILO. Fig. 7. Schematic of the single-ended injection-locked frequency divider. which allows simplification of (20) to a first-order differential equation (23) The noise transfer function from to the output phase (23) is shown in Fig. 6. From (23) and Fig. 6, it is clear that an ILO has the same noise transfer function as a first-order PLL. The noise from the incident signal is shaped by the low-pass characteristic of the noise transfer function, and the output signal tracks the phase variations of the incident signal within the loop bandwidth. However, unlike a first-order PLL, the loop bandwidth of an ILO is a function of the incident amplitude and is larger for a larger incident amplitude. The interpretation of the noise transfer function is a little different if the noise comes from the ILO itself. Within the loop bandwidth, the noise from the ILO is suppressed by the ratio of the noise power to the incident power. Outside the loop bandwidth, the noise suppression increases by 20 db per decade of offset frequency, and a 1 phase noise region is observed. The noise dynamics in a superharmonic ILO are the same as those of a first-harmonic ILO, except is of that in a first-harmonic ILO due to the frequency division operation. So (23) for an th-order ILFD can be modified as (24) is no longer a simple function of but is determined by solving the superharmonic ILO s fundamental equations, (9) and (10). As the division ratio increases, the noise rejection increases proportionally. So in a divide-by-two ILFD, the output close-in phase noise is db lower than that of the incident signal. IV. CIRCUIT IMPLEMENTATION In this paper, we propose two different architectures for ILFD s. Fig. 7 shows the schematic of an SILFD. For simplic- Fig. 8. Schematic of the differential injection-locked frequency divider. ity, the biasing circuitry is not shown in this figure. A Colpitts oscillator forms the core of the SILFD. The incident signal is injected into the gate of M1. Transistors M1 and M2 are used in cascode, mainly to provide more isolation between the input and output. Transistor M2 is sized to be smaller than M1 by almost a factor of three to reduce the parasitic capacitance at the output node (drain of M2). As a result, a larger inductor can be used to resonate this reduced capacitance. As discussed in Section II-A, using a larger inductor increases the locking range. The power consumption is also reduced due to the increased effective parallel impedance of the LC tank, assuming that tank losses are mainly from the inductor. Last, Li and Ci in the gate of M1 are used to model the LC tank of the preceding LC oscillator. The analogy of this circuit with the model in Fig. 3 can be realized by observing that transistor M1 functions as the summing element for the incident and output signals. The schematic of a DILFD is shown in Fig. 8. The incident signal is injected into the gate of M3, which delivers the incident signal to the common source connection of M1 and M2. The output signal is fed back to the gates of M1 and M2. The output and incident signals are thus summed across the gates and sources of M1 and M2. The common source connection of M1 and M2, even in the absence of the incident signal, oscillates at twice the frequency of the output signal, which makes this node an appropriate injection node for a divide-by-two operation.

5 RATEGH AND LEE: SUPERHARMONIC INJECTION-LOCKED FREQUENCY DIVIDERS 817 Fig. 9. Die micrograph of the SILFD ( mm 2 ). V. SIMULATION AND MEASUREMENT RESULTS A. Single-Ended ILFD The SILFD shown in Fig. 7 is designed in a 0.5- m CMOS technology and operates on 2.5 V and a bias current of 1.2 ma. The free-running frequency of oscillation is 920 MHz, and the incident frequency is around 1840 MHz. Both inductors are on-chip spiral inductors with patterned ground shields [18], [19]. The die micrograph of the SILFD is shown in Fig. 9. The total area of the die is 0.7 mm (0.7 1mm). The oscillation amplitude of the SILFD is plotted in Fig. 10 as a function of the incident frequency for different incident amplitudes. The locking range is determined by the frequency difference between the two ends of each curve. At small incident amplitudes, the locking range is phase limited, as explained in Section II-A, and increases with the incident amplitude. However, for incident amplitudes beyond 300 mv, the locking range is gain limited and shrinks as the incident amplitude increases. Simulated and measured locking range as a function of incident amplitude are shown in Fig. 11. A locking range of more than 190 MHz (11% of the center frequency) is achieved when consuming 3 mw of power. The maximum locking range as a function of bias current is shown in Fig. 12. A locking range of more than 135 MHz is achieved with a bias current as low as 600 A. Phase noise measurement results are shown in Fig. 13. The thin solid line in this figure shows the phase noise of the freerunning SILFD. The thick solid line is the phase noise of the HP8664A signal generator used as the incident signal. The nonsolid lines are the phase noise measurement of the SILFD when locked to three different incident frequencies, referred to as middle-frequency, phase-limited, and gain-limited curves. Fig. 10. Oscillation amplitude in the SILFD. The middle-frequency curve is the output phase noise measured at an incident frequency in the middle of the locking range. The phase- and gain-limited curves are measured when the incident frequency is at the edge of a phase- and gainlimited locking range, respectively. At low offset frequencies, the divider output phase noise is almost 6 db lower than the incident phase noise, as is expected from the divide-by-two operation and predicted by (24). However, at higher offset frequencies, the excess noise from the divider increases the output phase noise. The farout phase noise at the edge of a gain-limited locking range is even worse than the phase noise of the free-running oscillator. The small oscillation amplitude at the edge of a gain-limited

6 818 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 34, NO. 6, JUNE 1999 Fig. 11. Locking range for the SILFD. Fig. 13. Phase noise measurement in the SILFD. Fig. 12. Locking range as a function of the bias current in the SILFD. locking range explains this higher phase noise of the ILFD at large offset frequencies. Despite the large close-in phase noise of the free-running ILFD, the divider phase noise tracks the phase noise of the incident signal for offset frequencies up to 100 khz. As a result, the ILFD can be designed for very low-power operation without sacrificing the noise performance of the system. Also, very low on-chip spiral inductors, with small physical dimensions, can be used in ILFD s. B. Differential ILFD A DILFD (Fig. 8) is designed in a 0.5- m CMOS technology. The supply voltage is 1.5 V and the tail current is nominally 300 A. The DILFD oscillates at 1.6 GHz in freerunning operation, and the incident frequency is in the vicinity of 3.2 GHz. On-chip spiral inductors with a of 5.8 are used in this design. The oscillation amplitude as a function of incident frequency is shown in Fig. 14. Comparing this with Fig. 10, two differences are observed. In Fig. 14, the curves are flatter and the locking range increases monotonically with incident amplitude. These suggest that the locking range in the DILFD is phase limited, unlike the gain-limited locking range in the SILFD at large incident amplitudes. This can partially be due to the subunity voltage gain of M3 in Fig. 8. As a result, the amplitude of the injected signal at the summing node (the common source connection of M1 and M2) of the DILFD is less than that of the SILFD. Also, the increased tail current in the presence of a large incident signal changes, which can effectively change the phase-limited region of the locking range in DILFD s. More than 190 MHz of locking range is achieved with only 0.45 mw of power (Fig. 14). By increasing the power to 1.2 mw, the locking range increases to 370 MHz (12% of the center frequency). The DILFD is expected to have a better phase noise than the SILFD over the entire locking range, due to its phase-limited locking range. The performance of the SILFD and DILFD is summarized in Table I. For comparison purposes, the performance of a conventional frequency divider made out of two back-to-back connected source-coupled-logic (SCL) latches designed in the same technology is also tabulated. The SCL divider operates at about half the frequency of the DILFD and consumes more than four times the power. The SCL divider also fails to operate above 3 GHz. The last column in Table I shows the simulated acquisition time in ILFD s. The acquisition time, which measures how fast an ILFD locks to an incident signal, is inversely proportional to the locking range. Therefore, as long as the locking range is phase limited, increasing the incident amplitude reduces the acquisition time. C. Noise Transfer Function To verify the noise dynamics derived in Section III, the SILFD is injection locked to an incident frequency while a second signal is injected at different offset frequencies from the incident frequency. As demonstrated in Fig. 15, two sidebands are generated in the output signal spectrum. The power below carrier of the sidebands is measured at different offset frequencies and is shown in Figs. 16 and 17. In Fig. 16, the incident power is constant and the noise transfer function is measured for three noise power levels.

7 RATEGH AND LEE: SUPERHARMONIC INJECTION-LOCKED FREQUENCY DIVIDERS 819 Fig. 14. Oscillation amplitude in the DILFD. TABLE I FREQUENCY DIVIDER PERFORMANCE Fig. 16. Noise transfer function in the SILFD (P i = 040 dbm). noise transfer function measurement results of Figs. 16 and 17 are in very good agreement with (24). Fig. 15. Sideband generation due to noise injection at a frequency offset from the incident frequency. As predicted by (24), reducing the noise power by 3 db shifts the noise transfer function curve down by the same amount. The same measurement is repeated for different incident powers while keeping the noise power constant. The results are shown in Fig. 17. When the incident power increases by 3 db, both the loop bandwidth and the close-in noise rejection increase by 3 db, while the far-out noise does not change. The VI. CONCLUSION A new method is reported for calculating the locking range of injection-locked oscillators. Two different mechanisms for the failure of injection locking are introduced. It is shown mathematically that the noise transfer function of an ILO is the same as that of a first-order PLL. Two novel circuits for singleended and differential ILFD s are proposed. The measurement results of the SILFD verify the theory of injection locking and the model for the noise dynamics of ILO s. It is shown that ILFD s can operate at frequencies conventional digital frequency dividers fail and still consume less power than digital frequency dividers operating at lower frequencies (Table I). Unlike digital frequency dividers, the power consumption in

8 820 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 34, NO. 6, JUNE 1999 Now to complete the proof, insert (32) into (29) and replace by (35) Fig. 17. Noise transfer function in the SILFD (Pn = 070 dbm). an ILFD does not increase linearly with the frequency of operation. Therefore, injection-locked frequency dividers are attractive for digital CMOS frequency dividers, especially for low-power and high-frequency wireless systems. APPENDIX A To simplify the proof of (5), we redefine,, and as (25) (26) (27) and. Function is periodic with respect to both and. For every, we can define a periodic function as (28) Since and can be represented by its Fourier series as (29) each is a Fourier series coefficient of and is calculated as (30) APPENDIX B To derive (23), we start by evaluating the excess phase introduced in the loop, excluding the phase added by the frequency selective block in a first-harmonic ILO. The phasor representation of, (Figs. 4 and 5), is calculated as the vector sum of,, and. As experiences the nonlinearities of, new harmonics are generated, but, the component of with the same instantaneous frequency as, stays in phase with. So, the phasor representation of, and have the same direction, as shown in Fig. 5. The phase difference introduced between and is equal to (36) is the phase difference between and (vector sum of and ) and is the phase difference between and (Fig. 5). Since, we can approximate and as (37) (38) (39) (40) To satisfy the phase condition, should be canceled out by the phase introduced by the RLC tank. Thus (41) (42) and (31) Since each is even and periodic with period, it can be represented in terms of its Fourier series as (32) (33) (34) terms (43) is replaced by its equivalent from (17). To calculate, we insert (43) and (36) into (41) and rearrange the Equation (44) can be further expanded by replacing from (37) and (39) (44) and (45)

9 RATEGH AND LEE: SUPERHARMONIC INJECTION-LOCKED FREQUENCY DIVIDERS 821 Now if we replace by from (40) and expand, (45) can be written as Since, we can approximate as which ends our derivation. (46) (47) ACKNOWLEDGMENT The authors would like to acknowledge Dr. A. Hajimiri and R. Betancourt for their valuable discussions and comments. They are also grateful to Rockwell Semiconductor for fabricating the SILFD. REFERENCES [1] R. Adler, A study of locking phenomena in oscillators, Proc. IRE, vol. 34, pp , June [2] T. S. Aytur and B. Razavi, A 2-GHz, 6 mw BiCMOS frequency synthesizer, IEEE J. Solid-State Circuits, vol. 30, pp , Dec [3] I. Bahl and P. Bhartia, Microwave Solid State Circuit Design. New York: Wiley, [4] A. S. Daryoush, T. Berceli, R. Saedi, P. Herczfeld, and A. Rosen, Theory of subharmonic synchronization of nonlinear oscillators, in IEEE MTT-S Dig., 1989, pp [5] M. M. Driscoll, Phase noise performance of analog frequency dividers, IEEE Trans. Ultrason., Ferro-Elect., Freq. Contr., vol. 37, pp , July [6] R. G. Harrison, Theory of regenerative frequency dividers using double-balanced mixers, in IEEE MTT-S Dig., 1989, pp [7] V. Manassewitch, Frequency Synthesizers: Theory and Design. New York: Wiley, [8] C. G. S. Michael, H. Perrott, and T. L. Tewksbury, A 27-mW CMOS fractional-n synthesizer using digital compensation for 2.5-Mb/s GFSK modulation, IEEE J. Solid-State Circuits, vol. 32, pp , Dec [9] G. R. Poole, Subharmonic injection locking phenomenon in synchronous oscillators, Electron. Lett., vol. 26, pp , Oct [10] H. R. Rategh and T. H. Lee, Superharmonic injection locked oscillators as low power frequency dividers, in Symp. VLSI Circuits Dig., 1998, pp [11] H. R. Rategh, H. Samavati, and T. H. Lee, A 5 GHz, 32 mw CMOS frequency synthesizer with an injection locked frequency divider, in Symp. VLSI Circuits Dig., 1999, pp [12], A 5 GHz, 1 mw CMOS voltage controlled differential injection locked frequency divider, in CICC Dig., 1999, pp [13] B. Razavi, RF Microelectronics. Englewood Cliffs, NJ: Prentice-Hall, [14] I. Schmideg, Harmonic synchronization of nonlinear oscillators, Proc. IEEE, pp , Aug [15] G. R. Sloan, The modeling, analysis, and design of filter-based parametric frequency dividers, IEEE Trans. Microwave Theory Tech., vol. 41, pp , Feb [16] V. Uzunoglu, Z. Ma, and M. H. White, Coherent phase-locked synchronous oscillator (graphical design technique), IEEE Trans. Circuits Syst., vol. 40, pp , Jan [17] V. Uzunoglu and M. H. White, The synchronous oscillator: A synchronization and tracking network, IEEE J. Solid-State Circuits, vol. SC-20, pp , Dec [18] C. P. Yue, C. Ryu, J. Lau, T. H. Lee, and S. S. Wong, A physical model for planar spiral inductors on silicon, in Proc. Int. Electron Devices Meeting, 1996, pp [19] C. P. Yue and S. S. Wong, On-chip spiral inductors with patterned ground shields for Si-based RF IC s, in Symp. VLSI Circuits Dig., 1997, pp [20] X. Zhang, X. Zhou, B. Aliener, and A. S. Daryoush, A study of subharmonic injection locking for local oscillators, IEEE Microwave Guided Wave Lett., vol. 2, pp , Mar Hamid R. Rategh (S 98) was born in Shiraz, Iran, in He received the B.S. degree in electrical engineering from Sharif University of Technology, Iran, in 1994 and the M.S. degree in biomedical engineering from Case Western Reserve University, Cleveland, OH, in He currently is pursuing the Ph.D. degree in the Department of Electrical Engineering, Stanford University, Stanford, CA. During the summer of 1997, he was with Rockwell Semiconductor Systems in Newport Beach, CA, he was involved in the design of a CMOS dual-band, GSM/DCS1800, direct conversion receiver. His current research interests are in low-power radio-frequency integrated circuits design for high-data-rate wireless local-area network systems. He was a member of the Iranian team in the 21st International Physics Olympiad, Groningen, the Netherlands. Mr. Rategh received the Stanford Graduate Fellowship in Thomas H. Lee (S 87 M 87), for a photograph and biography, see p. 585 of the May 1999 issue of this JOURNAL.