Sensors and Actuators A: Physical

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1 Sensors and Actuators A 172 (2011) Contents lists available at ScienceDirect Sensors and Actuators A: Physical j ourna l h o me pa ge: Phototransistors for CMOS Optoelectronic Integrated Circuits P. Kostov,K. Schneider-Hornstein, H. Zimmermann Institute of Electrodynamics, Microwave and Circuit Engineering, Vienna University of Technology, Gusshausstr. 25/354, 1040 Vienna, Austria a r t i c l e i n f o Article history: Available online 8 April 2011 Keywords: Phototransistor CMOS Light Detector SoC a b s t r a c t Integrated pnp phototransistors (PT) built in 0.6 m OPTO ASIC CMOS are presented. The production starts with a low doped epitaxial wafer as bulk material. This work presents several different types of phototransistors due to the realization of base and emitter areas. The different types are optimized for different goals, e.g. responsivity or bandwidth. Responsivities up to 76 A/W, 35 A/W for DC light at 675 nm and 850 nm, respectively, as well as 37.2 A/W for modulated light at 300 khz and 850 nm wavelength were achieved. On the other hand bandwidths up to 14 MHz with lower responsivity were achieved with different design of base and emitter area. Due to the fact that the used process is a production silicon CMOS technology, cheap integration of an integrated optoelectronic circuit is possible. Possible applications are low cost, highly sensitive optical receivers, optical sensors, systems-on-a-chip for optical distance measurement or combined to an array even a 3D camera Elsevier B.V. All rights reserved. 1. Introduction The conversion of optical signals into electrical signals is done by photodetectors. Most common photodetectors are photodiodes (PD), avalanche photodiodes (APD) and phototransistors (PT). The goal of PTs as well as APDs is to increase the responsivity compared to simple photodiodes. PN diodes are the most common photodetectors and also easily integrated in CMOS technologies. They consist of a simple p n junction. Two different p n junctions can be used for the diode. Owing to the substrate anode, the n-well/p-substrate diode can receive photons of the complete visible and the near infrared (IR) spectrum although the near IR photons show a 1/e penetration depth of around 16.6 m in silicon [1]. The large penetration depths lead to long distances which the charges have to travel in the field free diffusion region. These diodes are rather slow but show a high responsivity for modern silicon technologies with a long carrier lifetime. The other junction which can be used is a p+/n-well diode. It is around 1 m thick and therefore every photon with larger penetration depths is lost for the photodiode. Each charge generated in the active diode area is rapidly collected due to short distances. This leads to fast but rather inefficient diodes. PIN diodes introduce an additional intrinsic layer into the photodiode which is in CMOS technologies usually a low-doped epi layer Corresponding author. Tel.: ; fax: addresses: plamen.kostov@tuwien.ac.at (P. Kostov), kerstin.schneider-hornstein@tuwien.ac.at (K. Schneider-Hornstein), horst.zimmermann@tuwien.ac.at (H. Zimmermann). grown on top of the standard substrate. This, often m thick epitaxial layer allows the PIN photodiode to overcome the limits of the PN diodes described before. The intrinsic zone between n and p area allows a thick space-charge-region (SCR) easily built by an electrical field due to a reverse bias voltage in the order of several volts. The bias voltage builds a thick drift zone, which means high velocity of the charge carriers and therefore combines the responsivity of the deep diode with the high speed abilities of the shallow one. For high speed communication applications the PIN PD is the most commonly used detector, e.g. [2]. Another interesting application of PIN PDs is distance measurement as single pixel [3] as well as line sensors [4] or as 3D camera [5]. However their performance is limited even under optimum circumstances to responsivities of 0.65 A/W and 0.55 A/W for 850 nm and 650 nm, respectively [1]. PDs do not have an internal amplification, which means that their maximum quantum efficiency is 1 when all photons generate carriers inside the diode. Both, APD and PT, have the goal to exceed this limit by different approaches. The internal amplification inside the photodetector of very weak signals is extremely interesting in each and every application field. Maximum distances and responsivities can be increased or the power of the light source can be decreased for the same performance. APDs achieve their amplification by the avalanche multiplication process. The drawback of this process is that several tens of volts are necessary to maintain the process [6]. This is a huge handicap when it comes to integration and SoCs. Nevertheless, in [7 9] special kinds of CMOS APDs, the so called single-photon avalanche diodes (SPADs), with breakdown voltages between 9.4 V and 17.2 V are reported. However, APDs show a very narrow bias voltage range for linear operation and therefore nonlinear behavior /$ see front matter 2011 Elsevier B.V. All rights reserved. doi: /j.sna

2 P. Kostov et al. / Sensors and Actuators A 172 (2011) Fig. 1. Schematic and cross section of conventional CMOS-integrated phototransistor. is expected for any changes of the bias voltage. Background light is also amplified in APDs, which can lead to saturation of the pixel circuit. Furthermore, background light amplification also occurs in PTs, which leads almost to the same problems as with APDs. Nevertheless there are many application fields for APDs, but of course complex control circuits to compensate the effects described above are necessary. Ref. [10] describes an APD for 430 nm light and a reported sensitivity of 4.6 A/W with a reverse bias voltage of 19.5 V. For red and infrared light, the detection probability decreases and much lower responsivities result. As opposed to APDs PTs do not need such high voltages to gain the current amplification. This is the most important advantage of PTs. The base collector junction of the PT forms a photodiode with a bipolar transistor for current amplification. The charges generated in the base collector diode are separated and swept into base and collector for a pnp transistor the electrons are swept into the base area and the holes into the collector (Fig. 1). The electrons in the base lower the base potential and holes of the p+ emitter are injected into the base. This leads to an amplification of the primary photocurrent, which is generated in the base. Ref. [11] reports a bipolar PT in standard-buried-collector (SBC) technology for 850 nm light with a responsivity of 2.7 A/W. This low value is caused by the low thickness of the base collector space charge region, which is only about 1 m in the SiGe bipolar transistors of [11]. Another SiGe bipolar PT with responsivities up to 5.2 A/W at 850 nm and 9.5 A/W at 670 nm is reported in [12]. [13] reports about a vertical bipolar npn PT with a responsivity of 3.2 A/W for 840 nm and a maximum current gain ˇ of 70. Npn PTs for the blue spectral range with current gains up to 158 and responsivities up to 0.25 A/W are reported in [14,15]. A pnp PT with a current gain of 300 and a maximum bandwidth of 7.8 MHz at 638 nm is shown in [16]. Some results of this work are presented in [17]. In this work we present integrated silicon PTs, which achieve much higher responsivities than these bipolar SBC PTs by implementing a thick intrinsic layer for a wide spread of the base collector SCR. Additionally we investigate different layouts optimized for different goals such as high responsivity or high speed. The possibility to integrate the PTs in a cheap CMOS technology exists to realize optoelectronic integrated circuits (OEICs) as system-on-chip (SoC). OEICs offer several advantages, e.g. smaller area due to only one die instead of two (one for photodetector and one for circuits). Therefore, there are no bond wires. An OEIC is much easier to handle and to package and there are many advantages more. Due to the fact, that the PTs only need low voltages compared to APDs and show a high responsivity due to the current amplification, they are suited for optocouplers, active pixels, light barriers and so on. 2. Device layout Several 100 m 100 m and some 10 m 10 m pnp-type PTs were implemented using a 0.6 m OPTO ASIC CMOS process. Typically PIN PDs are implemented in the OPTO ASIC process. The only difference to this process was a special wafer. The used wafers Fig. 2. Base designs, cross section of PIN PNP phototransistor with (a) n-epi, (b) n- well, (c) modulated n-well (B: base, E: emitter, C: collector, nw: n-well, pw: p-well). have a shallow n-epi layer on top the standard p /p + epi-wafer. The thickness of the p-epi layer is about 15 m with a doping concentration of about cm 3 while the n-epi layer is about 1 m thick and shows a doping concentration of about cm 3. A thick collector base SCR is possible due to the thick epi layer even for low voltages (compare PIN photodiodes). It also enables the reception of deep penetrating light with e.g. 850 nm wavelength. Nevertheless, the bandwidth of PTs is lower than the bandwidth of PIN-PDs because of the capacitances between base and emitter C BE and between base and collector C BC as well as because of the base transit time B which is no issue in a PD. The 3 db bandwidth of a PT is mainly defined by [18]: f 3dB = 1 2ˇ ( B + (k B T/qI E )(C BE + C BC ) ) (1) where f 3dB is the 3 db bandwidth of the phototransistor, ˇ is the forward current gain of the phototransistor, B is the base transit time, k B is the Boltzmann constant, T is the absolute temperature, q is the elementary charge, I E is the emitter current of the phototransistor, C BE is the base emitter capacitance and C BC is the base collector capacitance. The characteristics of the PTs are primarily defined by their layout. The work of [10,19] inspired the base and emitter layout engineering presented here. In the following there are different types of base layouts (n-region) and emitter layouts (p-region) as well as their performance described Base layout The base is implemented in the shallow low-doped n-epi layer. The base doping can be varied by additional n-wells inside the n- epi layer. This work uses three different base layouts. Fig. 2 shows the different layouts of the base. In Fig. 2(a) the lowest doped base is depicted. Here no additional n-wells, except for contacting the area, are implemented which leads to an increased thickness of the SCRs for the base collector diode and for the base emitter diode. This leads to smaller capacitances C BC and C BE. Additionally, the minority carrier transport time is decreased due to the increased drift component. This corresponds

3 142 P. Kostov et al. / Sensors and Actuators A 172 (2011) Fig. 3. Different emitter layouts with modulated n-well base (top view), (a) full plane, (b) stripes, (c) point. to a decreased effective width of the base and has the disadvantage, that for too large SCRs the base thickness will be zero and the SCRs touch each other with the effect of a reach through current between emitter and collector which is dependent on the collector emitter voltage. The second version of the base layout is shown in Fig. 2(b). Here an n-well over the complete base area is realized and therefore the doping concentration is significantly higher than above. The results of the higher doping are increased capacitances and an increased effective base thickness. Therefore the speed of the device is slower and with the high effective thickness also the current gain ˇ decreases 1 ˇ = (W 2 B /2 (2) bd p ) + (D n W B N D /D p L n N A ) where ˇ is the forward current gain of the phototransistor, W B is the effective base width, b is the minority carrier lifetime in the base, D p is the carrier diffusion coefficient of holes in the n-type base, D n is the diffusion coefficient of electrons in the p-type emitter, L n is the electron diffusion length in the emitter, and N D and N A are the donor and acceptor densities in base and emitter[20]. A tradeoff between speed and amplification is aimed for in the third version shown in Fig. 2(c). Additional to the base n-epi layer n- well stripes with different width-to-spacing ratios are introduced. NW 1/3 : one third is n-well, two thirds are n-epi NW 1/2 : one half is n-well the other half is n-epi NW 2/3 : two thirds are n-well, one third is n-epi During the CMOS process the drawn stripes diffuse into an inhomogeneously doped base layer. This enables a variation of the base doping concentration even for a standard ASIC process Emitter layout Three different layouts of the emitter were investigated. Fig. 3 shows the top view of different emitter layouts and modulated n- well base. To reach a very homogenous electric field inside the PT, the full plane emitter (Fig. 3(a)) is used. The generated charges move only vertically and therefore have to travel over the shortest distances. However the disadvantages of this type are a low current density in the emitter as well as a high C BE. As the results below will show, the disadvantages dominate and lead according to (1) to a low 3 db cut-off frequency. Fig. 3(b) shows a striped emitter layout with 1.4 m emitter stripe width and 8.4 m space in between. The point structure depicted in Fig. 3(c) only shows a single emitter dot with 1.4 m 1.4 m. Both structures have in common, that the current density is higher and the base emitter capacitances are lower because of the smaller emitter area. Both effects increase the 3 db cut-off frequency. Of course there is a disadvantage, the electric field in the PT is not completely homogenous anymore and there- Fig. 4. Gummel plot of the 100 m 100 m PT with full n-well base and corner emitter at V CE = 1 V. fore the charge carrier have to travel over longer distances which leads to reduced gain due to recombination. Another version of the emitter was produced also, similar to the point emitter, with the small emitter area not in the middle of the PT but at the corner of the PT and therefore outside the light sensitive area. This structure enables the use of the opto-window which is available in the process, but due to better comparison with the other emitter designs the opto-window was not used. The responsivity would be increased with the opto-window, i.e. with an anti-reflection coating, by about 2 3 db depending on the wavelength. 3. Measurement results The characterization of the PTs was done by three different measurement setups. Gummel measurements were done to achieve the electrical current amplification, the DC responsivity was measured by sweeps of the light power at 675 nm and 850 nm wavelength and the AC responsivity was measured at 10 dbm as well as 21.2 dbm optical incident power, both at 850 nm. All measurements were done with a laser diode as light source with an extinction ratio of 2: Gummel measurement The 100 m 100 m as well as the 10 m 10 m PTs with the base consisting only of the n-epi layer as depicted in Fig. 2(a) show for an emitter collector voltage of 4 V a reach-through effect, because the base emitter and base collector SCRs touch each other as described above. All other types of the 100 m 100 m PTs work properly and show the expected behavior. The current gain ˇ varies from 57 in case of the base consisting of the full n-well combined with the corner emitter (Fig. 4) to 176 for the striped transistor base of the type NW 1/3 combined with the small emitter point in the center. According to Eq. (2), PTs with lower doping concentration of the base (e.g. NW 1/3 ) have a higher current gain ˇ than PTs with higher doping concentration of the base (e.g. NW full ). This fact is due to a smaller effective base width W B. Compared to the larger PTs, the 10 m 10 m area PTs show a little bit better results for the current gain ˇ of up to 15 points for the same type of base and emitter design. The PT with the striped transistor base of the type NW 1/3 combined with the small emitter point in the center shows again the highest current gain ˇ of 190. A comparison of the current gain ˇ for both area sizes

4 P. Kostov et al. / Sensors and Actuators A 172 (2011) Fig. 5. Comparison of the current gain ˇ for the 10 m 10 m and 100 m 100 m PT with the 1/3 striped n-well and small center emitter point at V CE = 1 V. Fig. 7. Responsivity vs. optical power for different types of PTs at V CE = 4 V and floating base (NW 1/2 E ctr: base: n-well stripes, emitter: point in the center; NW 1/2 E full : base: n-well stripes, emitter: full plane; NW full E full : base: full n-well, emitter: full plane). Fig. 6. Gummel plot of NW 1/3 base and full plane emitter operating on the edge of reach through at V CE = 1 V. of this PT is depicted in Fig. 5.The oscillations at low base emitter voltages in Fig. 5 are due to measuring inaccuracy caused by the measuring setup and base currents in the pa range. PTs on the edge of reach-through show a different behavior. The graphs in the Gummel plot for I B and I C are not parallel anymore. The 100 m 100 m area NW 1/3 base combined with full emitter is an example for such a transistor. In case of low currents, ˇ reaches values up to Fig. 6 shows the Gummel plot of this PT. To protect the device from damage, the current was limited to 10 ma. In this measurement the dark current was about 4.56 A with a collector emitter voltage of 4 V. All other types of PTs showed a dark current of about 60 pa.in the CMOS fabrication process the striped n-wells diffuse into an inhomogeneously doped base. Due to Fig. 8. Responsivity vs. optical power for three different collector emitter voltages of the PT with striped n-well base NW 1/2 and a full emitter plane at 675 nm. this effect the distance between both SCRs is not constant, which leads to a reach-through effect in the device with the full plane emitter and NW 1/3 striped base. Since the small center emitter of the second PT with NW 1/3 striped base is placed directly over a drawn n-well, reach-through is not occurring for that device. For all other highly doped striped base (NW 1/2, NW 2/3 ) PTs the distance between both SCRs is accordingly thicker, which prevents Table 1 Responsivity in A/W of two PTs for three different collector emitter voltages at an optical power of 30 dbm at 675 nm and 850 nm. = 675 nm = 850 nm V CE = 1 V V CE = 4 V V CE = 8 V V CE = 1 V V CE = 4 V V CE = 8 V NW 1/2 E full NW 1/2 E ctr

5 144 P. Kostov et al. / Sensors and Actuators A 172 (2011) Fig. 9. AC measurements for different types of PTs, upper diagrams for low ( 21.2 dbm) optical power and the diagrams on the bottom for high ( 10 dbm) optical power (both for 850 nm) at V CE = 5 V. Fig. 10. AC measurements for two types of PTs, upper diagrams for low ( 21.2 dbm) optical power and the diagrams on the bottom for high ( 10 dbm) optical power (both for 850 nm) at three different collector emitter voltages.

6 P. Kostov et al. / Sensors and Actuators A 172 (2011) a reach-through from occurring at the applied collector emitter voltage DC measurements The DC measurements were done at 675 nm and 850 nm light with different optical power, varied from 55 dbm to 11 dbm by an optical attenuator. A 50/50 beam splitter was used to monitor the optical power via an optical power meter. The responsivity was measured for three different types of transistors of 100 m 100 m size for 675 nm and 850 nm each. The collector emitter voltage was also varied from 1 V to 8 V. Fig. 7 shows the responsivity of three different types of PTs for an emitter collector voltage of 4 V.The responsivity decreases with increasing optical power. High optical power leads to an induced base current in the A range and furthermore to a largely reduced gain (see Fig. 5). The reduced gain causes a change of the PTs operating point and thereby a different responsivity. The DC performance of the PTs shows only a minor dependence on the collector emitter voltage (see Fig. 8 and Table 1). The maximum achieved responsivity was 35 A/W at 850 nm and 76 A/W at 675 nm light at an optical power of 55 dbm for the PT with striped n-well base NW 1/2 and a full emitter plane. For 850 nm light the influence of the SCR is larger, because it has a deeper penetration depth. The values varied from 36 A/W to about 10 A/W for 55 dbm optical power and are slightly below this for the higher optical power of 11 dbm. The measurements showed that the responsivity is less dependent on the optical power for the devices with full plane emitter or striped emitter. The responsivity changes only by around 20 % over the optical power sweep for these devices. Here again the device near reach through shows a completely different behavior. It shows a responsivity of about 23,000 A/W, dark current already subtracted, for the lower optical power and still about 80 A/W for the high optical power AC measurements Modulated light was used for the measurements of the dynamic responsivity as well as the bandwidth of the devices. The used optical power levels were 21.2 dbm as well as 10 dbm. The characterized devices were measured at three different collector emitter voltages: 2 V, 5 V and 10 V. To adjust the operating point of the PTs a sinking current into the base was applied via an on-chip 1 M resistor. Four types of Fig. 11. Responsivity-Bandwidth Product (RBP) for different types of PTs, (a) for 21.2 dbm optical power, (b) for 10 dbm optical power. 100 m 100 m area PTs at 5 different operating points were characterized by AC measurements. For the higher optical power the devices show a decrease of the responsivity for the operating points with larger base currents. The devices with small emitter area show a nearly constant responsivity over the variation of the base current. The PTs with large emitter, full plane or stripes, show a higher dependence of the responsivity Fig. 12. Step response of the PT with striped base of the type NW 2/3 with striped emitter area. Operating point conditions: P opt = nm, I B = 1 A, V CE = 2 V. (Axis-properties: x: 500 ns/dev, y: 5 mv/dev).

7 146 P. Kostov et al. / Sensors and Actuators A 172 (2011) Table 2 Rise times in ns for different types of PTs, upper table shows results for low( 21.2 dbm) optical power and the lower one for high( 10 dbm) optical power at a wavelength of 850 nm. V CE = 2 V V CE = 5 V V CE = 10 V I B = 0 A I B = 1 A I B = 2 A I B = 5 A I B = 10 A I B = 0 A I B = 1 A I B = 2 A I B = 5 A I B = 10 A I B = 0 A I B = 1 A I B = 2 A I B = 5 A I B = 10 A NW 2/3 E str NW 1/2 E str NW full E cor NW 1/2 E full V CE = 2 V V CE = 5 V V CE = 10 V I B = 0 A I B = 1 A I B = 2 A I B = 5 A I B = 10 A I B = 0 A I B = 1 A I B = 2 A I B = 5 A I B = 10 A I B = 0 A I B = 1 A I B = 2 A I B = 5 A I B = 10 A NW 2/3 E str NW 1/2 E str NW full E cor NW 1/2 E full on the collector emitter voltage, compared to the small-emitter devices. All operating points show nearly the same bandwidth, because the power of the incoming light already ensures a certain operating condition (Due to the moderate extinction ratio of 2 of the laser diode used, a rather large DC component of the light used for AC characterization is present. This DC light causes a primary DC base current, which speeds up the PTs.) The shape of the SCRs, on the other hand, has a large influence on the bandwidth. Varying the collector emitter voltage changes the SCRs and therefore the effective thickness of the base. For low optical power, the devices show a decrease of the responsivity with increasing base current for all types of PTs. Furthermore, the responsivity of PTs with point emitters is nearly constant over the complete collector emitter voltage swing. The large emitter devices, with full plane or stripes, show a significant increase of the responsivity with increased collector emitter voltages. The bandwidths of the devices depend mainly on the collector emitter voltage, but of course the layouts with small emitter points show the highest bandwidth. Figs. 9 and 10 summarize the measured results. Nevertheless, a figure of merit can be defined by multiplying the two main properties of the PTs, the responsivity and the bandwidth. Fig. 1 shows the Responsivity-Bandwidth Product (RBP) for different types of PTs and different collector emitter voltages. Fig. 11(a) shows the graphs for low optical power of 21.2 dbm and Fig. 11(b) shows the results for high optical power of 10 dbm. In both conditions the PT with striped base and also striped emitter shows the highest RBP for the highest reverse bias voltage. Furthermore transient measurements were done for these PTs. Fig. 12 shows the step function for the PT with the striped transistor base of the type NW 2/3 combined with the striped emitter. For this measurement the optical light power was 10 dbm at 850 nm. The PT was set up in an operating point by sinking a current of 1 A from the base and applying a collector emitter voltage of 2 V. The PTs were connected in emitter follower configuration. Their output signal was capacitively coupled to the 50 oscilloscope input via a bias tee. Rise-times for this, as well as for the other PTs at different operating point conditions are listed in Table Conclusion Integrated silicon phototransistors were presented in a CMOS OPTO ASIC technology. The only modification in the production was a different wafer, an n-epi-layer was grown on the standard p /p + wafer. The characterization of several types of PTs with different base and emitter layouts showed current amplifications up to 190 as well as responsivities up to 76 A/W for 675 nm and 35 A/W for 850 nm light, which is about 20 times better than the responsivity of the SBC npn PT in a SiGeBiCMOS process presented in [11]. The achieved bandwidths were up to 14 MHz. A device in an operating point close to reach through showed a current gain up to 50,000 for low optical input power. The device properties depend mainly on the layout of the PTs base layout as well as emitter layout therefore it is possible to design the optimal phototransistors for several optical sensing applications integrated in SoCs or imaging systems. References [1] H. Zimmermann, Integrated Silicon Optoelectronics, 2nd ed., Springer-Verlag, Berlin, Heidelberg, [2] R. Swoboda, H. Zimmermann, 11 Gb/s monolithically integrated silicon optical receiver for 850 nm wavelength, IEEE International Solid-State Circuit Conference, Digest of Technical Papers ISSCC 49 (2006) [3] A. Nemecek, K. Oberhauser, H. Zimmermann, Correlating PIN-photodetector with novel difference-integrator concept for range-finding applications, European Solid-State Circuits Conference, Proceedings of ESSCIRC (2005) [4] G. Zach, H. Zimmermann, A 2 32 range-finding sensor array with pixelinherent suppression of ambient light up to 120 klx, IEEE International Solid-State Circuit Conference, Digest of Technical Papers ISSCC 52 (2009) [5] G. Zach, M. Davidovic, H. Zimmermann, Extraneous-light resistant multipixel range sensor based on a low-power correlating pixel-circuit, European Solid- State Circuits Conference, Proceedings of ESSCIRC (2009) [6] S. Cova, M. Ghioni, A. Lacaita, C. Samori, F. Zappa, Avalanche photodiodes and quenching circuits for single-photon detection, Applied Optics 35 (12) (1996) [7] M. Gersbach, J. Richardson, E. Mazaleyrat, S. Hardillier, C. Niclass, R. Henderson, L. Grant, E. Charbon, A low-noise single-photon detector implemented in a 130 nm CMOS imaging process, Solid State Electronics vol. 53 (2009) [8] M.A. Karimi, M. Gersbach, E. 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Philipsborn, 10 Gbit/s on-chip photodetection with self-aligned silicon bipolar transistors, European Solid-State Device Research Conference, Proceedings of ESSDERC (1990) [14] A. Tibuzzi, G.F. Dalla Betta, C.C. Piemonte, C. Di Natale, A. D Amico, G. Soncini, High gain bipolar junction phototransistors with finger-shaped emitter for improved optical gas sensing in the blue spectral region, Sensors and Actuators A 136 (2007) [15] A. Tibuzzi, G.F. Dalla Betta, F. Ficorella, G. Soncini, C. Di Natale, A. D Amico, C. Piemonte, Finger emitter/base bipolar junction phototransistors for optical gas sensing in the blue spectral region, Proceedings of IEEE Sensors 3 (2004) , art. no.w3l-f. 2. [16] K. Kieschnick, H. Zimmermann, P. Seegebrecht, Silicon-based optical receivers in BiCMOS technology for advanced optoelectronic integrated circuits, Material Science in Semiconductor Processing 3 (2000)

8 P. Kostov et al. / Sensors and Actuators A 172 (2011) [17] P. Kostov, W. Gaberl, H. Zimmermann, in: European Solid-State Device Research Conference, Proceedings of ESSDERC, Integrated phototransistors in a CMOS process for optoelectronic integrated circuits (2010) [18] G. Winstel, C. Weyrich, Optoelektronik II, Springer, Berlin, Heidelberg, 1986, 97. [19] A. Marchlewski, H. Zimmermann, G. Meinhardt, I. Jonak-Auer, E. Wachmann, PNP PIN phototransistor with modulation-doped base, IET Electronics Letters 46 (16) (2010) [20] P. Gray, P. Hurst, S. Lewis, R. Meyer, Analysis and Design of Analog Integrated Circuits, Wiley, 2008, p.8ff. Biographies Plamen Kostov was born in Veliko Tarnovo, Bulgaria, in He received the Masters degree in electrical engineering from the Faculty of Electrical Engineering and Information Technology, Vienna University of Technology, Austria, in He joined the Institute of Electrodynamics, Microwave and Circuit Engineering at Vienna University of Technology in 2009 in order to pursuit the Ph.D. degree, working as a scientific researcher and project assistant. His main interests include photodetectors and optoelectronic integrated circuit design. Kerstin Schneider-Hornstein was born in St. Pölten, Austria, on February 15, She received the Dipl. Ing. degree from the Vienna University of Technology, Austria, in In 2004 she received her Dr. techn. degree at the Vienna University of Technology, Austria. Since 2001 she is with the Vienna University of Technology, Institute of Electrodynamics, Microwave and Circuit Engineering, Vienna, Austria. Her major fields of interest are optoelectronics and integrated circuit design. She is author of the Springer book Highly Sensitive Optical Receivers. Dr. Horst Zimmermann, received the diploma in Physics in 1984 from the Univ. of Bayreuth, Germany, and the Dr.-Ing. degree in the Fraunhofer Inst. for Integrated Circuits (IIS-B), Erlangen, Germany in Then, he was an Alexander-von-Humboldt Research-Fellow at DukeUniversity, Durham, N.C., working on diffusion in Si, GaAs, and InP until In 1993, he joined the Chair for Semiconductor Electronics at KielUniversity, Germany, where he worked on optoelectronic integration. Since 2000 he is full professor for Electronic Circuit Engineering at Vienna Univ. of Technology, Austria. His main interests are in design and characterization of analog nanometer CMOS circuits, and optoelectronic integrated CMOS and BiCMOS circuits. He is author of the Springer books Integrated Silicon Optoelectronics and Silicon Optoelectronic Integrated Circuits and Highly Sensitive Optical Receivers. He is also author and co-author of more than 300 publications. He is IEEE Senior Member since 2002.