POWER CONSUMPTION IN DIGITAL CIRCUITS

Transcription

1 POWER CONSUMPTION IN DIGITAL CIRCUITS Alain Guyot and Sélim Abou-Samra TIMA Laboratory, 46 Avenue Félix Viallet, F383 Grenoble France Abstract: This paper will first address the issues: why a voltage transition causes power dissipation, what causes a transition, what are useful and redundant transitions, how information redundancy may reduce the number of transitions, how to make information redundant by adding dependant bits, how to statistically measure the average number of transitions (or activity) and reduce it through redundancy. In a second part, the paper will show the incidence of scaling down the transistors on power dissipation. The third part will address the question: what is performance. At last, the fourth part will redefine complexity and concentrate on complexity versus dissipation.. REDUCING POWER Designing low-power high-speed circuits requires a combination of techniques at four levels: circuitry, architectures, algorithms, and system [,]. This work concentrates on the architecture level and considers a CMOS static technology. System Algorithm Architecture Circuit Figure Let us consider a part of a circuit that we call a functional cell. The power consumption of a functional cell is highly data dependent. So is the cell delay. For example, if a combinatorial cell receives twice the same input vector, the delays as well as the power consumption will be zero. Nevertheless, the approaches to evaluate the power and the delay are quite different. For the delay, we are interested in the worst case, given by the slowest possible path in the circuit, called the critical path. For the power, we are interested in the average consumption, so the approach will be statistical. It is worth noting that in self-timed design, we are also interested in average delays and that for power supply wire sizing we may be interested in the worst case current... How is energy dissipated Energy is dissipated because some signal voltage changes and charge or discharge a parasitic capacitance C l. For a V dd transition, switch is closed, an energy E = C l * V dd is drawn from the power supply V dd and an energy EC = C l * V dd is saved in the capacitance C l. The other C l * V dd is dissipated. For a V dd transition, switch is closed, no energy is drawn from V dd, but the V dd energy stored in Cl is dissipated. To exhibit this result, we can I V out consider that the current I flowing through the switch is constant. In fact this is almost true in CMOS Cl and anyway the result would hold for any current. V dd E Vdd V out EC T T Figure 3 dq We have I =, q = C l Vout dt. The energy E s saved in the capacitance is: q dq Vdd q Es = V out I dt = dt = dq Cl dt Cl Es = Cl * V dd The total dissipated energy Ed is : Ed = V dd I dt = V C l V dd Ed = C l * V dd Half of it is lost. dd dq

2 .. What causes transitions Transitions at a cell outputs are obviously caused by the input transitions. In a synchronous machine, all switching activity ultimately derives from the clock transitions. Let us see what activity the input transition may cause on a 4-output cell. a No transition b Useful transition c Static glitch d Dynamic glitch inputs outputs Figure 4 In this example a does not change, b and d have an useful transition, c and d has two redundant transitions. Useful transitions are easier to analyse, since they follow the rules of Boolean algebra. Redundant transitions are caused by different delays from the inputs to the same output and are more difficult to analyse and minimise. In the previous example we can count on the output chronogram that there are twice as many redundant activity as useful one at the cell output. A = Auseful + Aredundant.3. Redundant transition taxonomy Redundant transitions are also called glitches or spurious transitions or hazards. An even number of transitions is often called a static glitch (fig.4 c), an odd number of transitions a dynamic glitch (d)..4. Transition injection In static CMOS, transitions are injected into a circuit by a change of input. The average number of injected transitions is the sum of the number of changes over all possible input pattern pairs divided by the number of pattern pairs. It is called activity. In dynamic CMOS, there is precharge between every new input evaluations. So the activity does not depend on the input transitions but only on input values. Nevertheless, every logic value "" causes two transitions, one for the decharge and another for the subsequent prechage..5.. Information is redundant Suppose that we are not interested in the actual value of two bits x and y {,,,}, but in the sum s = x+y {,,} Let us introduce o = x y and a = x y, o and a are not independent ( a o), so they carry less information than x and y. x y o=x y a=x y s=x+y o + a We note that s = x+y = o+a. If x and y are equiprobable and independent, the probability of each line is the same: /4. To count up the transitions, we draw a table with the 4 possible old a new values for (xy), and the transitions number (Hamming distance) between them. xy All occurrences in the table are equiproblable. The average number of transitions is 6/6 =. Now we derive another table by recoding (xy) into (oa). Again, all occurrences in the table are equiproblable. The average number of transitions is now /6. The activity gain is 5 oa.5.. Information is made redundant Let us suppose now that we are interested in the actual value of the two bits x and y {,,,}. We add a third bit, i and code a = x i and b = y i. To decode x and y from (i,a,b) is straightforward since x = a i and y = b i. The code is redundant since for each value of (x,y) there are two possible values of (i,a,b). xy iab The value of i is chosen in order to minimize the transitions. This table gives the choice of the new value of (i,a,b) according to the new value of (x,y) and the old value of (i,a,b). xy

3 Again, all the occurrences in the table are equiprobable. The minimum number of transitions is and the maximum number is and the average is 4/3. As in the previous example, the activity is reduced by 5% Formalisation If all the bit values are equiprobable and independent the average activity is n i i. If only a maximum of n/ bits = n i Cn are allowed to change then the activity becomes n/ i = i n C i n+ [3] The trade off In.5. examples were provided on how to exploit redundancy or make information redundant in order to decrease activity and consequently power. But to achieve activity reduction, extra logic is added. This logic will bring both its own consumption and its own delay.. SCALING DOWN The table below gives the effect of dimensions reduction on power dissipation. Three consequences are examined: Reduction with constant electric field Reduction with constant supply voltage Lateral reduction (channel length only) Parameter Reduction model Constant field Constant voltage Channel length Length (L) /K /K /K Width (W) /K /K Voltage (V dd ) /K Oxide thickness (t ox ) /K /K Current (I=(W.V )/(L.) /K K K Transconductance (g m ) K K Junction depth (X j ) /K /K Substrate doping (N A ) K K Electric field in oxide (E) K Depletion zone (d) /K /K Load capacitance (C = V.L/ t ox) /K /K /K Delay (V.C/I) /K /K /K Effect of scaling on power consumption Static power (Ps) /K K K Dynamic Power (Pd) /K K K Energy per Operation (EPO) /K 3 /K /K Area (W.L) /K /K /K Power density (V.I/A) K 3 K Current density K K 3 K 3. WHAT'S PERFORMANCE? The word performance is subjective and the way it is commonly used in microelectronics can sometimes be misleading, as many understandings can be put behind depending on what is expected : throughput, energy per operation or energy per throughput. Performance metrics has been addressed in [4,5] and others. An overview of the different performance components are defined or reminded..5. Throughput If one is looking for the best throughput, then performance will be the delay D, regardless to any other parameter (area, energy consumption etc.). The delay is a decreasing function with Vdd. As a rule of thumb, it can be assumed that : D ~ α.vdd/(vdd-vt) () Where α is a constant depending on the technology for a given design style. This equation does not account for short channel effects; it is only a first order approximation. From equation () one can see that the delay requirements can always be fulfilled by increasing the supply voltage - in the limits of the technology tolerance and the model boundaries though (fig. 5). The delay is measured in nanoseconds. The throughput is the inverse of the

4 delay, and is given in MHz. Better delay models [6] are of course needed for accurate predictions. Delay (arbitray units) V t Supply voltage Figure 5: Gate delay vs. supply voltage V dd.6. Autonomy If the only constraint for a design is battery life (like in a watch for example), then the energy per operation is the metrics to use. Energy per operation EPO is the same as power delay product PDP, but the term Energy Per Operation is preferred here, as the delay (or the throughput) is not a constraint. Indeed, the energy required for an operation is proportional to Vdd (say Ed = β.vdd ) and the power dissipated depends on the frequency f : P = β.vdd.f = β.vdd /D; thus, P x D = PDP = β.vdd = EPO () EPO (Arbitrary unit) Supply voltage Vdd Figure 6: EPO vs. supply voltage So, EPO is a monotone function of Vdd (fig. 6) meaning that it can be made as small as required simply by lowering the supply voltage. Of course, this strategy is not compatible with increasing the throughput, and furthermore, there are technological limits for the reduction of the supply voltage. The EPO also depends on the architecture, i.e. on the operation to perform. This can be influenced by parallelism or pipelining schemes [5] that do not appear in eq. (). The EPO is measured in picojoules..7. Efficiency And what if both constraints, throughput and battery life, need to be satisfied? This means that the EPO has to be minimised in the same time as the delay. A compromise will be necessary, as, on one hand EPO is improved by lowering Vdd (fig. ) and on the other hand, delay improvement requires higher Vdd (fig. 5). This compromise is the minimum of the Energy Delay product EDP. EDP = EPO x Delay (3) Energy Delay Product (*e -5 J.s) V dd (V) Figure 7: EDP vs. V dd Using the coarse power and delay models shown in the previous paragraphs, it is easy to solve : EDP = (4) V dd The result is Vdd = 3Vt. Actually, this is a first order approximation, further refinements require more technology based considerations. The optimal supply voltage is lower in SOI than in bulk [7]. On figure 3 the EDP is plotted against Vdd for a ring oscillator designed in a.µm technology [8,9] with ( Vtn + Vtp )/ =.7V. the EDP is measured in pj/mhz. In this paper, the energy delay product will be called performance, and the nearly optimal

5 supply voltage of V (fig. 7) will be used for further optimisation of the EDP in the performance complexity space for both SOI and bulk technologies. 4. QUANTIFYING COMPLEXITY At first sight, one might be tempted to define complexity as being equal to the number of transistors regardless to the level of abstraction - very simple! But as this might be true at the system level, it becomes false at the gate level. In fact, the complex cell implementation of a given function takes usually fewer transistors. The reduction of the transistor count has a cost : a logical cost and a performance cost. The logical cost is the loss of the internal nodes (γ on fig. 8). This is a purely formal cost, as it does not affect the behaviour of the circuit. The performance cost will be discussed in the following sections. γ Transistor level benchmarks As the scale here is the number of transistors in series, the logical function performed doesn t matter. We assume here a Nand gate with to 8 inputs (fig. 6). All figures are given per bit; thus the loading capacitance has to be proportional to the number of inputs. The load is Cl = n.5ff where n is the number of inputs of the gate. The measured delay is worst case, i.e. the closest input to ground changes.... i... n... i... n V dd C l Figure 8 : Building complex gates Gate decomposition for higher speed or lower power is a well-explored topic [4,5,]. Alternative implementations of a logical function are given, but always without a complexity scale. The attempt is done here to define such a scale. Complexity metrics actually depends on the level of abstraction one is dealing with. Here, for lack of space, only transistor levels will be considered. In this section, complexity quantification schemes are proposed, as well as an experimental protocol..8. Transistor level A finer granularity is needed at the transistor level, and, at this level, the complexity of a gate does not depend on the function it performs. Complexity can though be considered as being proportional to the number of transistors in series. Comparisons can then be easily performed after normalisation. On this scale, the results are divided by the number of bits, and thus all figures are normalised per bit..9. Experimental Protocol This section discusses the benchmark circuits used to explore the performance/complexity space. All results are obtained by HSPICE simulations. EPO (Joule) EDP (Joule/Hz) Figure 9 : n input Nand gate Electrical simulations were carried out for bulk and SOI versions of the same technology; the results are discussed in the following section. 5. RESULTS AND DISCUSSION Figure shows the EPO and the EDP as a function of the logical depth for a 6-input Nand gate loading ff., ,5 9 8,5 8 7,5 7 Bulk SOI Bulk SOI Figure : EPO and EDP vs. logical depth 3 -,5 - -, On figure the EPO/bit and the EDP/bit are plotted against the number of transistors in series.

6 EPO/bit (Joules) EDP/bit (Joules/Hz),46,44,4,4,38,36,34 Bulk EPO/bit SOI EPO/bit Number of Serial Transistors Bulk EDP/bit SOI EDP/bit Figure : EPO/bit and EDP/bit vs. number of transistors in series 6. CONCLUSION Some comments and design directives can be drawn from these results : There is an optimal decomposition scheme for large functions in terms of EDP but not in terms of EPO (fig. ). In this case, the implementations with logical depth equals 3 and 5 (fig. ) give approximately the same EDP. Then of course, one should choose the implementation with the lower EPO and transistor count. The logical depth that minimises the EDP depends on the function being analysed and on the technology. From figure it can be seen that the difference in terms of EDP/bit between SOI and bulk increases with the number of transistors in series. This means that SOI favours complex gate design. This increasing difference comes mainly from the very small junction capacitance in SOI as compared to bulk, leading to faster switching of a larger number of transistors in series. The EPO/bit curves for bulk and SOI are parallel with a lower value for SOI. For both SOI and bulk, the EPO/bit decreases with complexity (the number of transistors in series) where the EDP/bit increases (fig. ). Thus, whether using SOI or bulk, if the battery life is the critical parameter, then one should make extensive use of complex cells. On the other hand, if the EDP (or energy per throughput) is the main issue, then complex function should be mapped on smaller cells. 5, , , ,5-3 -3, REFERENCES [] R. Brodersen, A. Chandrakasan and S. Sheng, Low-Power Signal Processing Systems, VLSI Signal Processing Yao, Jain, Przytula and Rabaey, Editors. IEEE Press, 99, [] R. Brodersen, A. Chandrakasan and S. Sheng, Low-Power Signal Processing Systems, VLSI Signal Processing Yao, Jain, Przytula and Rabaey, Editors. IEEE Press, 99, [3] M. Stan and W. Burleson "Bus-Invert Coding for Low Power I/O" IEEE Trans on VLSI system, March 995. [4] C. Piguet, Circuit and Logic Level Design, in Low Power Design in Deep Submicron Electronics, ed. by W. Nebel and J. Mermet, Kluwer, 997, ISBN X, pp [5] C. Piguet, Low-Power and Low-Voltage CMOS Digital Design, Microelectronics Engineering, Vol. 39, Elsevier, Dec. 997, pp [6] D. Auvergne, J. M. Daga and S. Turgis, Power and Delay Macro-Modelling for Submicronic CMOS Process : Application to Low Power Design, Microelectronics Engineering, Vol. 39, Elsevier, Dec. 997, pp [7] J.-P. Collinge, Silicon-On Insulator Technology : Materials to VLSI, nd Edition, Kluwer, 997, ISBN : X [8] S.J. Abou-Samra, P. A. Aisa, A. Guyot and B. Courtois, 3D CMOS SOI for High Performance Computing, In proc. of the 998 International Symposium on Low-Power Electronics and Design (ISLPED), Monterey, CA, August -, 998 [9] S.J. Abou-Samra, J. Arweiler and A. Guyot, Low Power SOI CMOS Multipliers : D vs. 3D, In proc. of the 4 th European Solid State CIRcuits Conference (ESSCIRC 98), The Hague, The Netherlands, September [] C. Mead, M. Renn, Cost and Performance of VLSI Computing Structures, IEEE JSSC-4, April 979, pp