Electrical Load Emulation using Power Electronic Converters

Transcription

1 Electrical Load Emulation using Power Electronic Converters Y. Srinivasa Rao Department of Electrical Engineering Indian Institute of Technology Mumbai, India ysrao@ee.iitb.ac.in Mukul Chandorkar Department of Electrical Engineering Indian Institute of Technology Mumbai, India mukul@ee.iitb.ac.in Abstract The paper presents a method of emulating electrical loads using power electronic converters. The loads include machines such as induction motors and its associated mechanical load and also more complex machine systems such as wind power generation systems. The load emulator is effectively a dynamically controllable source or sink which is capable of bidirectional power exchange with either a grid or another power electronic converter system. Using load emulation, the feasibility of connecting a particular load to a grid under various conditions can be studied in the absence of any electromechanical machinery. This paper considers the case of a power electronic Voltage Source Inverter VSI) emulating a three phase induction motor connected to a three phase ac grid. The VSI is operated in a mode where the current drawn from the ac grid is controlled by closed loop control. Experimental results have been provided to verify the scheme. I. INTRODUCTION Load emulation is the concept of controlling a power electronic converter such as a Voltage Source Inverter VSI) in such a manner that its behavior resembles that of an electrical load such as an induction machine. The load emulator can provide different load characteristics with which the control algorithms and inverter design can be tested. Therefore, load emulation allows the user to test both the hardware and the software of the inverter, thus offering a more flexible platform for testing inverters in a laboratory environment. The main component of load emulation is the algorithm that generates the desired currents to be drawn so as to mimic the actual load. The current controller ensures that the VSI draws or supplies currents that are as close as possible to the desired current references. It achieves this by connecting the inverter to a power electronic converter through an appropriate interface impedance. The power electronics of the virtual load simply consists of two back to back, three-phase, six-switch, bridge converters in conventional fashion. This arrangement allows bidirectional power to flow to and from the inverter. The power electronics is then controlled by the real time system DSP) to draw or source the currents to emulate the electromechanical system on an instant by instant basis. The load emulation system has regeneration capability, as the power flow from the inverter can be returned to the mains supply. While testing an inverter with an actual machine, the machine uses this power for rotation and it is therefore lost. Inverter under test ^ E Is L1 ADC Emulator Fig. 1. E Signal cond. DSP Load Model L2 I_ref I_act Schematic diagram of Load Emulator Converter bridge Modulator FPGA Current controller Although the converter losses will have to be practically supplied by the source, the testing would ideally be lossless as the power that the converter will draw can be fed back to another supply. This work is concerned with the issues involved in the use of power electronic converter to emulate machine type loads, and the limits within which load emulation can be achieved. For this purpose, special attention will be paid to three phase induction motor which acts as a reference load. II. PRINCIPLE OF LOAD EMULATOR The load emulator is composed of a bidirectional power converter and a digital closed loop control system. This emulator produces a programmable load or source currents, which can be connected directly to the power electronic inverter under test or utility) as a replacement for an electrical load. Fig. 1 depicts the schematic diagram of digitally controlled load emulator. In this block diagram, the digital controller consists of ADC, DSP and FPGA. The digital controller is interfaced with the inverter through signal conditioning circuit. The sensing of real time variables and their digitization are done by the ADC. The electrical load model is coded in DSP processor and generates reference currents for the current controller. The output of the digital current controller in DSP is fed to the PWM Modulator in FPGA section to generate the switching pulses for the inverter. Therefore the load emulator is effectively a power level active impedance controlled by

2 a digital control system. However the complexity of the emulation is limited only by the capability of the converter, interface impedances and the digital controller. III. CURRENT CONTROLLER DESIGN The performance of the emulator largely depends on the quality of the applied current control strategy [1]. Current control loop ensures that the converter together with three-phase line inductors draw an appropriate current from the inverter. The transient response of the current loops determines the tracking accuracy between the demanded and actual current drawn from the inverter being tested. Fig. 2 shows the diagram of a single phase VSI with its output inductor filter interfaced to a grid. The controller designed can be implemented for a three phase system with a three phase VSI as will be shown in the later sections. The system analysis and controller design are performed with respect to the single-phase system shown in the Fig. 2. The dc link of the VSI is considered to be a constant dc voltage V dc. The switches S 1 to S 4 are power electronic switches such as IGBTs with their associated anti-parallel diodes. The switching frequency of the devices has been chosen to be 1 khz. The output of the VSI is the switched voltage waveform uv dc where u = ±1 is the switching logic that controls the VSI. The resistor R f represents the loss in the inductor L f and the VSI. The grid has been represented by a voltage source v s of 23 V Root Mean Square R.M.S) value and 5 Hz frequency. 4 V + V dc Fig. 2. S 1 S 4 S 3 uvdc S 2 L f 1 mh) R f.1ω) i f v s 23 V 5 Hz Topology of the single-phase VSI with inductor filter The current i f through the filter inductor L f can be expressed in the Laplace domain as follows, I f s) = U cs)v dc V s s) 1) sl f + R f where U c s) is the Laplace transform of the continuous control signal u c that will be obtained from the controller. u c will be used to obtain the switching control signal u = ±1 shown in Fig. 2. The grid voltage v s can be considered as a disturbance signal while designing the controller. Therefore, the output I f s)) to control signal U c s)) transfer function of the system can be written in the Laplace domain from 1) as follows: Gs) = I f s) U c s) = V dc 2) sl f + R f The frequency response characteristics can be represented in a Bode plot as shown in Fig. 3. Magnitude db) Phase angle degrees) Fig Frequency response of the VSI with output filter inductor Controller Saturation i Sine fr + e u c u i f K Triangle G PWM Fig. 4. Closed loop current control scheme The objective of the VSI is to inject a current i f that is approximately equal to a desired reference i fr. A proportionalintegral PI) current controller can be designed to achieve the objective. Fig. 4 shows the closed loop control scheme employed for the VSI of Fig. 2. The PI controller Ks) is chosen as follows, Ks) = U cs) Es) =.3s + 15 s The controller Ks) will be implemented in digital form. The sampling time is chosen to be T = 2 μs. The controller of 3) can be expressed in the Z domain by using bilinear transformation as follows, Kz) = U cz) Ez) =.35z.295 z 1 The controller output at any instant of time nt can be obtained from 4), u c n) =u c n 1) +.35en).295en 1) 5) In the above equation, T has been dropped but is implicitly present in all terms. The closed loop transfer function G cl of the control scheme is written as, G cl s) = I f s) I fr s) = Gs)Ks) 6) 1+Gs)Ks) The frequency response characteristics for the closed loop control system is shown in Fig. 5. From Fig. 5, it can be observed that the gain of the closed loop system is unity for frequencies up to 1 Hz. Moreover, the phase lag is approximately zero for frequencies up to 1 Hz. Therefore, current 3) 4)

3 Magnitude db) V/div) 2.5A/div) va vb ia ib Phase angle degrees) V/div) 5V/div) 2.5A/div) 2.5A/div) vc Vdc ic Fig. 5. Closed loop frequency response of the system 1V/div) 4 Fig. 7. Utility voltage and 7 th order harmonic current of three phase emulator Fig isa_ref Response of current controller for 7 th order harmonic references i fr containing fundamental 5 Hz components can be tracked with negligible error. To enable the VSI to be able to inject currents containing harmonic components, the bandwih of the controller can be increased by appropriately adjusting the gain of the controller Ks). To study the bandwih of the proposed current controller 7 th order harmonic currents are given as reference currents to the controller. The continuous time system equations for harmonic oscillator are: x =+ωy x) = 7) y = ωx y) = 1 8) where x =sin7ωt and y =cos7ωt. Fig. 6 shows the tracking accuracy of current controller for 7 th order harmonic current. Fig. 7 shows the experimental waveforms with respect to utility voltages. The performance of the controller for the 7 th harmonic can be seen to be in accordance with the bandwih of the controller shown in Fig. 5. IV. THREE PHASE INDUCTION MOTOR MODEL A three-phase squirrel-cage induction machine is modeled using a two-phase d q model, formulated in the stationary isa stator reference frame with respect to the stator [2]. The system is represented using linear differential equations as follows: v ds = r s i ds + dλ ds 9) v qs = r s i qs + dλ qs 1) v dr = r r i dr + dλ dr + ω r λ qr 11) v qr = r r i qr + dλ qr ω r λ dr 12) λ ds = L ls + 3 ) 2 L ms i ds L msi dr 13) λ qs = λ dr = λ qr = L ls + 3 ) 2 L ms i qs L msi qr 14) L lr + 3 ) 2 L ms i dr L msi ds 15) L lr + 3 ) 2 L ms i qr L msi qs 16) d ω r = P 2 ) Tem T L J 17) T em = P λ dsi qs λ qs i ds ) 18) where the symbols v, i and λ represent the instantaneous voltage, current and motor flux linkage, respectively. Also the sub-script q and d refer to q-axis and the d-axis quantities respectively. The subscript s and r refer to the stator side and rotor side quantities respectively. Rotor angular velocity is denoted by ω r. The terms r s and r r are stator and rotor resistances respectively. The terms L ls, L lr and L ms are stator leakage inductance, rotor leakage inductance and magnetizing inductance respectively. The rotor inertia is denoted by J and the load torque by T L.

4 TABLE I INDUCTION MOTOR MODEL PARAMETERS r s =2.7Ω r r = Ω l ls =.1235 H l lr =.1325 H l m =.2485 H T l = Nm J = kgm 2 P = 4 LL vg = 415 V rms Freq. =5Hz Forward Euler Adam Bashforth Fig. 8. Real time simulation using Euler and Adams-Bashforth Method 4 2 isa_ref isa By applying a numerical integration method the model is solved at every time step. Integration gives the evolution of the state variables with time. The selection of a solver for the differential equations is a trade-off between the accuracy requirement and the algorithm complexity [3]. Adams-Bashforth method is used to solve the motor model equations 9 to 18. This is an explicit linear multi step method that depend on multiple previous solution points to generate a new approximate solution point. Even though Euler s method is easy to implement in real time systems, it has a serious flaw in its approach to determining the slope to use in taking each step of the iteration. The iteration step from t n to t n+1 uses only the slope at the endpoint. Adams-Bashforth method uses linear combination of earlier values like y n 1,y n 2,.., in order to reduce the number of times fx, y) [4]. A two-step Adams-Bashforth method is written as y i n +1) = y i n)+h 3 2 f iy 1 n),..., y N n)) 1 2 f iy i n 1),..., y N n 1))) 19) Fig. 8 shows the real time simulation of 3kW induction motor using Euler and Adams-Bashforth algorithm for a 2 μs time step. Using Euler algorithm the error varies for the time step 1 to 1 μs. However for time step <1 μs the results are identical. Therefore, for larger time steps Adams algorithm is more accurate and reasonably stable. V. EXPERIMENTAL RESULTS A three-phase experimental setup has been built in a laboratory to verify the accuracy of the proposed system. In this setup the power circuit is rated at 3 A rms, 415 V rms input/output line to line voltages and 75 V dc bus with three 33 μf capacitors. A laboratory type 3-phase 4-pole squirrel cage induction motor with the parameters mentioned in table I is taken as a reference model, and the reference currents are generated from this model. For experimentation the phase voltage for the motor model is set as 135 V rms and reference dc bus voltage set as 36 V Fig. 9. Induction motor a-phase stator current The interface impedance chosen to be L =4mH. Fig. 9 demonstrates the performance of load emulator for steady state and transient conditions of the stator a-phase current. The model is simulated in real-time to obtain the free acceleration characteristics of the machine when started directon-line with no load. While the motor is running under no load steady state, an 8% rated torque is suddenly applied at t =.5 seconds to the rotor in order to observe the transient behavior of the system. From Fig. 9 it is observed that the measured currents are nearly identical to reference currents. Fig. 1 shows the experimental waveforms of rotor mechanical speed, electromagnetic torque and active power drawn by the emulator. The oscillogram 11 shows the a-phase stator current. For the given parameter values shown in table I, the transient and steady state currents of the emulator are as desired. The current waveforms have nominal ripple and the control system is stable. The digital signal processor which is currently used to perform the simulation has a clock frequency of 75 MHz, which gives it an instruction cycle time of ns. The entire load emulation software is driven by an Interrupt service routine ISR). The main code background loop) consist of simply peripheral initialization Timers, ADC, Interrupt control and buffer). The remainder of the code is taken up entirely by Timer ISR. This ISR is invoked every 2 μs by the period event flag on Timer. Calculation of reference currents from model, sampling of ADC and generation of PWM waveforms for power switches are done within 2 μs. Table II shows the tasks performed and time taken by each task. The tasks carried out by DSP take 9.8 μs in total for a time step of 2 μs. Three analog to digital converters sample

5 rad/sec Watts Nm rotor mechanical speed electromagnetic torque time sec) active power 3Φ Pcc TABLE II PROCESSOR EXECUTION TIME FOR LOAD EMULATION Integration Time Step rate of execution) 2 μs Control cycle total process time) 9.8 μs Motor model 2.4 μs Current controller 1.93 μs ADC Sample time 3.42 μs Transformations 68 ns FPGA 1.39 μs Buffer 1.76 μs Reverse flow converter i dc Inverter Lf Cf Ls Grid / Inverter under test Fig. 1. Transient response of the emulator V dc ref Control system dc bus feed back Emulator a phase stator current Fig. 12. Block schematic of lossless emulator using reverse flow converter 5A/div) Fig. 11. Startup response of the emulator time is 3.42 μs and PI current controller execution time is 1.93 μs. Data conversion and communication between DSP and FPGA is 1.39 μs. Motor model using Euler algorithm is 1.52 μs and for Adam-Bashforth algorithm the execution time is 2.4 μs which is well justified in terms of precision. Buffer save task execution time is 1.76 μs and data transfer between PC and DSP buffer is offline. The measurements are taken with the help of external flag XF of the DSP processor. These results are sufficient for IM load emulation and can be more optimized when using better methods. VI. REGULATION OF DC BUS VOLTAGE In the block schematic of load emulator Fig. 1 initially the dc bus capacitor is charged with a diode bridge rectifier, so the dc bus voltage in no case falls during load emulation. However, when the load model is regenerative in nature, the emulator draws real power from the utility. This will result in the dc bus voltage increasing to dangerous values. Since the emulator needs to draw the currents as per the load model, it is not possible to regulate the dc bus voltage using existing control loop. Fig. 12 shows the block schematic of a lossless emulator for high power applications. In this system the emulator dc bus is connected to the three-phase mains supply via a regeneration unit. This unit transfers power from the emulator converter back into the mains supply when the dc bus voltage of the emulator rises above a predefined value. In this way power which is taken by the converter, and usually absorbed in a load, is returned to the mains supply. The power exchange is based on instantaneous power theory using pqr transformation. The control scheme for operation of the front end converter is well elaborated [5]. The main advantage of this front end converter that is it utilizes its entire capacity to return the power to the grid. Fig. 13 shows the experimental results of bidirectional active power exchange. The figure shows the instantaneous real powers drawn by the emulator and returned by the reverse power converter. VII. DSP-FPGA HARDWARE PLATFORM This section describes the digital hardware structure for implementation of load emulation. Fig. 14 shows the block diagram of DSP-FPGA digital hardware system. In this system separate digital controllers are employed to carry out data acquisition, communication and control [6] [7]. This system is centered on Texas TMS32VC33 Digital Signal Processor DSP), which is a high performance floating point processor with 34 K 32-bit on-chip SRAM. It supports 16/32 bit integer and 32/4 bit floating point operations. Communication between the host computer USB port and DSP is done using a USB controller. On board program/data transfer between the USB and the DSP is implemented using Texas MSP43F168 micro controller which acts as Communication Link Interface Manager CLIM). The role of CLIM is to convert synchronous serial data to 8-bit parallel form. In order to get flexible I/O

6 Watts Watts active +ve power active ve power Fig. 13. Synchronous Serial Data Bidirectional active power transfer by reverse flow converter Mixed signal controller DSP TMS32vc33 8 bit Data Address Control 12 bit USB Controller Data USB PWM O/P SPARTAN3 FPGA JTAG PROM discussed. This technique allows implementation of more complex models. For experimentation and real time verification, the design of a 32-bit floating point DSP processor interfaced to FPGA is described. The program environment and code was set up in assembly language of processor, which best utilizes resources and results in reduced execution time. Measured control cycle time and load model time are reported. REFERENCES [1] Marian P. Kazmierkowski and Luigi Malesani, Current control techniques for three-phase voltage-source PWM converters: A survey, IEEE Transactions on Industry Applications, vol. 45, no. 5, pp , October [2] P. C. Krause, O. Wasynczuk, and S. D. Sudhoff, Analysis of electric machinery, IEEE Press, [3] Y. Srinivasa Rao and M. C. Chandorkar, Numerical Integration Methods for Digital Power Electronics and Electrical Drives, in Proceedings of CIEE-5 National Conference on Computational Intelligence for Electrical Engineering pp. 2-24, November 25. [4] Vijay Raman, Explicit Multistep Methods in system simulation, ISCAS- 89 pp [5] R. R. Sawant and M. C. Chandorkar, A Multi-functional Power Electronic Compensator using Instantaneous p-q-r Theory, in Proceedings of 2nd National Power Electronic Conference, Indian Institute of Technology, Kharagpur, India pp , December 25. [6] Antonello Monti, Enrico Santi, Roger A. Dougal, and Marco Riva, Rapid prototyping of digital controls for power electronics, IEEE Transactions on Power Electronics, vol. 18, no. 3, pp , May 23. [7] Joep Jacobs, Dirk Detjen, Claus-Ulrich Karipidis, and Rik W. De Doncker, Rapid prototyping tools for power electronic systems: Demonstration with shunt active power filters, IEEE Transactions on Power Electronics, vol. 19, no. 2, pp. 5-57, March 24. CLOCK ADC 1 ADC 2 ADC 3 AD7864AS 2 AD7864AS 2 AD7864AS 2 CH 3 CH4 7 CH8 11 Fig. 14. Block diagram of DSP-FPGA platform interface and data acquisition, this system has three analog to digital converters and a Xilinx XC3S2 FPGA. Three AD7864-AS2 analog to digital converters are interfaced to sensor unit for data acquisition of voltage and currents. DSP is used as a processor which simulates the load model and generates the current references with a 75 MHz clock. FPGA act as a pulse wih modulator and control the power switches of the converter using 2 MHz clock reference. VIII. CONCLUSIONS This paper has discussed load emulation which is capable of simulating an electrical load in real-time with power electronic converter. The PI controller has been designed and implemented in DSP. The system was operated to simulate three phase induction motor model for steady state and transient conditions. Experimental results of emulator and reverse power converter for bidirectional active power exchange are