CHAPTER 6 THREELEVEL INVERTER WITH LC FILTER


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1 97 CHAPTER 6 THREELEVEL INVERTER WITH LC FILTER 6.1 INTRODUCTION Multi level inverters are proven to be an ideal technique for improving the voltage and current profile to closely match with the sinusoidal profile in order to reduce the voltage and current harmonics. Various filtering techniques discussed in previous chapters minimize the harmonics present in the stator input and torque ripple in the output of the BLDC motor. The passive filters used in minimizing the harmonics and torque ripple are limited to a narrow range of speed and load operation of the motor. The Fuzzy logic based dynamic pulse width modulation technique reduces the harmonics, but it needs adequate training to tune the fuzzy system based on the load requirements. The shunt active filter is effective in minimizing the current harmonics and the voltage harmonics is still to be reduced. Multi level inverter topologies are prominently used for shaping the voltage and current profile close to the sinusoidal profile. This in turn provides the smooth torque profile of the motor. So there is a need of altering the inverter system for the BLDC motor drive which can reduce the harmonics and improve the performance. The conventional twolevel inverter for BLDCM shall be replaced by the threelevel inverter where the voltage and current profile can be improved for minimizing the harmonics.
2 98 Multilevel inverters with different Pulse Width Modulation (PWM) techniques are proposed for medium and high voltage applications for converting the pulsating two level AC voltages to near sinusoidal nature. Rodriguez et al (2002) and Shi et al (2010) discussed different types of three phase multilevel inverters. Diode Clamped Inverter, Flying Capacitor Inverter and Cascade Inverter, Cascaded HBridge inverters are some of the multilevel inverter topologies applied to different applications. Threelevel inverter has many advantages such as low harmonic distortion, low switching frequency, and lower common mode voltages, near sinusoidal output voltage, less requirement of filtering. Wang & Ahmadi (2010) and Zare et al (2011) stated that the multilevel inverters have a unique advantage of low dv/dt, which reduces the danger of motor failure due to high frequency switching. Moreover, the possibility of achieving smooth sinusoidal profile by altering the switching pattern of the multilevel inverters is discussed. Perez & Leon (2010) Zhao et al (2012) pointed out that the threelevel diode clamped inverters are widely applied in control of medium voltage drives due to the simplicity in inverter topology and the ease of control methodology. Bouhali & Rizoug (2013) stated that higher level inverters are used to obtain a close match with the sinusoidal profile of voltage and current. With multilevel inverter topology it is possible to attain low Total Harmonic Distortion in both voltages as well as current. As the level of inverter increases, the complexity of the controller also increases and the cost of the controller also will increase. The objective of the work described in this chapter is to experiment the possible implementation of a diode clamped three level inverter as the commutation system for the BLDC motor to reduce the harmonic components in both voltage and current input to motor. A threelevel diode clamped
3 99 inverter cascaded with a low pass filter is found to be a low cost, less complex system, which can improve the performance of the BLDC motor. Figure 6.1 shows the overall functional block diagram of the threelevel inverter with the passive filter for the BLDC motor drive system which is discussed in this chapter. The conventional two level inverter which is the commutation system is replaced with the diode clamped threelevel inverter. The three phase output of the inverter is connected to the stator of the motor through the passive LC filter which can minimize the higher order harmonics present in the stator voltage and current. The field programmable gate arrays (FPGA) performs the control action to be implemented and generates the switching gate signals for the threelevel inverter in synchronization with the instantaneous position of the rotor. Drive System Filter + DC Input _ Three Level Inverter Passive LC Filter BLDCM G G12 Gate Signals Decoder/ Gate Drive System Three Level Inverter Hall Signals Controller (FPGA) Figure 6.1 Functional Blocks of the threelevel inverter with passive filter
4 100 This work is distinct from the conventional threelevel inverter applications used in power system applications. The conventional threelevel inverter operates with fixed fundamental frequency. But the threelevel inverter acts as the commutation system for the BLDCM operates with variable fundamental frequency proportional to the instantaneous speed of the motor. Further, the commutation sequence of each phase will be decided upon the Hall positional bits from the BLDCM. The gate switching signalss for this three level inverter operation is generated by the Field Programmable Gate Array which acts as the controller for this motor. 6.2 FUNCTIONAL ELEMENTS OF THE SYSTEM The functional elements of the three level inverterr based commutation system for the brushless DC motor drive is presented in Figure 6.2. The BLDCM is connected with the diode clamped threelevel inverter in cascade with the LC filter. The FPGA (Spartan 3) is used as the controller for the three level inverter to generate the 12 switching gate pulse for the three level operation of the inverter. The speed is controlled by the conventional voltage control method using PI control. i abc Signal Conditioner FPGA Controller Figure 6.2 Functional elements of the three level inverter based BLDC motor drive
5 101 The BLDCM consists of three Hall Sensors displaced in 120 each in the stator of the motor. This gives the instantaneous position of the rotor. Also the pulse width of a Hall sensor output pulse is directly proportional to the speed of the motor. The phase current data and the instantaneous speed of the motor are fed to the FPGA through the analog to digital converter which are used for speed control action. The switching signal to the inverter are combined with the PWM signals to perform the commutation and speed control of the motor. A low pass LC filter is used to filter out the high frequency harmonic components and to transform the stepped voltage output of the inverter to a smooth profile. 6.3 DIODE CLAMPED THREELEVEL INVERTER The diode clamped three phase threelevel inverter is shown in Figure 6.3. The DC voltage applied from the rectifier (V dc1 ) is divided into three voltage levels by the two bulk identical capacitors (C) connected in series. The central point between the capacitor is assigned as neutral point n and the lower reference point is assigned as 0. Figure 6.3 Diode clamped three Level inverter
6 102 The phase voltage between any phase to neutral point (V an, V bn, V cn ) has three states: V dc1 /2, 0, V dc1 /2. The two diodes D 1 and D 1 1 of phase a clamp the switch voltage half the level of V dc1. S a1, S a2, S a3 and S a4 are the switches on phase a. The fundamental modes of operation of diode clamped threelevel inverter for forward and reverse current is described in six current paths. The one phase of the inverter three level operation is shown in modes A, B, C, D, E and F as shown in the Figure 6.4. The A, B, C modes are for positive, zero and negative voltage states in the forward current direction. Figure 6.4 Fundamental modes of threelevel inverter operation for phase a Depends on the direction of current and the switching state the current chose either the switching device or the forward biased diode which is shown in Figure 6.4. The phase voltage with reference to the neutral point (V an ) is an AC voltage with three levels +V dc1, 0 and V dc1. The phase voltage with reference to the pointt 0 (V a0 ) is DC with three levels 0, +V dc dc1/2 and V dc1, the voltage difference between V an and V a0 is V dc1 /2. The switching states and the phase voltage levels for phase a is tabulated in Table 6.1.
7 103 Table 6.1 Diode clamped threelevel inverter output voltage level and switching states for phase a Switching states S a1 S a2 S a3 S a4 Phase Voltage (V an ) Phase voltage (V a0 ) V dc1 /2 +V dc V dc1 / V dc1 /2 0 The brushless DC motor is constructed with three Hall Sensors positioned in 120 apart on the stator. The stator windings of the BLDC motor have to be energized in coordination with the hall positional bits. The switching table for the three level inverter operations with hall positional bits is presented in Table 6.2. Table 6.2 Switching table for threelevel inverter for BLDCM Hall Input Inverter Switching Pulse Phase a Phase b Phase c States H A HB HC S a1 Sa2 Sa3 Sa4 Sb1 Sb2 Sb3 S b4 Sc1 Sc2 Sc3 Sc The Table 6.2 indicates the switching cycles for the switching devices of the three level inverter in order to obtain the continuous three phase output for the stator input of the motor. The 0 and 1 corresponds to phases indicates the ON and OFF states respectively of the switching devices for the three level inverter in coordination with the Hall sensor positional
8 104 three bit code. Figure 6.5 shows the simulated switching gate pulses for a specific phase a of the threelevel inverter. At any instant two switching devices will be in on state as per the switching table indicated in Table 6.2 Time (s) Figure 6.5 Threelevel Switching pulse for Phase a (S a1 S a4 ) 6.4 FPGA CONTROLLER FOR THREELEVEL INVERTER Programmable Gate Array (SPARTON 3E) is used to generate the 12 switching pulses of the threelevel inverter and also to perform the speed control of the motor. The three Hall sensor positional bits (H A, H B and H C ) are given as the input to the FPGA for deciding the commutation of stator coil of the BLDCM. The pre processed three phase current input is given as 12 bit digital data to the controller for PI speed control action. The speed control action is performed using the V/f control method. The speed of the motor is estimated from the hall pulses. The duration of each pulse is directly related to the speed. The top level schematic of the FPGA controller for threelevel inverter for the BLDC motor is presented in Figure 6.6.
9 105 Figure 6.6 Top level schematic of the FPGA controller for Threelevel inverter 6.5 DESIGN OF FILTER ELEMENTS The higher order harmonics produced during the switching of power devices of the inverter, causes EMI problems. Akagi & Tamura et al (2006) stated that the EMI problems can be rectified using a low pass filter with the appropriate frequency limit. The lower order harmonics are minimized by the threelevel inverter and the higher order harmonics are reduced by the passive low pass filter. The filter elements are designed based on the motor parameters and the range of fundamental frequencies of stator voltage. Table 6.3 Design Parameters Parameter Range Units Max. Motor EMF (Line Line) 200 Volts Speed (rated) 6000 rpm Stator Current (rated) 7.2 Amps Stator Resistance (LineLine) 10.4 Ohms Stator Inductance (LineLine) 43 MilliHenrys Number of poles 4 
10 106 The Design parameters and specification of the motor used for real of the time experimentation is given in Table 6.3. For the wide range of speed motor specified, for a 4 pole BLDC motor, the fundamental frequency of the stator voltage varies from DC level to 200Hz for the maximum speed of 6000rpm. The low pass filter is designed to limit the high frequency component of voltage above 200Hz. The filter elements are designed based on equation (6.1) and (6.2).. Z o L Henry * f c (6.1) 1 C Farads Z 0* * f c (6.2) Where Z o characteristic impedance in ohms, CCapacitance in Farads, LInductance in Henries, f c Cutoff frequency in Hertz. (a) Figure 6.7 (b) Low pass LC harmonic Filter a) Circuit b) Response of the filter
11 107 The Figure 6.7 shows the low pass LC filter and the response of the filter for the cutoff frequency of 200Hz. L 1 2 1is filter inductance, L 2  is considered as the lineline inductance of the stator winding, C filter capacitance. For the characteristic impedance of 50 ohms, based on the equation (6.1) and (6.2), value of L 1 and L 2 are approximately 43mH and the capacitance C is 31.83µF. 6.6 RESULTS AND DISCUSSIONS This work is simulated using MATLAB/Simulink environment to investigate the performance enhancement in terms of harmonics reduction. An experimental prototype was developed to test the effectiveness of the methodology. The experimented results and the simulated results confirm the reduction in harmonics Simulation Results The simulated stator voltage, stator current for the diode clamped threelevel inverter applied to BLDCM is presented for analyzing the reduction in harmonics. The phase phase stator voltage output of the threelevel inverter (V 1 ab, V 1 bc and V 1 ca ) before filtering is presented in Figure 6.8. The three level stator voltage profile exhibits the close match with the stepped sinusoidal profile.
12 108 Figure 6.8 Stator voltages between two phases of the threelevel inverter (V ab 1, V bc 1, V ca 1 ) Figure 6.9 Three phase stator voltage and current to the BLDCM with load of 2Nm The simulated three phase stator voltage and current during the steady operation of the BLDCM are presented in Figure 6.9. The stepped sinusoidal profile is transformed towards the smooth sinusoidal profile by the LC filter. The current profile also transformed towards the sinusoidal profile. This transformed voltage and current profile contain less harmonic components.
13 109 V (a) Time (s) A (b) Time (s) V (c) Time (s) A (d) Time (s) Figure 6.10 Stator voltage and current with a step change of load at 0.5 s (a) Three phase stator voltage (b) Three phase stator current (c) Phasephase stator voltage (d) Per phase stator current Figure 6.10 shows the simulated stator voltage and current with the step change of load (2Nm) at 0.5s time. Figure 6.10a shows the three phase stator voltage. The instant at which the load applied, the speed drops. The PI controller responds immediately to maintain the speed by increasing the stator voltage by the V/f control method. So a rise in stator voltage is observed after the load applied at the simulation time of 0.5s. Simultaneously the stator current also increases proportional to the load shown in Figure 6.10b. The phase to phase voltage and the phase current are shown in Figure 6.10c and 6.10d respectively.
14 110 (a) (b) Figure 6.11 a) Speed profile of the BLDCM (b) Torque Profile of BLDCM The speed and the torque profile of the BLDC motor are shown in Figure The simulation is carried out for the reference speed of 1000rpm and the closed loop PI speed controller is designed to maintain the speed. The load applied to the motor at 0.5s causes a dip in the speed and further the speed is maintained by the controller by increasing the stator voltage. The corresponding variation of torque is observed in Figure 6.11b. It is observed that the hysteresis width of the torque pulsation is reduced in threelevel inverter than the conventional two level inverter controlled BLDC motor.
15 111 (a) (b) Figure 6.12 (a) Simulated stator current profile and Harmonics graph (b) Simulated Stator voltage profile and harmonic graph The harmonic spectrum of the simulated stator voltage and stator current are presented in Figure The fundamental frequency is basically related to the speed of the motor and it is also proportional to the frequency of the backemf. Figure 6.12a presents the harmonic spectrum of the stator current, and is 4.32%THD. Figure 6.12b shows the harmonic spectrum of the stator voltage and is 3.40% %THD. The third order harmonics are very low and the 5 th order current harmonics are almost 4% with reference to the fundamental.
16 Experimental Results Figure 6.13 shows the experimented results of stator voltage and the harmonic spectrum before passing through the LC filter. From Figure 6.13a, it is observed that the voltage profile is matching towards sinusoidal profile. The harmonic spectrum presented in Figure 6.13.b shows that the lower order voltage harmonics are reduced much and the THD is observed as 24.98%. The higher order harmonics still exists in smaller level which contributes rise of THD value. These higher order harmonics can be reduced by passing this voltage profile through the LC low pass filter V msec/div (a) Waveform V Vrms, %THD (b) Figure 6.13 (a) Experimented three phase inverter output voltage before LC filter (b) Voltage Harmonics spectrum for stator voltage
17 113 The stator voltage after the LC filter section is presented in Figure 6.14a, and the harmonic spectrum is presented in Figure 6.14b. It is observed that the harmonic components are very much reduced. The THD is 5.86% which very closely matching with the IEEE STD 519 value of 5% V (a) Waveform V Vrms, 5.86 %THD (b) Figure 6.14 a) Experimented three phase stator voltage to the BLDCM b) Harmonics spectrum for stator voltage
18 114 The Stator current and the corresponding harmonic spectrum of the motor running at steady no load is presented in Figure It is observed that the current profile is well matched with the sinusoidal profile. The harmonic spectrum of stator current is presented in Figure 6.15b. The harmonics are observed as 13.1%. The 5th order current harmonics is 11.1%, but the higher order harmonics are greatly reduced. The consolidated voltage and current harmonics for both simulation and experimentation are presented in Figure 6.16a and Figure 6.16b A (a) Waveform I Arms, %THD (b) Figure 6.15 (a) Experimented three phase stator current (b) Harmonic spectrum for stator current
19 %THD (I) Simulated %THD (I) Experimented Two level inverter Three level inverter with filter %THD (V) Simulated (a) %THD (V) Experimented Two level inverter Three level inverter with filter (b) Figure 6.16 Harmonics comparison a) current harmonics b) harmonics voltage The consolidated torque ripple analysis of the previous methodologies and for the three level inverter based commutations system are presented in Figure It is observed that the torque ripple is considerably reduced with reference to the previous methodologies of two level inverter based drive system, the passive filter and the dynamic PWM methods. The torque ripple linearly varies for the increase of load. It is observed that this methodology may be suitable for BLDC motor with high voltage, high speed and light load applications.
20 116 Ripple Torque (Nm) Two level inverter Two level inverter with filter Two level inverter with dynamic PWM Two level inverter with SAF Three level inverter with filter Load (kg) Figure 6.17 Torque Ripple analysis 6.7 CONCLUSION This chapter describes a combined diode clamped three level inverter which acts as a commutation system cascaded with an LC filter for a Brushless DC motor for minimizing the harmonics present in the stator voltage and current. The entire system is simulated using MATLAB/Simulink and it is observed that there is a considerable reduction in harmonics. The real time experimentation is carried out with an FPGA controller for investigating the effectiveness of the system. The voltage harmonics are considerably reduced and the current harmonics are marginally reduced. The torque ripple for this motor drive is also reduced. The next chapter presents the consolidated experimental outcome of various methodologies applied on the BLDC motor drive system for reducing the harmonics and torque ripple.
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