DIGITAL-TO-ANALOG CONVERTER ICs

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YOUR SEMICONDUCTOR SOLUTIONS RESOURCE Volume 10, Issue 1 DIGITAL-TO-ANALOG CONVERTER ICs Contents Current Output DACs Provide Unmatched Combination of Speed and Accuracy.

1 YOUR SEMICONDUCTOR SOLUTIONS RESOURCE Volume 10, Issue 1 DIGITAL-TO-ANALOG CONVERTER ICs Contents Current Output DACs Provide Unmatched Combination of Speed and Accuracy.. 1 Precision DACs Offer Up to 60 V Output Range ADI Provides High Quality Clocking Signals for High Speed DAC Applications DDS-Based QDUC Modulator IC Eliminates Imbalance Errors Improve Power Efficiency in Noise Sensitive, High Speed Data Converter Applications Tested Circuits from the Lab Design Resource Precision 16-Bit DAC Significantly Improves Quality of Test and Measurement Equipment Transmit DAC with Expanded Processing Functionality Eases Digital Interface Task Digital Variable Resistors Save Space in Tiny 3 mm 3 mm LFCSP (SON) Package When Time Domain Performance Is Critical, Current Output DACs Provide an Unmatched Combination of Speed, Accuracy, Low Power, and Integration In arbitrary waveform generation, instrumentation, and medical applications where positioning an analog signal to an exact value within the shortest interval is critical, the demand is for integrating more channels and functionality in the same board space. To achieve this higher level of integration and smaller package sizes, high speed current output DACs are tasked with not only delivering high accuracy and fast settling time specifications but also providing more functionality on lower power consumption. To achieve fast digital-to-analog conversion, current output DACs are the solution of choice for mixed-signal board designers. This DAC architecture minimizes the output resistance, allowing faster settling time. Led by communications requirements, current DACs have achieved the required high update rates without compromising static accuracy. The AD9726 is a true 16-bit accurate current output DAC with a maximum update rate of 400 MSPS, combining a single or double data rate LVDS data interface with a factory calibrated 20 ma differential current output for improved INL and DNL performance. The AD9726 operates from 2.5 V and 3.3 V power supplies. AD9726 DAC Output Rise TIme 10.0% 90.0% Rise Time = 484.6ps VERTICAL = 40mV/DIV HORIZONTAL = 2.0ns/DIV R L = 25Ω The dual AD9117 features two 14-bit accurate current output DACs operating up to 125 MSPS update rate, integrating a double data rate CMOS digital interface with internally calibrated 20 ma differential current outputs. The AD9117 can operate with supplies between 1.8 V and 3.3 V. Visit our new website for data sheets, samples, and additional resources. Part Number Resolution (Bits) Maximum Update Rate (MSPS) Power Consumption (mw) Settling Time (ns) Rise/ Fall Time (ps) AD AD Package Price ($U.S.) 80-lead, 14 mm 14 mm lead, 6 mm 6 mm

2 Precision DACs Offer Up to 60 V Output Range Designers of high voltage systems typically utilize low voltage DACs coupled with a discrete amplifier solution to attain the high voltage output drive capability required in applications such as high voltage test equipment, programmable voltage/current sources, precision HV biasing, and receiver bias in optical communications. This approach involves multiple elements: time spent for layout and interface considerations, additional component count, added costs, and increased power consumption. ADI s newest family of high voltage DACs addresses these concerns with the introduction of the AD5501 (single) and AD5504 (quad) devices, which integrate a 12-bit DAC, an on-chip high voltage output amplifier, and a precision reference. In addition, a temperature sensor with alarm function and power saving features are also incorporated on chip. The AD5501/ AD5504 provide a pin-selectable 0 V to 30 V or 0 V to 60 V output range, and the on-chip output amplifiers allow an output swing within the range of AGND of +0.5 V and V DD of 0.5 V. The low power, high speed serial interface with readback capability can handle clock speeds up to 30 MHz. The AD5501/AD5504 operate over a wide temperature range of 40 C to +105 C and are available in a 16-lead TSSOP package. SYNC SCLK SDI SDO ALARM VLOGIC POWER-ON RESET DAC REGISTER INPUT CONTROL LOGIC PRECISION REFERENCE kΩ REF (+) 12-BIT DAC TEMPERATURE SENSOR OUTPUT BUFFER POWER-DOWN CONTROL LOGIC 1713kΩ V DD AD5501 RESISTOR NETWORK VFB V OUT AD550x Features Resolution: 12-bits Output range: 30 V, 40 V, or 60 V Integrated precision reference SPI interface with readback Applications HV test equipment Programmable voltage and current sources Precision HV biasing CLR R_SEL DGND AGND Receiver bias in optical communications Avalanche photodiodes Piezoelectric cells Transducer, servo, HV LED drivers HV regulators Part Number Number of Channels Resolution (Bits) INL (LSB) Max Outputs (V) Temperature Range ( C) Package AD , to lead TSSOP 4.58 AD , to lead TSSOP 8.12 Price ($U.S.) Understanding Sampled Data Systems at Circuit Design Shortcut Complementary components for AD5501/AD5504 high voltage output DACs: ADSP-BF531 DSP ADCLK846 clock buffer for low clock jitter 2 For data sheets, samples, and additional resources, visit

3 ADI Provides High Quality Clocking Signals for High Speed DAC Applications The clock signals provided to high speed, high performance DACs are often one of the primary limiting factors for the performance achieved by that DAC. In order to achieve their rated performance specifications, high speed data converters require a fast rising, low jitter sampling clock. In large complex systems where there are many digital chips requiring clock signals as a reference, it can be a significant challenge to maintain a good low noise/low jitter clock signal throughout the entirety of the clock tree. Functional Block Diagram ADCLK954 LVPECL Q0 Q0 Q1 Analog Devices has developed a broad portfolio of clock buffers that have been designed to help designers solve this clock integrity challenge. With a clock buffer inserted between the converter and the system clock tree, jitter figures on the order of 75 fs for LVPECL fanout buffers and extremely low skew on the order of 9 ps (picoseconds) can be obtained. These buffer ICs also provide up to 12 channels of low jitter clock fanout. The ideal clock signal for a data converter features not only low phase noise/jitter but also very sharp rise and fall edges. As clocking speeds continue to increase, the challenge to achieve a high quality square wave clock signal grows along with that speed. When a very sharp edge for just one or two DACs is needed, the ADCLK905, ADCLK907, ADCLK914, and ADCLK925 clock buffers can provide very fast edges with extremely little impact on the noise of the clock signal when located in close proximity to the converter. Per the table below, ADI has a portfolio of low jitter clock buffer products ranging from one to 24 outputs and various logic families. V REF 0 V T 0 CLK0 CLK0 V T 1 CLK1 CLK1 IN_SEL V REF 1 REFERENCE REFERENCE Q1 Q2 Q2 Q3 Q3 Q4 Q4 Q5 Q5 Q6 Q6 Q7 Q7 Q8 Q8 Q9 Q9 Circuit Design Shortcut Q10 Complementary components for clock buffers: AD9549 clock generator for system clock AD bit, 2.4 GSPS transmit DAC AD9268 dual channel, 16-bit, 125 MSPS Rx ADC Q10 Q11 Q11 Part Number Number of References Number of Outputs Maximum Output (MHz) Jitter (ps) Price ($U.S.) ADCLK ECL ADCLK ECL ADCLK ECL ADCLK HVDS ADCLK LVDS/12 CMOS 1200/ ADCLK LVDS/24 CMOS 1200/ ADCLK LVPECL ADCLK LVPECL ADCLK LVPECL ADCLK LVPECL For data sheets, samples, and additional resources, visit 3

4 2.4 GSPS, DDS-Based QDUC Modulator IC Eliminates Imbalance Errors Common to Dual DAC Transmit Paths in Wireless Transmit Infrastructure Applications Dual DAC direct-conversion schemes are a common approach to upconversion in base station and point-to-point microwave transmit signal chains. However, this approach can introduce quadrature phase and amplitude imbalance issues into the signal chain as a result of mismatching in the separate I and Q DAC functions. DDS-based quadrature modulators are an effective solution in these architectures because they utilize a single DAC function and inherently avoid the imbalance problems noted above. ADI s AD9789 quadrature digital upconverter (QDUC) integrates a high speed 2.4 GSPS DDS core, a high performance 14-bit DAC, digital filters, and other DSP functions onto a single chip. IF/RF DC TO 2.8GHz ADDITIONAL RF UPCONVERSION/ PROCESSING While this device contains additional DSP processing to support four DOCSIS channels for CMTS applications, it also features a single-carrier, wideband mode of operation that Applications supports signal reconstruction bandwidths up to 100 MHz (1 db 2.4 GSPS). Due to the CMTS/DVB AD9789 s single DAC QDUC architecture, the anomalies such as I/Q phase and amplitude imbalance issues are avoided. Broadband communications systems AD9789 QDUC Application in Transmit Path The AD9789 also features a patented mix-mode super-nyquist function that allows signal reconstruction in the second and third Nyquist zone, hence enabling IF/RF frequencies up to 2.8 GHz when clocked at 2.4 GSPS. The AD9789 supports either a 16-bit I/Q interleaved LVDS or dual port CMOS data interface with its digital interpolation filters configurable for 16 to 512 interpolation. The QAM encoder supports constellation sizes of 16, 32, 64, 128, and 256 with SRRC filter coefficients for all standards. Power consumption of GSPS is achievable with only 16 interpolation. The device is available in a 164-ball CSP-BGA package. The DDS-based modulation approach provides excellent dynamic performance and modulation accuracy while reducing cost, power, and board space all important considerations in wireless communication systems. RFDAC ADF4350 PLL/VCO F CLK = 2.4GHz (MAX) INTERPOLATION/ TUNABLE BPF CLOCK DIVIDER/ DISTRIBUTION AD9789 QDUC 16 Cellular infrastructure Point-to-point wireless 1 TO 2 FRAC RESAMPLER 2N INTERPOLATION 1 TO 32 I Q F DATA = 150MHz (MAX) I/Q 16-BIT INTERFACE Pricing FPGA AD9789 $53.10 AD9789 Features Excellent IF/RF dynamic range Two-tone IMD: MHz; MHz NSD: MHz (P OUT = 15.5 dbm) NSD: MHz (P OUT = 18.5 dbm) 1st adj. single-carrier W-CDMA 2.1 GHz: 68 dbc 2nd adj. single-carrier W-CDMA 2.1 GHz: 70.4 dbc 3rd adj. single-carrier W-CDMA 2.1 GHz: 72.7 dbc On-chip and bypassable: 4 QAM encoders with SRRC filters, 16 to 512 interpolation, rate converters and modulators Flexible data interface: 4-, 8-, 16-, or 32-bits wide with parity Direct-to-RF synthesis support with f S mix-mode Built-in, self test (BIST) supports input connectivity check, internal random data generator Understanding Sampled Data Systems at Circuit Design Shortcut Complementary components for AD9789 QDUCs: AD9549 clock generator for system clock ADCLK914 high speed clock buffer for jitter reduction and fanout 4 For data sheets, samples, and additional resources, visit

5 Improve Power Efficiency in Noise Sensitive, High Speed Data Converter Applications by Using Switching Power Supplies Linear LDOs do provide great noise performance for sensitive high speed converter designs, but power efficiency suffers as much as 70% of the total power efficiency in a multiconverter system can be lost in the supply section. Switching dc-to-dc converters achieve high efficiencies but previously weren t adequate because they typically exhibited high noise levels, which translated to ADC spurs and SNR degradation. ADI s new generation of lower noise dc-to-dc converters, such as the ADP2114 dual output switching power supply, have forever changed the picture. In the application study below, using the AD9268, 16-bit, 125 MSPS ADC, the ADP2114 provides the power for the converter s 1.8 V AVDD and DRVDD rails. As can be seen in the chart, changing to this switching supply increases the application s overall efficiency from 50% with the LDO, up to 85% with the switching supply. There was practically no degradation in ac performance between the two power sources. In this single converter case, the 35% improvement in efficiency results in a power savings of 640 mw. Whether in a high speed DAC or ADC application, this dramatic power savings translates into a greener system with many related cost savings. AD9268 ADC Case Study (FS = 125 MSPS) Linear Voltage Regulator Supplies ADP2114 Switching Voltage Regulator Supplies Input voltage/current 3.6 V/0.433 ma ( W) 3.6 V/0.255 ma (0.918 W) Output voltage/current 1.8 V/0.433 ma ( W) 1.8 V/0.433 ma ( W) Overall efficiency 50% 85% AC performance with 70 MHz A IN SNR = 78.5/SFDR (dbc) = 91.0 SNR = 78.4/SFDR (dbc) = 90.8 Designing with Switching Regulators in High Speed ADC Applications at Tested Circuits from the Lab Design Resource Provides Faster Time to Market and Lowers Risks Analog Devices Circuits from the Lab is a new design assistance resource that provides design engineers with tested circuit solutions for many common applications. Each circuit has been built and tested in the lab and can be easily integrated into designs, resulting in reduced design risk and faster time to market. Featured Circuits from the Lab CN-0021 Circuit Note, Interfacing the ADL5375 I/Q Modulator to the AD9779A Dual Channel, 1 GSPS High Speed DAC The ADL5375 and the AD9779A are well matched devices because they have the same bias levels and similarly high signal-to-noise ratios (SNR). The matched bias levels of 500 mv allow for a glueless interface there is no requirement for a level shifting network that would add noise and insertion loss along with extra components. Access this complete circuit note at CN-0009 Circuit Note, 4 ma to 20 ma Process Control Loop Using the AD5662 DAC This circuit provides a low power current transmitter with 16-bit resolution and monotonicity, which is powered directly from the 4 ma to 20 ma control loop power supply and consumes less than 4 ma. Access this complete circuit note at For data sheets, samples, and additional resources, visit 5

6 New Precision 16-Bit DAC Significantly Improves Quality and Repeatability of Sensitive Test and Measurement Equipment In a host of ATE and high end instrumentation applications, product developers and system architects require solutions to the growing demand for precise and repeatable electrical test and materials characterization systems, while simultaneously reducing system test costs. Analog Devices, leveraging its leadership position in data converter technology, delivers the AD5541A family of single channel high performance DACs. These products provide the fundamental building block required in precision source applications by delivering full 16-bit resolution and accuracy, low noise performance (10 nv/ Hz), low drift (0.05 ppm/ C), and low glitch impulse (0.5 nv/sec) coupled with fast DAC refresh rates (1 μs). Enabled by ADI s proprietary icmos industrial manufacturing process technology, the AD5541A family operates from single supply voltages of 2.7 V to 5.5 V. The output can be configured for a unipolar or bipolar range using the integrated internal feedback resistor and can be asynchronously set to zero-/midscale using the CLEAR pin during power-up/down or system fault conditions. A VLOGIC pin provides increased interface flexibility and allows connections to 1.8 V to 5.5 V logic interfaces, as well as an LDAC pin, which allows synchronous DAC update in multichannel systems. The flexible serial interface is SPI-, QSPI-, and MICROWIRE-compatible. V DD 10 The AD5512A is a pin-compatible, 12-bit device. R FB AD5542A-1 All devices in the AD5541A family are specified over the R INV extended industrial temperature range 40 C to +125 C. Devices are housed in 3 mm 3 mm LFCSP, MSOP, and 8 7 R FB V 1 16-BIT DAC 6 TSSOP packaging. REF V OUT AD5541A Features 16-bit resolution and accuracy Low noise: 10 nv/ Hz Low glitch: 0.5 nv/sec Low drift: 0.05 ppm/ C Configuration: bipolar or unipolar Functionality: CLEAR and LDAC Compatibility: 1.8 V logic Packaging: TSSOP, MSOP, and 3 mm 3 mm LFCSP CS CLR SCLK DIN Applications Automatic test equipment Precision source-measure instruments CONTROL LOGIC 16-BIT DAC LATCH SERIAL INPUT REGISTER 9 GND Data acquisition systems Medical/aerospace instrumentation Communication equipment Industrial control Part Number Configuration Resolution/ Price Package Accuracy ($U.S.) AD5541A LDAC, VLOGIC functionality 16-bit, 1 LSB 10-lead MSOP, 10-lead LFCSP 6.25 AD5541A-1 CLEAR functionality 16-bit, 1 LSB 8-lead LFCSP 7.95 AD5542A CLEAR, LDAC, RFB, VLOGIC functionality 16-bit, 1 LSB 16-lead TSSOP, 16-lead LFCSP 6.25 AD5542A-1 CLEAR, RFB functionality 16-bit, 1 LSB 10-lead LFCSP 7.95 AD5512A CLEAR, LDAC, RFB, VLOGIC functionality 12-bit, 1 LSB 16-lead LFCSP 2.85 Differential Circuit Design Techniques for Communications Applications at 6 For data sheets, samples, and additional resources, visit

Transmit DAC with Expanded Processing Functionality Eases Digital Interface Task The quest for higher transmit channel densities in multistandard, multicarrier communications systems is increasing

7 Transmit DAC with Expanded Processing Functionality Eases Digital Interface Task The quest for higher transmit channel densities in multistandard, multicarrier communications systems is increasing the required interface width between the digital and analog portions of these designs. The increasing data interface width is in turn driving up the pin counts of the FPGAs sourcing data to the mixed-signal components of these cards. Besides increasing the cost and power consumption of the FPGAs, the sheer number of interconnects makes the layout of the PCBs increasingly complex and the desired densities harder to achieve in the increasingly smaller system form factors. The AD9122 dual, 16-bit, 1200 MSPS TxDAC+ digital-to-analog converter (DAC) with on-chip 32-bit NCO addresses the problem of increasing interface width by offering a rich set of signal processing functions and a flexible digital interface. The AD9122 supports 2, 4, 8 interpolation and 32-bit resolution digital upconversion. This allows the digital source to provide the synthesized signal at the lowest possible data rate without carrying the extra speed burden that these functions entail. The flexible digital interface gives designers the option of trading interface width for interface speed. The AD9122 supports bus interface speeds up to 1200 Mbps. The interface width can be configured for word, byte, or nibble mode. The pin width and interface speeds are shown in the table below. Reliably transmitting data over an LVDS data bus at 1200 MSPS presents a design challenge as well. In order to ease this design task, the AD9122 provides on-chip sample error detection (SED) circuitry. This circuitry helps designers characterize and optimize their interface timing margins, ensuring robust operation of the interface. Pricing AD9122 $34.95 AD9122 Interface Widths and Speeds Interface Width Nibble (4 bits) Byte (8 bits) Word (16 bits) Interpolation Factor 1 Pins Required f BUS (Mbps) f DAC (MSPS) Complex Bandwidth (MHz) Circuit Design Shortcut Complementary components for AD9122 transmit DAC: AD9516 clock generator for system clock ADCLK914 clock buffer for jitter reduction and fanout ADL5375/ADRF6702 quadrature modulators ADRF6602 Rx mixer For data sheets, samples, and additional resources, visit 7

600 North Bedford Street East Bridgewater, MA 02333-1122 Highest Accuracy 3 V to 5 V Digital Variable Resistors Save Space in Tiny 3 mm 3 mm LFCSP (SON) Package The AD5270/AD5271/AD5272/AD5274

8 600 North Bedford Street East Bridgewater, MA Highest Accuracy 3 V to 5 V Digital Variable Resistors Save Space in Tiny 3 mm 3 mm LFCSP (SON) Package The AD5270/AD5271/AD5272/AD5274 members of ADI s digi POT+ family of digital variable resistors are single channel, 1024-/256-position digitally controlled resistors with less than 1% end-to-end resistor tolerance error and 50 programmable memory. The devices perform the same electronic adjustment function as a mechanical rheostat with enhanced resolution, solid state reliability, and superior low temperature coefficient performance. These devices are well suited for high precision applications across industrial, communications, and consumer markets. These digipot ICs are available in thin 3 mm 3 mm LFCSP (SON) and compact 10-lead MSOP packages. The parts are guaranteed to operate over the extended industrial temperature range of 40 C to +105 C. Applications Instrumentation: gain, offset adjustment Programmable voltage to current conversion Programmable power supply Sensor calibration Pricing AD5270/ AD5272 $1.59 AD5271/ AD5274 $0.95 Understanding and Applying Digital Potentiometers at Worldwide Headquarters One Technology Way P.O. Box 9106 Norwood, MA U.S.A. Tel: ( , U.S.A. only) Fax: Europe Headquarters Wilhelm-Wagenfeld-Str Munich Germany Tel: Fax: Japan Headquarters Analog Devices, KK New Pier Takeshiba South Tower Building Kaigan, Minato-ku, Tokyo, Japan Tel: Fax: Southeast Asia Headquarters Analog Devices 22/F One Corporate Avenue 222 Hu Bin Road Shanghai, China Tel: Fax: All prices in this bulletin are in USD in quantities greater than 1000 (unless otherwise noted), recommended lowest grade resale, FOB U.S.A. I 2 C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors) All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Inventory Code: DAC-V10-IS1-09 Printed in the U.S.A. SB /09

Multiplying DACs. Flexible Building Blocks.

Multiplying DACs. Flexible Building Blocks. Multiplying DACs Flexible Building Blocks Analog Devices has a comprehensive family of 8-/10-/12-/14-/16-bit multiplying digital-to-analog converters. As a result of manufacture on a CMOS submicron process,