A Comparison of 25 Gbps NRZ & PAM-4 Modulation Used in Legacy & Premium Backplane Channels

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1 Adam Healey, LSI Corporation Chad Morgan, TE Connectivity Abstract Standards bodies are now examining how to increase the throughput of high-density backplane links to 25 Gbps. One method for achieving this is to construct premium backplane links utilizing advanced materials and connectors. Another approach is to re-use legacy backplanes by employing PAM- 4 signaling at half of the baud rate. For PAM-4 to offer an advantage over NRZ, the signal-to-noise ratio (SNR) at the slicer input, i.e. after equalization, must be ~9.5 db better than NRZ to overcome loss of separation between signal levels. This paper will examine 25 Gbaud NRZ and 12.5 Gbaud PAM-4 signaling across varying levels of channel insertion loss and crosstalk. Chip parameters such as rise-time and jitter will also be varied. The paper provides a reference for engineers to use when considering when it is appropriate to use NRZ signaling at 25 Gbaud and when it is appropriate to use PAM-4 signaling at 12.5 Gbaud for successful high-density backplane operation. Author Biographies for Ethernet operation over electrical backplanes at speeds of 1 and 10 Gbps and currently secretary of the IEEE Ethernet Working Group. Adam has also previously served a technical committee chairman and Vice President of Technology for the Ethernet Alliance. Adam received B.S. [ 95] and M.S. [ 00] degrees in Electrical Engineering from the University of New Hampshire. Chad Morgan earned his degree in Electrical Engineering from the Pennsylvania State University, University Park, in For the past 16 years, he has worked in the Circuits & Design group of TE Connectivity as a signal integrity engineer, specializing in the analysis & design of highspeed, high-density components. Currently, he is a Principal Engineer at TE Connectivity, where he focuses on highfrequency measurement & characterization of components & materials, full-wave electromagnetic modeling of high-speed interconnects, and the simulation of digital systems. Mr. Morgan is a Distinguished Innovator with numerous patents at TE Connectivity, and he has presented multiple papers at trade shows such as DesignCon and the International Microwave Symposium. Adam Healey is a Distinguished Engineer at LSI Corporation where he supports the development and standardization of high speed serial interface products. Prior to joining Lucent Microelectronics in 2000, Adam worked for University of New Hampshire s InterOperability Lab where he developed many of the test procedures and systems used to verify interoperability, performance, and compliance to standards of 10, 100, and 1000 Mb/s Ethernet products. During his tenure at Lucent Microelectronics, which later became Agere Systems and then LSI Corporation, Adam was involved in wide variety of projects including channel modeling and equalization strategies for high speed optical and electrical links, transcoding and error correction coding subsystems, and transport networking architecture. Adam is a member of the IEEE and regular contributor to the development of industry standards through his work in the IEEE Ethernet working group and INCITS T11.2 Fibre Channel Physical Variants task group. Adam was chairman of the IEEE P802.3ap Task Force chartered to develop the standard Introduction The growing demand for instant multimedia access in an ever-increasing number of digital devices has continued to push the need for higher aggregate bandwidth in modern communication hardware. As a result, standards bodies are now examining how to increase high-density backplane serial throughput to 25 Gbps per differential pair. As an example, the Optical Interconnect Forum (OIF) now has Implementation Agreements defining the criteria for designing both short- and long-reach 25 Gbps channels [1]. Further, The IEEE Ethernet Working Group has begun discussions on a 100 Gigabit Backplane Ethernet standard that would consist of 4 lanes, each transporting 25 Gbps of data. Currently, there is much debate within standards bodies on how to achieve acceptable 25 Gbps data transmission across

2 high-density backplane channels of up to 1 meter. One possible method for achieving this is to construct high-quality backplane links utilizing low-loss dielectrics, smooth copper, and low-reflection, low-crosstalk connectors. These channels still require high-levels of equalization and are more expensive than legacy backplane systems built for 10 Gbps operation. Another method that has been suggested is to use PAM- 4 signaling at half of the baud rate to achieve 25 Gbps transmission across legacy backplanes. The hope is that successful 12.5 Gbaud PAM-4 operation would allow the use of cheaper legacy backplane channels. The possible move to PAM-4 signaling, however, comes with numerous factors to consider. Engineers attempting to implement PAM-4 would need to use updated simulation algorithms, new test equipment, newly defined test protocols, and highercomplexity equalization. achieved by studying multiple lengths (1.0 m & 0.75 m), dielectrics (Improved FR4 as defined by the IEEE P802.3ap Task Force [2] & Megtron6), and TE Connectivity Z-PACK TinMan and STRADA Whisper connector systems.. Various crosstalk levels are achieved by studying multiple connectors (TE Connectivity Z-PACK TinMan & STRADA Whisper connectors) and multiple pinouts for each connector. These pinouts include the manufacturer-recommended pinout, full near-end crosstalk (NEXT), and full far-end crosstalk (FEXT). Proven time-domain simulation methods will be used to complete 25 Gbaud NRZ vs Gbaud PAM-4 comparisons. Once package and chip parasitics are added to the multiple channel models, simulations will be completed for a given driver rise time, jitter level, and equalization scheme. When all baseline simulations are complete, results will then be augmented to show the effects of varying rise time and jitter. Before considering PAM-4, the first step is to clearly outline where PAM-4 signaling at 12.5 Gbaud has performance advantages over NRZ signaling at 25 Gbaud. This paper will accomplish this by providing NRZ vs. PAM-4 electrical performance data across a range of different backplane performance levels. Ultimately, the goal of the paper is to provide a detailed and reliable reference for engineers to use when considering the appropriate use of 25 Gbaud NRZ signaling and when it is appropriate to use 12.5 Gbaud PAM-4 signaling for successful high-density backplane operation. Backplane performance levels can essentially be categorized by their insertion loss-to-crosstalk (ICR) ratio. Therefore, a range of channel insertion loss and crosstalk levels are included in the paper. Various insertion loss levels are Description of Figure 1 shows all parameters for the eight backplane channels that are studied in this paper. As shown, overall Figure 1: Simulated 1.0 m & 0.75 m Backplane Using Improved FR4 or Megtron6 Dielectrics and ZPACK TinMan or STRADA Whisper Connectors from TE Connectivity. 2

3 channel lengths of ~1 m and ~0.75m are implemented by concatenating daughtercard lengths of m (5.0 ) with backplane lengths of either m (17.0 ) or m (3 ). In order to study legacy channels that were designed for 10 Gbps, some channel permutations are implemented in improved FR4 and with Z-PACK TinMan connectors from TE Connectivity. In order to study high-performance channels, other channel permutations are implemented in Panasonic Megtron6 with H-VLP smooth copper and STRADA Whisper connectors from TE Connectivity. All other parameters shown in Figure 1 are typical of modern backplane channels, such as counterbored vias with mm (10 ) remaining stubs. For each of the eight channel permutations, multiple crosstalk patterns are studied. For example, crosstalk effects are examined when the manufacturer-recommended connector pinout is implemented, as shown in Figures 2 and 3 for STRADA Whisper and Z-PACK TinMan connectors from TE Connectivity. Crosstalk effects are also studied when all eight nearby aggressors are producing near-end crosstalk (all- NEXT) or when all eight nearby aggressors are producing far-end crosstalk (all-fext). Generally, crosstalk effects are more prevalent when utilizing PAM-4 modulation, since full-swing aggressors can produce high-magnitude crosstalk on 1/3-swing bits. For this reason, it is important to study crosstalk carefully under multiple conditions. Figure 3: Z-PACK TinMan connector & footprint showing crosstalk configurations. All channel performance data for the four ~1.0 m channels is shown in Figure 4, and all channel performance data for the four ~0.75 m channels is shown in Figure 5 (following two pages). For insertion loss (IL), return loss (RL), and ICR, limit lines are included from the IEEE specification [3] as a reference. Although insertion loss deviation (ILD) is not shown, all four ~1.0 m channels and all four ~0.75 m channels fall within the ILD bounds specified by IEEE In Figures 4 and 5, note that all eight channels meet the IEEE 10GBASE-KR limits for insertion and return loss. Because these limit lines are only specified to 6 GHz, they are not definitive for successful 25 Gbps operation. However, they do serve as a useful definition for the lowest acceptable performance of a legacy 10 Gbps channel. When examining ICR plots, it is clear that all STRADA Whisper connector channels surpass the fit-icr limit with at least 10 db of margin. The Z-PACK TinMan conector channels, on the other hand, just fail the fit-icr limit when using the recommended pinout. This is intentional, as it was desirable to examine NRZ vs. PAM-4 performance for a 1 m, improved FR4 legacy channel that just violates the 10GBASE-KR fit-icr specification. Figure 2: STRADA Whisper connector & footprint showing crosstalk configurations. Note that the connectors for the eight channels in Figures 4 and 5 were carefully chosen. Z-PACK TinMan connector channel performance is similar to numerous other connectors 3

4 (a) (b) (c) (d) (e) (f) (g) (h) Figure 4: 1 meter Channel Data - (a) Differential Insertion Loss, (b) Differential Return Loss, (c) Recommended Pinout Crosstalk, (d) Recommended Pinout ICR, (e) All NEXT Crosstalk, (f) All NEXT ICR, (g) All FEXT Crosstalk, & (h) All FEXT ICR 4

5 (a) (b) (c) (d) (e) (g) (h) Figure 5: 0.75 meter Channel Data - (a) Differential Insertion Loss, (b) Differential Return Loss, (c) Recommended Pinout Crosstalk, (d) Recommended Pinout ICR, (e) All NEXT Crosstalk, (f) All NEXT ICR, (g) All FEXT Crosstalk, & (h) All FEXT ICR 5

6 in legacy backplane systems (Max RL = -10 db to 5 GHz, Max XTALK = -30 db to 5 GHz). STRADA Whisper channel performance, on the other hand, represents industry best-inclass performance (Max RL = -15 db to 12.5 GHz, Max XTALK = -45 db to 12.5 GHz). A goal of this paper is to study how connector performance impacts time-domain results. addition, the argument of the complementary error function is reduced by a factor of 1/ (L - 1) to account for the reduction in the distance between symbols when the peak amplitude d is held constant. The probability of error for various values of L is shown in Figure 6. As a final point, it is interesting to note that lower-loss dielectrics and shorter systems buy little in the way of improved ICR at 6 GHz. In simulations including NEXT, only about 5 db of improvement is seen in going from 1.0 m to 0.75 m or in going from Improved FR4 to Megtron6. In simulations including FEXT, almost no improvement is seen. Later, the paper will show how this translates to time-domain performance. Probability of error L = 2 L = 3 L = 4 L = 5 L = 6 L = 7 L = 8 Simulation Conditions Probability of Symbol Error Consider a serial link utilizing NRZ modulation where the distance between symbols is 2d and there is additive white Gaussian noise with standard deviation a symbol error is given by Equation 1.. The probability of In Equation 1, the variable Q is also referred to as the signalto-noise ratio (SNR) and it is defined to be. NRZ modulation may also be considered to be 2-level pulse amplitude modulation (PAM-2). The expression for the probability of a symbol error can be generalized to PAM-L, where L is the number of amplitude levels, as shown in Equation 2. Equation SNR, db For increasing L, the SNR required to achieve a target probability for symbol error also increases. Comparing NRZ modulation and PAM-4, one can see that the SNR must be 9.6 db larger for PAM-4 to achieve the same symbol error probability as NRZ. However, since each PAM-L symbol can convey log 2 (L) bits of information, the symbol rate is reduced accordingly. Figure 6: Symbol error probability as a function of SNR It is clear that for PAM-L to have an advantage over PAM-2, the reduction in symbol rate must yield an improvement in SNR that overcomes the increased SNR requirement for the same symbol error ratio. SNR improvement may be realized in a variety of ways and is not limited to the effective reduction in the channel insertion loss. Transmitter Model Equation 2 The factor of (L - 1) is associated with the fact that the inner symbols in the PAM-L constellation are more prone to error. In The transmitter model shown in Figure 7 includes pre-driver and driver stages for independent control of rise and fall times and output return loss. The pre-driver consists of a voltage source v s (t) that drives the low pass filter formed by 6

7 R pd and C pd. The values of R pd and C pd are chosen to set the pre-driver rise and fall times. The filter output voltage v i (t) then controls a voltage source which represents the driver. The driver includes the on-die termination, represented in a simplified form by R pd and C pd, and is connected to a channel that consists of the backplane channel of interest plus the transmitter and receiver device packages, and the receiver on-die termination. the terminated channel is measurably larger than the channel in isolation. Furthermore, additional insertion loss deviation artifacts are visible reflecting the interaction between than channel, device packages, and termination impedances. R pd v i (t) R d Channel v o (t) (a) (b) v s (t) C pd v i (t) C d C t R t Figure 7: High-level view of the transmitter and channel model Figure 9: Example of driver/receiver package and driver capacitance effect on channel performance The device package model is selected to be representative of a large package that might be used for a high channel count device such as a switch. The insertion loss and return loss for the selected model are shown in Figure 8. For simplicity, the same device package model is used for both the transmitter and the receiver. Given the package model, the single-ended on-die termination resistance is set to 50 Ω and the parasitic capacitance is tuned to yield the desired return loss performance. A single-ended on-die termination capacitance of 0.25 pf was found to just touch the transmitter differential output return loss mask defined by the OIF CEI-25G-LR implementation agreement [1]. For simplicity, the same on-die termination is used for both the transmitter and receiver. Figure 9 shows the impact of the choice of package model and on-die termination. It is clear that the insertion loss of Note that voltage source v s (t) incorporates a finite impulse response filter with three symbol-spaced taps that implements de-emphasis. The delay of this filter is one unit interval which implies that there is one pre-cursor tap and one post-cursor tap. The voltage source also incorporates voltage scaling to set the driver output amplitude as well as phase modulation of the clock for the generation of jitter. Both deterministic (sinusoidal) and random jitter components are defined for the transmitter. The transmitter parameters, other than symbol rate and modulation format, are kept constant for the both the PAM-2 and PAM-4 simulation cases. Specifically, the same device packages and on-die termination networks are used, the peak differential output voltage is constant, and the jitter is fixed in absolute time (ps). The premise is that the design techniques that would be employed to realize the PAM-2 solution could also be leveraged by the PAM-4 solution. This is reflected in the near-end eye diagrams shown in Figure 10. Sensitivity to variation in rise-time and jitter will also be studied later in this paper. Receiver Model Figure 8: Package differential insertion loss and return loss for Pkg35mm_ T21mm115ohmLoXtalk_BGALoXtalk.s8p model from PkgModels40GHz.zip 7 Two receiver architectures will be considered in this study. The first architecture reflects a conventional approach which is heavily reliant on analog signal processing.

8 The second architecture features a digital signal processing (DSP) based receiver. The analog front end includes a PGA and CTE as before, and an analog-to-digital converter (ADC) that renders the analog signal at the AFE output into a series of digital words for subsequent post-processing. The DFE is implemented in the digital domain and may be supplemented by other structures that are readily realized in DSP. This approach will be associated with PAM-4 modulation. Both architectures set the transmitter de-emphasis, CTE transfer function, sampling point, and the coefficients of the receiver s equalizer to minimize the mean-squared error (or maximize the SNR) at the decision point. Continuous Time Equalizer Both architectures under consideration utilize a CTE but the design parameters vary as a function of the symbol rate. The variation is due to proper placements of the peaking frequency as well as constraining the bandwidth to avoid integrating excess noise. The template for the continuous time equalizer transfer function is given in Equation 3. Equation 3 The parasitic poles p p are chosen so the insertion loss of the filter is 2 db at the fundamental frequency, i.e. half of the Figure 10: Comparison of eye diagrams from PAM-2 (NRZ) and PAM-4 transmitters. (a) PAM-2 (NRZ) near-end eye (b) PAM-4 near-end eye The first architecture reflects a conventional approach which is heavily reliant on analog signal processing. The analog front end (AFE) for this architecture consists of a programmable gain amplifier (PGA), continuous time equalizer (CTE), and analog circuitry required for the timing recovery and highspeed decision feedback equalizer implementation. Digital circuitry is used where possible, especially in adaptation loops and management functions. This approach will be associated with PAM-2 or NRZ modulation. symbol rate, when the gain value k is zero. The value of p 1 is fixed at 12.9 π Grad/s to foster consistent mid-band gain between the two filters. The set of gain values k is defined so that the peaking increases in 1 db increments up a maximum of 10 db. The resulting transfer functions are illustrated in Figure 11. Electronics noise is modeled as additive white Gaussian noise with power spectral density N 0 /2 referred to the input of the CTE. This means that the CTE will shape this noise according to its k setting. 8

9 15 10 logic level at its output. The method chosen for modeling latch metastability is the simple but conservative overdrive model in which the signal is required to exceed the decision threshold by a certain amount, otherwise, an error occurs. Magnitude, db 5 0 The number of taps for each equalizer as well as the minimum latch overdrive is set according to Table DSP-Based Equalizer Magnitude, db Frequency, GHz Frequency, GHz Recent deployments of 10 Gbps serial links using digital signal processing (DSP) technology have been enabled by enhancements to analog-to-digital converter (ADC) performance and the scaling of CMOS technologies. DSP-based receivers have advantages over their analog counterparts in several areas. Equalizer structures that are challenging to realize in the analog domain have relatively straight-forward digital counterparts. A simple example is the feed-forward equalizer (FFE). While this structure is realizable in the analog domain, the delay line is subject to variation due to process, voltage, and temperature and does not readily scale with data rate. Analog multiplication must be carefully implemented to achieve sufficient linearity and resolution. Finally, the bandwidth limitations and noise accumulation of these cascaded components has an adverse effect on the SNR. All of these elements are trivial operations in the digital domain, and the digital architecture readily scales with speed (within the bounds of the digital clock rate). Figure 11: Comparison of continuous time equalizers for PAM-2 (NRZ) and PAM-4 receivers. (a) PAM-2 (NRZ) continuous time equalizer (b) PAM-4 continuous time equalizer Analog Equalizer Decision feedback equalizers (DFE) with a relatively large number of taps have been successfully implemented with largely analog signal processing techniques [4]. Apart from the challenges of closing the critical timing path, one of the factors that influence the performance of the receiver is latch metastability. Metastability occurs when the input signal is not large enough for the latch to resolve a discernable This simple example highlights essential benefits of the DSP-based architecture. The first is a lower sensitivity to power, voltage, and temperature variation. While this is still a consideration for the ADC, once the signal is rendered as a sequence of digital values, the processing is consistent regardless of the corner case. Not only is the processing more consistent, it is also more predictable. Cycle-accurate models are readily generated that are not reliant on analog models that must account for variation of a number of parameters and at times may not be very precise. Furthermore, correct implementation of the signal processing path may be checked with robust digital verification techniques. Finally, a DSPbased implementation is inherently portable to other process nodes without the need for extensive analog re-work. 9

10 Porting into smaller process geometries holds the promise of a faster digital clock rate, a smaller receiver, lower power, or some combination thereof. However, DSP-based receivers present their own set of challenges. The most obvious challenge is the upper limits on the digital clock frequency for a given technology node. Well known techniques such as parallelism pipelining and parallelism can circumvent these problems in many cases. However, if we consider the feedback structure of the DFE, the iteration bound presents a challenge for high-speed operation that cannot be addressed by pipelining alone. For this particular example, look-ahead techniques [5] can be employed to relax the iteration bound but this particular architecture scales exponentially for an increasing number of DFE taps. For a PAM-4 receiver based on DFE, the need to resolve 4 levels and propagate 2-bit decisions (each symbol represent 2 bits) translates to an implementation that requires twice the complexity of the corresponding NRZ receiver with half as many taps. One approach to the scaling problem is to shift more emphasis to the FFE and limit the number of DFE taps. Other novel architectures could be considered that achieve performance comparable to DFE with superior scaling properties [6]. In addition, a performance limiting factor for the DSP-based receiver is the quantization noise introduced by the ADC. The resolution of the ADC is defined by its effective number of bits (ENOB). This quantity is less than the actual number of bits (ANOB) in the ADC output word, as the ENOB includes the non-idealities in the conversion process. It is also affected by the scale of the input signal relative to the ADC full-scale range. Since the ADC quantization step is relative to the full scale range, signals smaller than the full scale range see effectively more quantization noise while larger signals are clipped introducing non-linearity. It is the responsibility of the PGA and automatic gain control (AGC) loop to balance these trade-offs. Table 1: Default simulation parameters 10

11 For the purpose of this simulation study the DSP-based equalizer is assumed to include both a FFE and a DFE. The PGA is configured so that ADC clips the input signal with a relative frequency no greater than 1E 6. The number of taps for each equalizer as well as the ENOB of the ADC are set according to Table 1. Simulation Parameters That said, SNR margin is readily derived from simulation data and provides a single-value as a figure of merit that may easily be compared across a large number of simulation cases. Since margin is reported, the higher SNR values required to maintain a constant symbol error probability with increasing L is built into the calculation and no longer needs to be explicitly considered. Furthermore, the ability of Forward Error Correction (FEC) to improve the performance of the link may be readily evaluated in terms of SNR. Unless otherwise specified, all simulations are performed with the parameters summarized in Table 1. Note that the a common symbol error ratio target, i.e. probability of symbol error, yields a common bit error ratio target under the assumption that the PAM-4 symbols are generated from a Gray code and that detection errors map the symbol of interest only to adjacent symbols. Simulation Results The results of the simulations are presented in terms of SNR margin which is defined to be the difference between the SNR at the decision point and the SNR required to achieve the target probability of symbol error. In general, SNR margins greater than or equal to zero imply the probability of symbol error is less than the target (good) and SNR margins less than zero imply the probability of symbol error may exceed the target (bad). It should be noted that a negative SNR margin does not assure that the target probability of symbol error was not achieved. The relationship between SNR and error probability, as discussed earlier in this paper, assumes that the noise term represents the standard deviation of an unbounded Gaussian amplitude distribution. In practice, components of the noise term, such as inter-symbol interference (ISI) and crosstalk, are in fact bounded i.e. the likelihood of that component exceeding some maximum amplitude is zero. Since the relationship between SNR and the probability of a symbol error does not take this into account, the SNR margin metric can be viewed as conservative. For the purpose of these simulations, the SNR at the decision point is computed as the square of the mean of the outermost symbol divided by the sum of the variances of the individual error terms (due to ISI, crosstalk, jitter-induced amplitude error, etc.). This quantity is reported in units of decibels. The first set of simulation results investigates the relative impact of each of the link impairments. Referring to Figure 12, 0.75 m and 1 m channels are examined using the PAM-2 and PAM-4 transmitter and receiver reference models. are described by an index where 1 and 2 correspond to the STRADA Whisper connector and 3 and 4 correspond to the Z-PACK TinMan connector. In addition, 1 and 3 represent channels built with Megtron 6 while 2 and 4 represent channels built with materials satisfying the definition of improved FR4 used by the IEEE P802.3ap Backplane Ethernet Task Force. Manufacturer recommended pinouts are used for these channels. The graphs illustrate the cumulative reduction of SNR margin as impairments are added. The ISI only values represent the SNR margin with only residual ISI considered. The +FEXT values are the SNR margin considering residual ISI and all farend crosstalk aggressors. The +NEXT values include residual ISI, far-end crosstalk aggressors, and all near-end crosstalk aggressors. The final set of values, labeled ENOB represent the SNR margin with all impairments considered. Note that, for the PAM-2 cases, there is no ADC in the receiver reference model and therefore the SNR degradation due to quantization error is zero. 11

12 ISI only FEXT NEXT AWGN UJ ENOB ISI only FEXT NEXT AWGN UJ ENOB ISI only FEXT NEXT AWGN UJ ENOB ISI only FEXT NEXT AWGN UJ ENOB Figure 12: SNR margin reduction as a function of various impairments. Channel index [1, 2] = STRADA Whisper, [3, 4] = ZPACK TinMan, [1, 3] = Megtron 6, [2, 4] = Improved FR4. Recommended pinouts. (a) PAM-2, 0.75 m channels (b) PAM-4, 0.75 m channels (c) PAM-2, 1 m channels (d) PAM-4, 1 m channels The comparison of the total SNR margin for the PAM-2 and PAM-4 reference models is given in Figure 13. From these results, it is evident that positive SNR margin is achieved for the STRADA Whisper connector channels while there is significant negative margin for the Z-PACK TinMan connector channels. Referring the Figure 12, the PAM-2 reference model operating over the Z-PACK TinMan connector channels shows negative SNR margin even for the ISI only indicating that there is significant residual ISI in these cases. The PAM- 4 reference model yields small positive margins in the ISI only case with the exception of the 1 m Z-PACK TinMan connector channel. Reflecting on the transfer functions for the Z-PACK TinMan connector channels shown in Figures 4 and 5, significant insertion loss deviation is evident and the residual ISI may be a consequence of reflected energy that is out of the reach of the DFE. In addition, higher crosstalk levels in the Z-PACK TinMan connector channels are the next largest contributor to margin degradation. Next, the sensitivity of SNR margin to variations in link parameters is explored. First, crosstalk is manipulated by specifying pinouts that differ from the manufacturer s recommendations. Two such cases are considered. The first is the All FEXT case where the victim receiver is surrounded by other receivers (co-propagating or far-end aggressors). The second is that All NEXT case where the victim receiver is surrounded by transmitters (counter-propagating or nearend aggressors). The SNR margin for these cases is compared to the values obtained for the manufacturer recommended pinouts. These results are summarized in Figure 14. In Figure 14, the largest variation with pinout appears for the Z-PACK TinMan connector channels for which the SNR margin was negative even for the recommended pinout. For the STRADA Whisper connector channels, the variation is considerably smaller, and this reflects that fact that for these low-noise channels, crosstalk is not a dominant impairment 12

13 PAM PAM Channel index PAM PAM Channel index Figure 13: Comparison of PAM-2 (NRZ) and PAM-4 SNR margin. Channel index [1, 2] = STRADA Whisper connector, [3, 4] = Z-PACK TinMan connector, [1, 3] = Megtron 6, [2, 4] = Improved FR4. Recommended pinouts. (a) 0.75 m channels (b) 1 m channels FEXT/NEXT All FEXT All NEXT Channel index FEXT/NEXT All FEXT All NEXT Channel index FEXT/NEXT All FEXT All NEXT Channel index FEXT/NEXT All FEXT All NEXT Channel index Figure 14: Comparison SNR margin for various crosstalk configurations. Channel index [1, 2] = STRADA Whisper connector, [3, 4] = Z-PACK TinMan connector, [1, 3] = Megtron 6, [2, 4] = Improved FR4. NEXT/FEXT corresponds recommended pinouts. (a) PAM-2, 0.75 m channels (b) PAM-4, 0.75 m channels (c) PAM-2, 1 m channels (d) PAM-4, 1 m channels The scope of the analysis is then narrowed to the two 1 m STRADA Whisper connector channels where transmitter and receiver parameters are varied to investigate their impact on SNR margin. The first parameter considered is the transmitter output rise-time. As reported in Table 1, the default value for this parameter is approximately 18.6 ps (20 to 80%) as measured at the package pin. The pre-driver rise-time is varied in order to manipulate the rise-time observed at the 13 Other 2011 logos, Tyco Electronics product and/or Corporation. company All names Rights Reserved. might be trademarks TE Connectivity, of their TE respective connectivity owners. (logo) and TE (logo) are trademarks. Other products, logos and company names mentioned herein may be trademarks of their respective owners.

14 pin without changing other aspects of the transmitter such as return loss performance. Three additional values, again referenced to the package pin, are considered: 16.4, 20.8, and 24.3 ps. The results are summarized in Figure 15. The results indicate that the solution based on PAM-4 modulation is relatively insensitive to increases of rise-time on this order while the PAM-2 solution loses 0.7 to 0.9 db of SNR margin. This may be explained by the fact the unit interval for the PAM-4 solution is twice that of the PAM-2 solution. In addition to this, the penalty resulting from increasing rise-time is muted by the equalizer which attempts to compensate for the apparent reduction in bandwidth Transmitter output rise time (20 to 80%), ps PAM-2, Megtron 6 PAM-2, "Imp. FR4" PAM-4, Megtron 6 PAM-4, "Imp. FR4" Figure 15: Degradation in SNR margin due to increasing rise and fall times for 1 m STRADA Whisper connector channels (manufacturer recommended pinouts). that the margin for the PAM-4 solution is decreasing at an accelerated rate. This seems to agree with the conventional wisdom that PAM-4 has reduced jitter tolerance due to the additional data dependent jitter caused by the unconstrained transitions between levels (refer to Figure 10b). Thus, while PAM-4 appears to suffer a larger penalty per unit interval of jitter, the unit interval is twice that of the PAM-2 solution offering the same throughput. It follows that if the low jitter design practices that would be used to realize the PAM-2 solution could be applied to the PAM-4 solution, a net benefit could result Added sinusoidal jitter, ps peak-to-peak 3.0 PAM-2, Megtron 6 PAM-2, "Imp. FR4" PAM-4, Megtron 6 PAM-4, "Imp. FR4" The next parameter to be considered is jitter. For this experiment, jitter is added to the default values given in Table 1 as receiver deterministic jitter (default value was 0). This jitter is sinusoidal and of sufficiently high frequency to not be tracked by the clock and data recovery unit. In this way, the tolerance of the system to additional jitter, or in another manner of speaking, the horizontal margin can be evaluated. Peak-to-peak receiver deterministic jitter amplitudes of 2, 4, and 6 ps are considered. Figure 16a shows the SNR margin as a function of the added jitter expressed in absolute time units Added sinusoidal jitter, UI peak-to-peak PAM-2, Megtron 6 PAM-2, "Imp. FR4" PAM-4, Megtron 6 PAM-4, "Imp. FR4" Figure 16: Degradation in SNR margin due to added sinusoidal jitter for 1 m STRADA Whisper channels (manufacturer recommended pinouts). (a) Jiiter in ps (b) Jitter in unit intervals Considering cases where the SNR margin is greater than zero, the PAM-4 solution suffers an approximately 1 db reduction in margin from 0 to 6 ps where the PAM-2 solution sees a 2 db reduction in margin. However, considering Figure 16b, where the added jitter is normalized to the unit interval, one can see Forward Error Correction (FEC) Both the NRZ and PAM-4 solutions fail to achieve positive SNR margin for the Z-PACK TinMan connector channels. 14

15 Further, additional SNR margin for the STRADA Whisper connector channels may be of interest for operation at lower symbol error probabilities. The symbol error probability for either receiver could be improved with the application of FEC. FEC operates by adding redundancy in the form of parity check information to the outgoing data which is used by the receiver to identify and correct errors. This effect may be represented by an effective coding gain in decibels which may then be added to SNR margin computed in this paper to estimate the improvement. The selection of an error correcting code must consider trade-offs between coding gain, over-clocking to maintain consistent throughput with the overhead of the code, and added latency. Since the DFE is a staple equalizer for these applications, the performance of the code in the presence of burst errors must be carefully considered. Burst errors may be observed at the output of the DFE, especially under stress conditions, since a decision error leads to a higher propensity to make mistakes detecting subsequent symbols. However, the application of a Reed-Solomon code, with precoding, has been estimated to provide coding gain as high as 5.4 db for a PAM-4 system under these conditions [7]. Considering the most challenging channel considered in this study, the 1 m Z-PACK TinMan improved FR4 connector channel, an initial SNR margin of 3.8 could theoretically be improved to a SNR margin of 1.6 db. More detailed analysis would be required to quantify the exact improvement and this is beyond scope of this paper. Naturally, FEC could also be applied to NRZ modulated links with comparable improvement. However, for the same 1 m Z-PACK TinMan improved FR4 connector channel, the SNR margin was 8.4 db and may not be easily salvaged even with the use of FEC. Observations and Conclusions This paper has examined 25 Gbps NRZ vs. PAM-4 signaling across multiple backplane channels with varying degrees of insertion loss and crosstalk. The goal of this work was not only to quantify sources of SNR margin degradation for both types of modulation, but ultimately to determine if and when premium channels and/or PAM-4 signaling are required for successful 25 Gbps operation. When examining sources of SNR margin degradation in timedomain simulations, several trends become clear. First, it is apparent that channel reflections (i.e. connector reflections) can be far more detrimental to system performance than channel loss (i.e. channel length and dielectric loss). This is partially true because channel loss can be more effectively compensated by equalization. While lossier channels do require more equalization, which then increases AWGN amplification, it is still clear that the primary source of SNR margin degradation is due to reflections, when they are present. This effect can be seen by comparing Z-PACK TinMan connector channel performance (noticeable reflections) to STRADA Whisper connector channel performance (minimal reflections). The second most dominant source of SNR margin degradation occurs when significant connector crosstalk is present. In channels using Z-PACK TinMan connectors, significant SNR margin degradation from crosstalk can be seen with both NRZ and PAM-4 modulation. On the other hand, in channels using STRADA Whisper connectors, there is far less connector crosstalk. In these channels SNR margin degradation from crosstalk is almost invisible with NRZ modulation and is only small with PAM-4 modulation. It is worth noting that SNR margin degradation can change noticeably with Z-PACK TinMan connector channels when varying the pinout and number of aggressors. STRADA Whisper connector crosstalk levels are so low, that crosstalk degradation does not seem to be highly sensitive to the connector pinout assignment. System SNR margin can also vary according to changes in driver rise-time and system jitter. In the case of rise-time, it turns out that SNR margin is not very sensitive. In fact, when looking at driver output rise-times between 16.4 ps and 24.3 ps (20-80%), PAM-4 SNR margin is virtually constant and NRZ SNR margin only changes by less than 1 db. On the other hand, SNR margin is more sensitive to the amount of system jitter. When adding up to 6 ps of peak-to-peak sinusoidal jitter at the receiver, SNR margin can be degraded by up to 2 db. It is worth noting that PAM-4 signals tend to degrade more rapidly than NRZ signals with increased jitter, but they also have twice the unit interval width. Therefore, though 15 Other 2011 logos, Tyco Electronics product and/or Corporation. company All names Rights might Reserved. be trademarks TE Connectivity, of their TE respective connectivity owners. (logo) and TE (logo) are trademarks. Other products, logos and company names mentioned herein may be trademarks of their respective owners.

16 decreasing more rapidly, PAM-4 SNR margin is not degraded as much as NRZ SNR margin when induced jitter reaches 6 ps peak-to-peak. Ultimately, there are two major questions that are paramount in comparing 25 Gbps NRZ vs. PAM-4 signaling across modern backplane channels. First, what type of signaling gives better SNR margin? Second, will PAM-4 signaling allow the use of legacy channels with improved FR4 and connectors such as Z-PACK TinMan connector? To answer the first question, the PAM-4 solution offered superior performance in the majority of cases. There are multiple reasons for this. First, channel ICR is better at PAM- 4 s 6.25 GHz fundamental frequency than it is at NRZ s 12.5 GHz fundamental frequency. Second, the PAM-4 solution employed advanced equalization in a DSP-based architecture that was enabled by the lower symbol rate. Finally, several impairments such as jitter and noise were held fixed between the two cases and therefore their impact on the system operation at the lower symbol rate was muted. To answer the second question, PAM-4 modulation and advanced equalization by themselves are not sufficient to enable operation over all 10GBASE-KR compliant channels. Simulation results show that 12.5 Gbaud PAM-4 achieves positive SNR margin for 0.75 m or 1.0 m STRADA Whisper channels using either Megtron 6 or improved FR4 materials. However, in the absence of premium connectors such as STRADA Whisper, additional measures, such as Forward Error Correction, would be required to achieve robust operation. References [1] Optical Internetworking Forum, OIF-CEI Common Electrical I/O (CEI) - Electrical and Jitter Interoperability agreements for 6G+ bps, 11G+ bps, 25G+ bps I/O, September [2] J. Goergen, IEEE802.3ap FR-4 Materials Review: Past Review and Future Recommendations, IEEE Gb/s Backplane and Copper Cable Study Group interim meeting, May [3] IEEE Std , Carrier Sense Multiple Access with Collision Detection (CSMA/CD) access method and Physical Layer specifications, Section 5, Annex 69B, December [4] S. Quan, F. Zhong, W. Liu, P. Aziz et al, A to- 125 Gb/s Multimedia Transceiver with Full-rate Source- Series-Terminated Transmit Driver and Floating Tap Decision Feedback Equalizer in 40nm CMOS, Digest of Technical Papers, IEEE Intl. Solid States Circuits Conf., pp , Feb, [5] K. Parhi, Design of Multiplexer-Loop-Based Decision Feedback Equalizers, IEEE Trans. VLSI Sys., vol. 13, no. 4, Apr [6] A. Pola et al., A New Low Complexity Iterative Equalization Architecture for High-Speed Receivers on Highly Dispersive : Decision Feedforward Equalizer (DFFE), Proceedings ISCAS 2011, May To state things differently, simulations in this paper show that there are only two scenarios where positive SNR margin was achieved. When running 25 Gbaud NRZ signaling, one must use premium dielectrics (Megtron 6) and premium connectors (STRADA Whisper) for successful operation. When running 12.5 Gbaud PAM-4 signaling, one can use either dielectric (Megtron 6 or improved FR4 ), but one must use premium connectors (STRADA Whisper) for successful operation. Forward Error Correction may be investigated as a means to support Z-PACK TinMan channels but this is beyond the scope of this paper. [7] S. Bhoja, W. Bliss, C. Chen, et al., Precoding proposal for PAM4 modulation, IEEE P802.3bj 100 Gb/s Backplane and Copper Task Force interim meeting, September