- SinUmdal line current. The Series Inductance Interval, a New Family of Single-Stage PFC Converters. . nigh Cost

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1 The Series Inductance Interval, a New Family of Single-Stage PFC Converters A. LkARO, A. BARRADO, J. PLEITE, R. VAZQUEZ, E. OLfAS. Universidad Carlos I11 de Madrid. Dept. of Electronic Technology. Power Electronic Systems Group. Avda. Universidad, 30; 2891 I, LeganCs, Madrid. SPAIN Tel.: ; FAX: alam-o@ ing.uc3m.cs Abstract -- In low power single-phase power supplies, single-stage AC/DC converters allow meeting low frequency harmonic Regulations such as EN and they result a cheaper and simpler solution than the two stages approach. "The Series Inductance Interval (SII)" gives name to a new family of single-stage Power Factor Correction (PFC) converters which have been developed to get three features: a storage capacitor voltage below the peak value of line voltage, low variation of this voltage with line and load changes, and input current harmonics lower than the EN Class D limits for the full load power range. This paper present the principle of operation of the SI1 converters besides the first experimental results. I. INTRODUCTION In recent years, the number of electronic loads has shown a strong growth. The conventional power supplies of these electronic loads take energy from the utility by means of a line current waveform with a high harmonic content. Voltage distortion, extra heating. lower capability of energy generation and transmission, etc. are the main problems associated to harmonics currents. Therefore, Harmonics Regulations such as the European Normative EN [I] (similar to IEC ) have arisen to reduce these effects. Two main strategies have been used to comply with the Harmonic Regulations in single-phase power supplies: Two stages approach. Single-stage solutions. These strategies are summarize in Fig. 1 together with their main features. q Singie-slage CO""W@l Control Fig. 1. TU.0.Sto#o.s cf/jprll~fch urrd S;ftg/i+~Yt~i,yi, WO slaaes amroach - SinUmdal line current * ConflOlled stonge capacitor voltage * Design Flexibility * Full Power mnge * Two lull convener$ Complexily Double energy procersing Low Efficiency. nigh Cost Sinale-slaae solutions LOW cost. Energy process8ng lower Inan two Higher eltlcle"cy. LOW complexity * Llne current lust comply With regulatlon 1,mlIL Storage capacitor voltage not Contmlled Complex Design. Llmlled wweriange.so/rftiori.\ ~.i~fii~~~ii~;.~~~rf. None of the Regulations requires unity power factor, it is enough to present harmonic currents lower than the regulation limits. This fact allows using single-stage PFC converters for low power applications in order to reduce cost and complexity. In recent years, hundreds of references and different topologies of single-stage PFC converters have appeared. therefore, to count with some survey references [2-31 has become necessary to obtain a global knowledge of the advantages and disadvantages of each solution. The performance of each solution of the state of the art can be measured by means of: limits compliance, hold-up time. component count, voltage and current stress of components, efficiency etc. However, the following aspects have gain much attention because they are the main limitation of single-stage solutions: The Storage capacitor voltage. To count with low voltage values on the storage capacitor as well as low variation of this voltage can improve the performance of single-stage PFC converters. Some aspects could be the following: Low voltage stress. Capacitors with low equivalent series resistance (ESR) can he used. Reduced size of bulk capacitor. More micro Farads must be used at low voltage to store the same quantity of energy. However, low voltage capacitors presents a lower size. Also a bigger number of capacitance values as well as a bigger number of rated voltage values are available in commercial low voltage series (<lo0 VDC). So, low voltage capacitors result better exploited and therefore, the size can be reduced. The EN Class D compliance. In a close future the Amendment 14 of EN (it will be mandatory in January 2004) will force power supplies of "high impact products" as computers, PC monitors and television sets to comply with Class D limits. At that time, feeding these equipments with input currents under Class D limits will be necessary. These limits are defined for the rated load condition, therefore it is not enough the compliance at full load but the limits must be complied in the worst conditions. In this paper a new family of single-stage PFC converters, which has been developed to improve the storage capacitor voltage and line current features, is proposed. The purpose of this paper is just to introduce these new converters, so, the principle of operation together with the first experimental results will be presented /02/$ IEEE 737

2 11. PROPOSED CONVERTERS The new SI1 family of PFC converters is characterized by presenting a stagc of the switching period. in which the magnetizing inductances of the two transformers result connected in series while their common reset is produced. The Series Inductance Interval (SII) is the name of the family and it comes from this feature. tn Fig. 2. the power stage and the main functional features of the Serial Inductance Interval - Boost converter (SII-B2) are presented. This converter will bc use as an example to show the principle of operation and the first experimental results. EN Class D The new family of PFC converters. proposed in this paper, opens the possibilities. Now a storage capacitor voltage lower or higher than output voltage can be obtained by means of a SI1 converter. Around the horizontal line, which represents in Fig. 3 the output voltage (e.g. 56 V), a lines-tilled area is distributed. This area gathers the values of the storage capacitor voltage for each SI1 topology and design. The discontinuous conduction mode (DCM) operation of the magnetizing inductances of both transformers of the SI1 converters results in a low variation of the storage capacitor voltage. See experimental results and [ 1 I] for a theoretical explanation. Line current. The typical line current waveform of the SII converters in a line half-cycle is represented in Fig. 4. This current complies with the Class D limits with a wide enough margin. Also. if the current version of the EN is applied, this shape will be classified into Class A, see also Fig. 4. Fig. 3. SII- E_.~clrrrrr~ irrrrl rrririrr,firrrc.fi/~rro/.ti.lrfrrr~,.s The main features can be summarized as follows: Storage capacitor voltage. According to the voltage on the storage capacitor the most interesting solutions of the state of the art [4-10] can be classified into two big groups which are represented in Fig.3. + IC, Group A a5 265 Line voltage (VRMs) Fig. 3. Sfori7ge ctrpirciror idtirgc 1 crsir.s AC irrlirrt i~ilfi~ge. The d!j%rcwt g~oll[ls Of.SO/~ltiO~lS (lrl.shon?l /JY Ifll liii,s l!fgtti?. llly<i. N /i~fl S~f;//l l/ (IIX LI rrr7d (1 holtl lirrr. Grmy A: Those solutions which present a limited storage capacitor voltage although always higher than the peak value of the line voltage [4-81. This group is represented in Fig. 3 with a gay area. Grmp B: Those solutions in which the bulk capacitor voltage is clamped to the peak value of input voltage [9- IO]. This group is shown in Fig. 3 as a bold black line. ri2 n WI Fix. 4. Tvpictrl lirrr cr!rrerlr c!f SfI PFC corrl erfers. Furthermore, also due to the MCD operation, this waveform is invariant with the load power, so Class D limits will be complained for the full load power range. Output voltage presents fast dynamic response. For any value of line angle along a line half-cycle, the load is fed from the line and complementarily from the storage capacitor. Therefore the Hz ripple is not present at the output and a high band-width control loop can be used to regulate the converter. This type of control loop provides the fast dynamic response to the output voltage. Energy Processing. By design, the portion of the output power processed twice can be reduced below the 30%. On the one hand, the switch S2 transfers a low quantity of power. on the other, it present a reduced voltage rating due to the low voltage value on storage capacitor. Therefore, its cost and losses will be reduced. Component count. The converter SII-B2 presents just an extra diode in comparison with a Boost-Flyback two stages approach. Other topologies of the family present the same number of components than the previous two stages approach. Furthermore, the SI1 family counts with a single-switch topology. Moreover, a single control loop is used to tightly regulate the output voltage. This control loop generates only a duty cycle that controls both active switches. 738

3 111. PRINCIPLE OF OPERATION To introduce the principle of operation and also to present thc first experimental results of the SI1 family, the SII-B2 converter has been selected as an example. Energy Flow. All the converters of the family SI1 can be classified into I-IIIB type if the classification proposed in [ 121 is used. This method proposes a block diagram very useful to explain the internal energy flow of the SI1 converters. Fig. 5. rrc~,;q~,/lrl,l~ (rrrrl hl0c.k di~rgrelrj1 f!/ tlrc. SI/ ~'orri'i'r/c'rs The inner converter placed in the position 2 takes the power from the line (branch I in Fig. 5). It can be described as a Flyback converter with two output diodes (Dsi, DAus). A portion of this energy (branch 0 in Fig. 5 and trace 0 in Fig. 6.d) is directly delivered to the output through Dsi, soi this energy has been processed once. The other portion of the input energy is stored in thc capacitor C, through the diode DAuX (branch 0 in Fig. 5). hrty Cycle equals the output power, when input voltage reaches zero Volts. In Fig. 6.a it is shown how the duty cycle must vary wilh the line angle to keep the output voltage constant. The output voltage presents a fast dynamic response since the addition of the average currents through Dsl and DS2 is constant along the whole line half-cycle, see Fig. 6.d. During a portion of the line cycle, C, stores energy which is delivered to the output when input power is lower than the output power (Fig. 6.c). Finally, the input current results modulated by the duty cycle and the input voltage, as it can be seen in Fig. 6.b. Switching process. In order to make easier the description of the switching process, an agreement about the magnetizing inductances and turns ratio of transformers TI and T2 has been adopted. Using this agreement, Li is the magnetizing inductance of Ti when it is viewed in the primary winding of TI. Therefore, L12 is the magnetizing inductance of TI when is referred to the secondary winding. The different stages of a switching period could be summarized as follows (Fig. 7): I.<,./ $ 1 * A Line current 1 Average cunent m C, Fig. 6. Lirrr,frc,ilrterrr.?. tlreowtic(r1 \r(ilvfonrra, The components LI2. S2 and Ds? can be seen as a Boos1 converter (this is the reason for the name SII-B2) which holds the position 1 of the block diagram. Along the whole line half-cycle, and complementarily to the single processing energy, this Boost converter feeds the output via Ds~ (branch 0 in Fig. 5 and trace 0 in Fig. 6.4 with the energy stored in capacitor C,. This energy is processed twice and its value Fig. 7. Swit(.lririg,tr.rilrriw? tlrrori~ti(.cil ii~(rivforirr.s. Stage I: SI and S2 are On. LZ2 is magnetized with the voltage on storage capacitor and L, I is magnetized from input voltage. The duration of this stage normalized with the switching period is cl. Stage 2: L12 resets through Ds2 to the output. During this stage the diode DAux is reverse biased because the voltage in the transformer T2 is imposed by the conduction of DS2. Moreover, n?, the transformer turns ratio of Tz, is designed to be lower than I.( n2<1, defined as 1:n:). For this reason, the primary winding oft2 together with DAUX can be seen as a controlled switch, which transition to on-state is delayed until DS2 has switched off. The delayed conduction of DAvx eases the flow of the single processing energy. The normalized duration of this stage is dl. Stqe 3: DAUX and Dsl share L12 current. Now, a portion 739

4 of the LI2 current can flow through DAUx. due to the magnetization of L21 with the voltage Vo-V,., (output voltage minus storage capacitor voltage). When the value of the current through DAux equals to the current in LIZ, DS1 switches off. The duration of the third stage is <I2. Stage 4: The Series Inductance Interval. Once Dsl has switched off, L12 and L21 result connected in series and reset together. This stage is common to the whole family and gives it its name. Stages 3 and 4 allow the recharge of CI. The normalized duration of the series inductance interval is d3. After this stage, as in any converter working in DCM, a dead time is produced. The duration is <I4. Switching modes. Along the line half-cycle three different switching modes appear, see Fig.8. These modes have been named as Mode 0, Mode 1 and Mode 2. Mode 0: The voltage in the primary winding of the transformer TI when SI is on, is given by (I): If the input voltage is lower than V171<lr the diodes of the input rectifier result reverse biased, therefore, the input current is zero. Output is only feed from C,, but this capacitor is not recharged. Only the converter SII-B2 presents Mode 0.: nevertheless, this operation mode can be eliminated by design. Mode 0 Mode 1 Fig. H. Suirchirtg iirodc~s riloiiji line c:ylr. Mode 1: For low values of the input voltage, L12 resets before than L22 and therefore, the diode DAOX never is forward biased. In this switching mode, output is feed from the input and from the storage capacitor, but C, is not recharged. Mode 2: This is the principal switching mode and its corresponding switching process has been described in the previous paragraph. In this mode the diode DAUX results forward biased when L22 has reset. Therefore, in each switching cycle, the current through LI2 discharge and charge C,. However, the average current in C1 is zero when the averaged value is calculated along a line half-cycle. So, the steady state on the storage capacitor is reached at the double of the line frequency ( 1 00, I20 Hz). Functional design considerations. Two design considerations have to be taken into account for the SI1 converters to work properly. These considerations are originated in the switching process and they can be described as follows: 1. D,.,u,y hrive to De reverse binsed iii stnge 2. For all the SI1 converters, the single processing energy is due to flow through Dsl in stage 2. This fact would not be possible if DAux always be forward biased. Applied to the SII-B2 converter this consideration results in a turns ratio lower than 1 for the transformer T2 (nzcl). 2. DAcix Izmv to be,for\vat-d biased iii stage 3. In this way, a portion of the current of LIZ can flow through DAUx to recharge C,. To consider that the anode voltage of DAUX is higher than its cathode voltage results in a storage capacitor voltage lower than output voltage if this consideration is applied to the SII-B2 converter. The main functional design criteria for each SI1 topology are obtained when these previous considerations are applied to each SI1 converter. Suitable structures Based on the principle of operation described in this paper up to six different topologies have been developed. They share the block diagram of Fig. 5. the energy flow, the waveform of the line current and the DCM operation of the magnetizing inductances of both transformers. However they can be designed to present different voltage values on storage capacitor, although the lower variation of this voltage is common to all the SI1 topologies. According to the storage capacitor voltage value, the SI1 converters can be classified into two groups: Groip VC,,: Those converters that always present a storage capacitor voltage lower than output voltage (VclcV,,). The converter SII-B2 belongs to this first group. Group VC,.,,: Those converters in which the storage capacitor voltage can be selected to be lower or higher than output voltage by means of design. IV. EXPERIMENTAL RESULTS In order to check the performance of the proposed family a SII-B2 converter for an output voltage of 56 V and European input voltage range has been designed according the snecifications listed in Fig. 9. Line frequency waveforms. In Fig. 10, the line frequency waveforms for an input voltage of 220 VKMs have been presented. It can be seen the similarity between both the theoretical duty cycle and line current shown in Fig. 6 and the corresponding experimental 740

5 results. Also, in Fig. IO it can be seen how the design has achieved that line current does not present the Mode 0 switching mode. I I 31 - * A z30- m L - 20 t B - o v V EN Compliance. The typical line current of SI1 converters in a line hallcycle is shown in Fig. 4 and Fig. 6 (theoretical) and Fig.10 (measured). This waveform complies with Class D limits with a wide enough margin. as it can be seen in Fig 11. In this figure, EN Class-D limits and the main harmonics of the SII-B2 line current are shown for 220 V line voltage and full load zo = Harmonic number Fi,y. I I. Hi~r~riorric coiitriit iri the e.yeriiiieirto1 protonpi trrd t/w EN CIU.YS-D limits. For the full load range measured in the prototype. (Po: 15W + IOOW), the input current has met the Class D limits. The current waveform is independent of the load power, so, the harmonic content in (ma/w) remains constant and therefore Class D limits will be complained for any load condition. This fact is due to the DCM operation of the converter It is important to point out that the measure of the current harmonics has been made with non senoidal line voltage. This fact could produce higher values of the current harmonic than the aciual ones. Storage capacitor voltage. In Fig. 12 is shown the measured variation of the storage capacitor voltage as a function of the load power and the input AC voltage. The voltage values measured on the prototype has resulted around 29 VIK. for an output voltage of 56 Vlx. While the European range of line voltage varies 1.5 times between its minimum and maximum values ( a? 0805 E E I Load Power (W) Fig Eflicirrri.~ ~rrc~cf.sffri~t~ ill dlr pl-orrln~jp (IS (I,fiorctioll oftllc, /(lifd pou.c~r cirrd 111r irrprrt AC i,o/tlrge. Dynamic response of output voltage. Fig. 14 shows the line current under a load step of%% of amplitude. Due to the fast dynamic response of the converter, the input current increases rapidly. Moreover, it can be seen how the output voltage is tightly regulated. The maximum output voltage ripple measured (full load) is around 700 mv (1.25 % of nominal output voltage). This features on output voltage. have been obtained with a single control loop. Furthermore 74 1

6 the same duty cycle is applied to both MOSFET SI and S2, see Fig.3. I r- I I Chl 1 Oov'v Ch2 IOOV M10 Oms Ch3f S20mV I nm 1 oov CI1.l 1 oovn VI. CONCLUSIONS The SI1 converters. a novel family of single-stage power factor correctors, has been introduced. The main features are the following: These converters present EN Class-D compliance for the full load power range. The voltage on the storage capacitor can be chosen to be lower or higher than output voltage by selection of the SI1 topology and design. In this paper. a prototype of the SII-B2 converter has been checked. This prototype has obtained an experimental voltage value around 29 VIK on storage capacitor, for an output voltage of 56 Vlx. Also, a reduced variation with line voltage (<I 7%) and load power (<2%). Therefore, the size of the storage capacitor has been reduced in comparison with other solutions of state of the art. No special control strategy is needed to control the storage capacitor voltage. A tight regulated output voltage with fast dynamic response is achieved by means of a single control loop operating on both MOSFETS. The measured effkiency in the prototype is around the 80% for European input voltage range. The components count also results advantageous because just a diode is added in comparison with a Boost - Flyback two stages approach. In the SI1 converters, the power transferred by means of the second controlled switch can be lower than the 30% and it have a low voltage rating. Furthermore the family SI1 counts with a single-switch topology. REFERENCES [ 1 ] IEC : A.l: A.2:1998. EMC Part 3-2: "Limits- Limits for harmonic current emissions (equipiiient input current 2 16 A per phase)". [ 2 ] 0. Garcia. J.A. Cohos. R. Prieto. P. Alou. J. Ucrda. "Power Factor Correction: A Survey" IEEE PESC '01. Pp [ 3 ] C. Qiao. K.M. Sniedley. "A Topology Survey of Single-Stage Power Factor Corrector with a Boost Type Input-Current-Shaper". IEEE Transactions on Power Electronics. Vol. 16. No.3. May Pp [ R. Redl et al. "A new family of siii:le-stage isolated powei--factor correctors with fast regulation of the output voltage". IEEE PESC '94. Pp M Daniele. P. Jain. G. Jbos. "A Singlt Stage Single Switch Power Factor Corrected AC/DC Converter". IEEE INTELEC '96. Pp J. Quian. F.C. Lee. "A High Efficient Single Stage Single Switch High Power Factor AC/DC Convener with Universal Input". IEEE APEC '97. Pp L. Huher and M.M. Jovanovic. "Single-stage. Single Switch. Isolated Power Supply Technique with Input Current Shaping and Fast Output-Voltage Regulation for Universal Input-Voltage-Range Applications". IEEE APEC '97. Pp J. Sehastihn. M.M. Hernando. P. Villeyas. J. Diaz. A. Fontan. "Input Current Shaper Based on the Series Connection of a Voltage Source and a Loss Free Resistor". IEEE Applied Power Electronics conference (APEC) Pp Garcia. J.A. Cohos. R. Pi-isto. P. Alou. J. Uceda. "Simple AC/DC Converters to Meet IEC ". IEEE APEC '00. Pp N. Vbzquez. C. HernQndez. R. Cano. J. Antonio. E. Rodriguez. I. Arau. "An efficient Single-Switch Voltage Regulator". IEEE PESC '00. Pp. 8 I R. Redl. L. Balogh. "Design Considerations for Single-Stage Power Factor Coirected Power Supplies with Fast Regulation of the Output Voltage". IEEE APEC '95. Pp C.K. Tse and M.H. Chow. "A Theoretical Examination of the Circuit Requirements of Power Factor Correction". IEEE PESC '98. Pp