High performance ac-dc notebook PC adapter meets EPA 4 requirements

Transcription

1 High performance ac-dc notebook PC adapter meets EPA 4 requirements Alberto Stroppa, Claudio Spini, Claudio Adragna STMICROELECTRONICS via C. Olivetti Agrate Brianza (MI), Italy Tel.: +39/ (039) , 5106, 5097 Fax: +39 / (039) alberto.stroppa@st.com, claudio.spini@st.com, claudio.adragna@st.com URL: Keywords «Power Factor Correction», «Efficiency», «Sensorless Control», «Switched Mode Power Supply». Abstract This paper presents the characteristics and the performance of a 75W-19V ac-dc adapter for notebook PC tailored on the latest Energy Star Program requirements. The power supply is composed of a frontend PFC pre-regulator and a Flyback downstream converter. An innovative PFC control circuit sensing both the input and the output voltages through an auxiliary winding is the key element in achieving the desired performance. A prototype board has been implemented and test results are reported. Introduction The new guideline coming from Energy Star Program and in particular the EPA rev. 4.0 COMPUTERS document, introduces not only limitation on the minimum efficiency during computer active operation, but also stringent limitations on the maximum power consumption during computer off-mode, sleep mode and idle state. From the power supply point of view this means that very high efficiency is required also at light loads from 15-10W down to 500mW output power. Therefore, the purpose of this study has been to design an ac-dc adapter for notebook PC whose main characteristic is its high efficiency during no-load and light load operation. The power converter is composed of a front-end PFC pre-regulator and a Flyback downstream converter. To maximize the efficiency during light load operation, the following features have been implemented: The flyback stage operates in quasi-resonant mode, thus reducing the switching losses that become significant mainly at light load. The downstream converter acts as the master stage, allowing complete PFC shut-down during light load operation when harmonic distortion reduction is not required. An innovative sensorless PFC control circuit is implemented by sensing both the input and the output voltages through an auxiliary winding on the boost inductor instead of using resistor dividers like in the standard approach.

2 Adapter architecture The circuit is composed by two stages: a front-end PFC using the L6563S and a flyback converter based on the L6566A. The flyback stage works as master and it is dedicated to control the circuit operation including the stand-by and protections. Additionally, it switches on and off the PFC stage by means of a dedicated pin (VCC_PFC). Because the PFC is kept off during light load operation, an excellent efficiency is achieved even at light load. The circuit is designed so that at start-up the flyback starts first, then it turns-on the PFC stage controlling the L6563S via the Vcc_PFC pin. Therefore, the flyback stage is designed to manage at start-up the full output power overall the input voltage range because it has to guarantee the regulation of the output voltage even during load transition when the load is increasing but the PFC is still not yet delivering the nominal output voltage. Of course this condition can be maintained only for short time, typically tens of milliseconds, because the flyback is not designed to sustain this condition from thermal point of view. The flyback controller is directly connected to the bulk capacitor and at start-up, an internal high voltage current source supply the IC until it starts switching, then the high voltage current source is automatically switched off and the transformer auxiliary winding will provide the voltage to power the IC. Afterwards, according to the load level, the L6566A activates the L6563S powering it via the dedicated pin. Because the L6566A integrated HV startup circuit is turned off and therefore it is not dissipative during the normal operation, it gives a significant contribution to power consumption reduction when the power supply operates at light load. This gives a significant contribution to meet stand-by worldwide standards currently required. PFC PRE-REGULATOR (BOOST) DC-DC CONVERTER (FLYBACK) VinAC EMI Filter HV Startup DC L6566A is turned off in case of PFC s anomalous operation, for safety L6563S L6566A PFC WORKS AS SLAVE L6563S can be turned off at light load to ease compliance with energy saving requirements DD WORKS AS MASTER Fig. 1: Adapter electrical diagram.

3 Sensorless PFC control The main function of the PFC is to keep the current absorbed from the power line tracking the line voltage to comply with the EN or other similar regulations and to regulate the output voltage of the boost stage powering the downstream converter. Therefore, it is necessary to sense the PFC output voltage as well as the input one coming from the mains and feed these two signals to the controller. The simplest way to implement these functions is to sense both input and output voltage through two resistor dividers as shown in. These resistors are in the MΩ range (6.6MΩ for the input divider and MΩ for the output divider of the example in fig. ), however their power dissipation, which is negligible at full load, becomes significant at light load and, even if the PFC is turned off at light load, the power dissipation of the two dividers is always there. Additionally, at light load both the input and the output voltage becomes very close to the peak value of the rectified mains because the input and output capacitors will act as peak detectors of the rectified mains voltage. Considering the worst case for power consumption once the SMPS is working at European mains range, the power dissipation of these two dividers can be easily calculated as follow: P P ( 30V ) = mw VIN = = (1) R 6.6MΩ MULT 16 MULT ( 30V ) = mw VOUT = = () R MΩ FB 53 MULT For example, if we calculate the impact of these losses with a 1W output load these two circuits affect the overall efficiency about 7%. Fig. : Typical Transition mode PFC electrical diagram. To overcome this problem, in this board a sensorless PFC solution has been implemented (Fig. 3). The information relevant to input and output voltages is provided to the PFC controller L6563S by an auxiliary winding of the boost inductor.

4 Fig. 3: Sensorless PFC electrical diagram Operation of the sensorless PFC is explained here following, referring to fig. 4: a) During the MOSFET OFF-time the voltage applied across the boost inductance is the difference between the output and the input voltage. So D is reverse biased and C will be charged via D1 to: Vin V = (3) n Where n is the winding turn ratio. b) During the MOSFET ON-time the voltage applied across the boost inductor is Vin (with reversed polarity) so D1 is reverse biased and the capacitor C1 is charged via D to a voltage equal to: Vin V = (4) 1 n Hence we can use the voltage across C1 to feed the multiplier input of the L6563S because it is information about the instantaneous value of the input voltage, as needed by the control part to shape the input current. Fig. 4: Sensorless PFC Operation Theory

5 c) Because C3 is in parallel to the series of C1 and C, the voltage at which it will be charged will be proportional to the PFC output voltage and so can be used to get the output voltage feedback signal: Vin Vin V = + = (5) 3 n n n During light load operation the PFC controller is stopped by the PWM controller, so the MOSFET doesn t switch and there is no reflected voltage on the auxiliary winding; C1, C and C3 are not charged and discharged anymore and so both the multiplier and the feedback networks will not dissipate. C1, C and C3 have to be dimensioned accurately to assure proper circuit behavior. First of all it is a good choice selecting C1=C to get symmetrical circuit response. To select properly C1 and C values it should be considered that signal on C1 and C must track the input rectified voltage. Considering a 60 Hz mains frequency, the rectified voltage frequency is twice and relevant period is 8.3 ms. We can assume as a rule of thumb a time constant one fifth of the rectified period i.e. about T c1 = 8.3/5 = 1.66ms. Referring to figure 3, the discharging time constant is given by (C1+C)*(R1+R). In the reference design presented we selected R1 = 680 KΩ and R = 56 KΩ. Assuming C1 = C, their value is calculated as follow: C TC1 = CMAX = 1. nf (6) ( R + R ) 1 MAX = 1 1 The charging time constant is given by the capacitor value times the dynamic resistance of the charging diode (D 1 or D ); because its value is far less than R1+R value, the condition imposed on the capacitors value is less stringent that the one imposed by the discharging constant. A second constraint on C1 value is that we have to assure that the voltage on this capacitor has not to decrease significantly during the MOSFET off-time. For this design the worst case is when the L6563S controller operates at his starter frequency and the off time is 150usec. In this case we consider as a rule of thumb a minimum time constant five times the maximum off-time: C 5 TOFF = ( R + R ) 1 min = pf Finally the selected value for C1 and C is 1 nf. Of course C3 time constant has to be significantly longer than C1 and C ones in order to feed a stable feedback signal into the PFC controller Error Amplifier. Anyway the time constant should not be too long to assure a proper loop response. In particular, in case of load steps and consequent output voltage decreasing, C3 voltage has to follow quickly the output voltage deviation. It makes sense imposing that the discharging time constant of C3 has to be at maximum equivalent at the output bulk capacitor discharging time constant. The maximum power applied at the PFC is 80 W that corresponds to an equivalent kω resistive load. Because the PFC output capacitor is 100 µf, the output power cell time constant is 100µ F kω = 0. sec = T (7) c Referring to figure 3, R3 = 180 kω and R4 = 47 kω. That leads to: TC C3 = = 0nF. (8) R + R 3 4

6 Experimental results Harmonic content measurement The board has been tested according to the European rule EN Class-D and Japanese rule JEITA-MITI Class-D, at both the nominal input voltage mains. As reported in figures 5 and 6, the circuit is able to reduce the harmonics well below the limits of both regulations with performance equivalent to traditional PFC architectures. THD = 5.95% - PF = Fig. 5: Compliance to EN standard at 30Vac-50Hz THD = 4.5% - PF = Fig. 6: Compliance to JEITA-MITI standard at 100Vac-60Hz On bottom side of the diagrams the Total Harmonic Distortion and Power Factor have been measured too. The values in all conditions give a clear idea about the correct function of the PFC.

7 Efficiency Measurement The EPA rev. 4.0 Computers requires a minimum efficiency higher than 80%, measured at 0%, 50% and 100% of nominal load. In Table I the overall efficiency measurements are reported and compared with the Energy Star regulations. As visible, these values are fully compliant. Table I: Overall Efficiency compared to EPA rev.4.0 COMPUTERS 30 Vac 50 Hz 115 Vac 60 Hz EPA4 Load [V] Iout [ma] Pout Pin Eff. [V] Iout [ma] Pout Pin Eff. Min eff. 0% load Pass 50% load Pass 100% load Pass Additionally, the EPA rev.4.0 Computers document poses specific limitations to the maximum consumption of computers during stand-by mode, sleep mode and idle state but this is not sufficient to deduce the required power supply efficiency because the load applied during these states is not indicated. This information comes from computer manufacturer requirements. The major computer manufacturers require efficiency higher than 70% from 1W to W input power and efficiency higher than 75% from W to 3W input power. Experimental Results are shown in Fig % 85% 80% Efficiency 75% 70% 65% 60% 55% 30V-50Hz 115V-60Hz EPA4 50% Pin Fig. 7: New design light load efficiency measurements. These results have been compared to whose of a very similar design [5]. The two designs differ mainly in two aspects: the older does not implement the sensorless PFC and the flyback stage is configured to operate in fixed frequency instead of as quasi resonant. As visible, sensorless approach, allows gaining more than 10% efficiency at 1W.

8 90% 85% Efficiency 80% 75% 70% 65% 60% 55% 30V-50Hz 115V-60Hz EPA4 50% Pin Fig. 8: Previous revision light load efficiency measurements. In the following table, no load consumption are indicated and compared to the reference design results. Table II: No load Consumption Vin New approach power consumption Typical solution power consumption 115 Vrms 83 mw 110 mw 30 Vrms 15 mw 18 mw As indicated in Table III, this converter is also compliant with the newer, most stringent EPA rev.5.0 Computers limits for active load efficiency. Table III: Overall Efficiency compared to EPA rev.5.0 COMPUTERS 30 Vac 50 Hz 115 Vac 60 Hz EPA4 Load Iout Pout Pin Eff. Iout Pout Pin Eff. Min eff. [V] [ma] [V] [ma] 0% load Pass 50% load Pass 100% load Pass This latest Energy Star document, which effective date is July 009, introduces a new method of testing the energy performance of computers. It sets a limitation on computer Typical Energy Consumption (TEC) which is a value for typical annual electricity use, by measurements of average operational mode power levels scaled by an assumed typical usage model (duty cycle). This new approach, like the previous one, does not establish direct limits to the power supply minimum efficiency for each different state. In fact it depends by the actual load applied by computer itself. At the moment this paper has been written, not all the major computer manufacturers have produced

9 specific requirements for EPA rev.5.0 compliant designs. Anyway, the good margin achieved against the EPA rev.4.0 limits, proves that this board can be a viable solution even for coming EPA 5 computer designs. Conclusion A 75W-19V ac-dc adapter for notebook PC has been designed. A prototype has been tested and compared with previous reference design. Thanks to innovative solutions implemented, good improvement of light load efficiency and no-load consumption has been achieved. This design provides reference to achieve efficiency performance at light load compliant with the latest Energy Star Program eligibility Criteria. References [1] Energy Star Program requirements for computers: Version 4.0, available at [] Energy Star Program requirements for computers: Version 5.0, available at [3] L6566A Datasheet, available at [4] L6563S Datasheet, available at [5] AN690-19V-75W adapter with pre-regulator PFC using the L6563 and the L6566A, available at [6] Optimizing performance in UC3854 power factor correction application - Bill Andreycak 1999