Reference Design Report for a 21W (42V/0.5A) LED Driver Using SFL900
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1 Reference Design Report for a 21W (42V/0.5A) LED Driver Using SFL900 Specification Application VAC Input; 42V/0.5A output LED Driver Author Document Number System Engineering Department SFL900_LED Driver_21W_42V0.5A Date Revision 1.0 Key Features Both Primary-side control and secondary-side control with single stage PFC for LED driver Power factor >0.9 Built in Soft Start THD<10% using min-thd TM technique MAX 90KHz frequency clamping for EMI Pass EN55015 class B and FCC Part 15 Class B OVP /SCP protection features Low Components Count SiFirst Technology SiFirst_RDR_SFL900_V1.0
2 Contents 1. Introduction Specifiction Schematic PCB Layout Module Snapshot Bill of Materials Transformer Specifications Electrical Diagram Electrical Specification Materials Transformer Build Diagram Tranformer Winding Specification Performance Data Test Equipments Summary of Testing Results PF/THD/Efficiency vs. Power and Line Voltage No Load Input Power Output short Input Power Waveforms and Testing Results Drain Voltage and Current Sense Startup Drain Voltage and Current Sense Nomal Operation Ripple and Noise Output current overshoot Max Mosfet Vds and second diode Vak Voltage Protections Output Short Circuit Protection Over Voltage Protection EMI Testing Results Conduction EMI Testing Results Radiation EMI Testing Results SiFirst Technology SiFirst_RDR_SFL900_V1.0
3 1. Introduction This engineering report describes a 21W (42V/0.5A) universal input power supply for LED Driver applications. This reference design is based on the SiFirst s product SFL900. The mechanic dimensions are 79mm in length, 46 mm in max width. It can be using to par 38 LED lamp. SFL900 is a high performance, high power factor flyback PWM controller special for LED lighting applications. The IC adopts unique super-pfc/psr TM which can support both PSR and SSR applications. SFL900 has built-in load CC compensation and AC line CC compensation function, which can further increase LED output CC accuracy. The IC has Max.90KHz frequency clamping function and soft totem pole gate driver to improve system conduction and radiation EMI. The IC will clear External EA Feedback network before IC power on, which can reduces startup LED current spike. The IC also has soft start control during power on period. 2. Specifiction Description Min Typ Max Units Remark Input Voltage / VAC 2 Wire Frequency 47 50/60 63 Hz Output (Measure at the end of Cable) Output Current 0.5 A Output Ripple Current 150 ma Output Current A Line Regulation ±2 % Load Regulation ±3 % Continuous Output Power 21 W Efficiency(Measure at the end of Cable) Required average efficiency 88 % 115VAC/230VAC Protection Feature Short Circuit Protection Over Voltage Protection Output shut down with automatic recovery Environmental, Surge and ESD Ambient Temperature 0 40 Operating Humidity % R.H Storage Temperature Storage Humidity 0 95 % R.H EMI Test Pass EN55015 Class B and FCC Part15 Class B with 6dB margin SiFirst Technology SiFirst_RDR_SFL900_V1.0
4 3. Schematic 4. PCB Layout Print circuit board (PCB) layout and design are very important for switching power supply where the voltage and current change with high dv/dt and di/dt. Good PCB layout minimizes excessive EMI and prevents the power supply from being disrupted during surge/esd tests. The PCB layout guidelines are highlighted as following: 1. The area enclosed by the transformer auxiliary winding, Ddd and Cdd should be kept short path. 2. The ground of the control circuits should be connected first, then to the other circuitry. 3. Regarding the ESD discharge path, put in the shortcut pad between AC line and DC output (which is the best way). The other method is to discharge the ESD energy to AC line through the primary main ground. Because ESD energy is delivered from secondary to primary through the transformer stray capacitor, the controller circuit should not be placed on the discharge path. 4. For the surge path, select fusible resistor type with wire wound type to reduce inrush current and surge energy, using π input filter (two bulk capacitor and one inductance) to share the surge energy. 5. The drain trace length should be minimized to reduce EMI. 6. RCD Clamp and output rectifier diode loop areas should be minimized to reduce EMI 7. The AC input is located away from switching nodes to minimize noise coupling that may bypass input filtering. SiFirst Technology SiFirst_RDR_SFL900_V1.0
5 PCB Layout (Top view) Layout (Assembly Drawing, Bottom view) PCB SiFirst Technology SiFirst_RDR_SFL900_V1.0
6 PCB Layout (Bottom Copper, Bottom view) 5. Module Snapshot SiFirst Technology SiFirst_RDR_SFL900_V1.0
7 6. Bill of Materials POSITION DESCRIPTION QTY C1 Capacintor metal poly 154/630V, ±20% 1 C2 Capacintor Electrolytic 4.7UF/400V,8*12, ± 20% 1 C3 Capacintor Electrolytic 47UF/50V,6.3*11, ± 20% 1 C4 Capacintor Ceramic 102/1KV, ±20% 1 C5 C6 Capacintor Electrolytic 470UF/50V,10*20, ± 20% 2 C7 Capacintor Ceramic 101/50V, 0805, 10% 1 C8 Capacintor Ceramic 152/50V, 0805, 10% 1 C9 Capacintor Ceramic 104/50V, 0805, 10% 1 C10 Capacintor Ceramic 222/630V, 1206, 10% 1 C11 Capacintor Ceramic 10PF/50V, 0805, 10% 1 C12,C13,C14 NC CX1 Capacintor X2 0.1UF/275V P=10 1 CX2 Capacintor X UF/275V P=10 1 LJ1 Jumper 0.6*18mm 1 R1 Resistor 10K % 1 R3,R4 Resistor 470K % 2 R5 Resistor 10K % 1 R6/R7 Resistor 3.9R % 2 R8 Resistor 3.0R % 1 R9 Resistor 2K % 1 R10,R18 Resistor 15K % 2 R11,R26,R27 Resistor 100R % 3 R12 Resistor 82R % 1 R13,R14 Resistor 47K % 2 R15 Resistor 100K % 1 R16,R17 Resistor 300K % 2 R19,R20 NC R21 Resistor 0R % 1 R22 Resistor 91K % 1 R23,R24 Resistor 1M % 2 R25 Resistor 30K % 1 D1 Diode IN4007 1A/1KV DO-41 1 D2 Diode FR107 1A/1KV DO-41 1 D3 Diode HER304 3A/300V DO-201AD 1 D4 Diode M7 1A1KV SMA 1 D5 Diode 1N4148W SOD BR1 Bridge B6S 0.8A/600V TO269AA 1 F1 Fuse, 2A/250V 4*10 1 L1 DR6*8 400UH 0.20mm 1 L2 DR8*10 1.5mH 0.25mm 1 LF1 UU mh min 1 LF2 Core T10*4*5 100UH min 0.6mm 1 T1 RM8 1.5mH 1K/1V 1 Q1 MOSFET, TK5N60 5A/600V TO CY1 Capacintor 102/400V 1 IC1 SFL900, SO-8 1 VAR1 NC PCB SFL9X0.PCB 1.6mm 1 SiFirst Technology SiFirst_RDR_SFL900_V1.0
8 7. Transformer Specifications 7.1 Electrical Diagram 7.2 Electrical Specifications Primary Inductance Pin 12-10, all other windings open, measured at 1KHz, 1Vrms 1.5mH, ±8% Primary Leakage Inductance Pin 12-10, with Pins P1-P2 shorted, measured at 10KHz, 1Vrms 20uH(max) Electrical Strength 60 seconds, 60Hz, from N1,N2,N4,N5 to N3 3750Vac 7.3 Materials Item Description [1] Core: RM8, TDK PC40 or equivalent [2] Bobbin: R8, Horizontal, 12 pins (6/6). See attached drawing [3] Magnet Wire: Φ0.28mm, for the Shield Winding [4] Magnet Wire: Φ0.28mm, for the Primary Winding [5] Magnet Wire: Φ0.28mm, for the Auxiliary Winding [6] Triple Insulated Wire: Φ0.40mm, for the Secondary Winding [7] Tape: 0.05mm thick, 9mm wide [8] Tube :Φ0.70mm Teflon Tube SiFirst Technology SiFirst_RDR_SFL900_V1.0
9 7.4 Transformer Build Diagram 7.5 Transformer Winding Specification No Winding Material Start Turns Finish 1 N1 0.28mm*1 2UEW NC 2 TAPE TAPE W=9mm 2 3 N2 0.28mm*1 2UEW TAPE TAPE W=9mm 2 5 N3 0.40mm*1 triple insulated wire P1 27 P2 6 TAPE TAPE W=9mm 2 7 N4 0.28mm*1 2UEW TAPE TAPE W=9mm 2 9 N5 0.28mm*1 2UEW TAPE TAPE W=9mm 3 SiFirst Technology SiFirst_RDR_SFL900_V1.0
10 8. Performance Data 8.1 Test Equipments Item Vender Vender AC Source Gwinstek APS9501 Electrical Load Prodigit 3314F Digital Power Meter Voltech PM1000 Oscilloscope LeCroy Wavesufer24Xs Thermal Agilent 34970A 8.2 Summary of Testing Results Description Test Results Units Remark Input MAX Total Harmonic 9.05 % <10% Output Output Current MIN MAX A <±3% Output Ripple Current 124 ma <150mA Max. Output Voltage 47.2 V Min. Output Voltage 22.4 V Line Regulation 1.5 % <±2% Load Regulation 1.9 % <±3% Continuous Output Power 21 W Pass Average Active Mode Efficiency(Measure at the end of % Protection Feature Short Circuit Protection OK Over Voltage Protection OK EMI EMI Test Pass EN55015 Class B and FCC Part15 Class B with 6dB margin Pass Pass SiFirst Technology SiFirst_RDR_SFL900_V1.0
11 8.3 SFL900 PF/THD/Efficiency vs. Power and Line Voltage Vin (VAC) Pin (W) Vout (V) Iout (A) Pout (W) PF THD (%) Efficiency Average Efficiency load regulation % % % 86.03% ±1.3% % % % % 88.30% ±1.3% % % % % 89.40% ±1.7% % % % % 89.34% ±1.8% % % % % 88.73% ±1.9% % line regulation Vout=30v Vout=35v Vout=42v Vout=45v Total regulation ±1.2% ±1.3% ±1.5% ±1.4% ±2.7% SiFirst Technology SiFirst_RDR_SFL900_V1.0
12 Efficiency 21W LED Driver Using SFL900 Efficiency VS Voltage 91.00% 90.00% 89.00% 88.00% 87.00% 86.00% 85.00% 84.00% 83.00% Input Voltage 30V 35V 42V 45V Fig.1 Efficiency vs. Line Voltage and Output Voltage 8.4 No Load Input Power Input Voltage 90VAC 115VAC 230VAC 264VAC SFL mW 213mW 311mW 371mW 8.5 Output short Input Power Input Voltage 90VAC 115VAC 230VAC 264VAC SFL mW 123.2mW 255.8mW 315.9mW SiFirst Technology SiFirst_RDR_SFL900_V1.0
13 9. Waveforms and Testing Results 9.1 Drain Voltage and Current Sense Startup --(Red Vcomp,Blue Vout,Yellow Vcs,Green Vds) Fig.2 Startup 90VAC, 42V load Fig.3 Startup 115VAC 42V load Fig.4 Startup 230VAC, 42V load Fig.5 Startup 264VAC 42V load 9.2 Drain Voltage and Current Sense Nomal Operation --(Red Vcomp,Blue Iout,Yellow Vcs,Green Vds) Fig.6 90VAC, 42V load Fig. 7 90VAC 42V load SiFirst Technology SiFirst_RDR_SFL900_V1.0
14 Fig.8 115VAC, 42V load Fig.9 115VAC, 42V load Fig VAC, 42V load Fig VAC, 42V load Fig VAC, 42V load Fig VAC, 42V load SiFirst Technology SiFirst_RDR_SFL900_V1.0
15 9.3 Ripple and Noise Input Voltage Ripple & Noise Ripple current Ripple Voltage Waveform 90VAC/60Hz 116mA 3.8V Fig VAC/60Hz 108mA 3.5V Fig VAC/50Hz 118mA 3.8V Fig VAC/50Hz 124mA 3.8V Fig.17 Note: Ripple and noise are measured at cable end with a 0.1uF/50V ceramic cap connected in parallel with a 47uF/50V aluminum electrolytic cap. The oscilloscope bandwidth is limited to 20MHz. Fig.14 Ripple & 42V load (Blue Iout,Red Vout) Fig.15 Ripple & 115VAC/60Hz, 42V load (Blue Iout,Red Vout) Fig.16 Ripple & 42V load (Blue Iout,Red Vout) Fig.17 Ripple & 264VAC/50Hz, 42V load (Blue Iout,Red Vout) SiFirst Technology SiFirst_RDR_SFL900_V1.0
16 9.4 Output current overshoot Input Voltage Measure Data (%) SPEC Waveform 90VAC/60Hz 0 <5% Fig VAC/50Hz 0 <5% Fig.19 Fig.18 90VAC, 42V load (Blue Iout,Red Vout) Fig VAC, 42V load(blue Iout,Red Vout) 9.5 Max Mosfet Vds and second diode Vak Voltage Test Condition Max. Vds (V) Max. Vak(V) Remark Full load 264V/50hz Normal full 264V/50Hz Output 264V/50Hz Fig Fig Fig.22 Fig.20 Startup 264VAC, 42V load Fig.21 Normal 264VAC 42V load SiFirst Technology SiFirst_RDR_SFL900_V1.0
17 Fig.22 Output short 264VAC, 42V load Fig.23 Output short 264VAC, 42V load 10. Protections 10.1 Output Short Circuit Protection --(Red Vcomp,Blue Vcc,Yellow Vcs,Green Vds) Fig.24 output short 90VAC, 42V load Fig.25 output short 90VAC 42V load Fig.26 output short 264VAC, 42V load Fig.27 output short 264VAC 42V load SiFirst Technology SiFirst_RDR_SFL900_V1.0
18 10.2 Over Voltage Protection -- Blue Vout,Yellow Vdem Input Voltage Vout (V) Vdem (V) Waveform 90VAC/60Hz Fig VAC/50Hz Fig.30 Fig.28 90VAC no load Fig.29 90VAC no load Fig VAC no load Fig VAC no load SiFirst Technology SiFirst_RDR_SFL900_V1.0
19 11. EMI Testing Results 11.1 Conduction EMI Test Full Load Report VIN=230V/50Hz, Line (Blue QP yellow--av ) VIN=230V/50Hz, Neutral (Blue QP yellow--av ) FCC 15 Class Full Load Report VIN=120V/60Hz, Line (QP ) VIN=120V/60Hz, Line (AV ) SiFirst Technology SiFirst_RDR_SFL900_V1.0
20 VIN=120V/60Hz, Neutral (QP ) VIN=120V/60Hz, Neutral (AV ) 11.2 Radiation EMI Test Radiation EN55022 CLASS full load report VIN=230V/50Hz, Vertical VIN=230V/50Hz, Horizontal SiFirst Technology SiFirst_RDR_SFL900_V1.0
21 Radiation FCC 15 CLASS full load report VIN=120V/60Hz, Vertical VIN=120V/60Hz, Horizontal IMPORTANT NOTICE SiFirst Technology Nanhai, Ltd (SiFirst) reserves the right to make corrections, modifications, enhancements, improvements and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. SiFirst Technology SiFirst_RDR_SFL900_V1.0
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