A Novel Single-Switch High Conversion Ratio DC--DC Converter

Transcription

1 A Novel Single-Switch High Conversion Ratio DC--DC Converter Ching-Shan Leu and Shun-Yuan Wu Power Conversion Laboratory Department of Electrical Engineering National Taiwan University of Science and Technology Taipei, Taiwan, R.O.C 106 mail.ntust.edu.tw Abstract By employing the coupled-inductor technique to the two cascaded boost converters, a single-switch high conversion ratio DC--DC converter is proposed. Unlike its predecessor, high voltage gain can be obtained without operating at extreme duty cycle. In addition to the operating principles and the analysis, a 100 khz 36-75V DC input, 400V/40W converter is implemented and tested. The 91.% maximum efficiency can be achieved under high-line 85% full load operation condition. operation of the converter can be divided into two stages within one full switching cycle: Index Terms boost, DC-DC, high voltage gain ratio I. INTRODUCTION High step-up DC-DC converters are necessary in low input-voltage to high output-voltage power conversion applications. By employing the traditional boost converter with extreme duty cycle operation, the voltage gain approximates six times its applied voltage due to the losses of the parasitic components. However, at least ten times voltage gain is needed in many applications such as the frontend stage of the renewable energy systems, the DC bus of the telecom power systems and high intensity discharge (HID) lamp ballast for the automobile headlights. To obtain the required voltage gain, several topologies have been proposed by employing the coupled inductor or the cascaded booster converter techniques [1]-[1]. However, the former technique induces high voltage stress caused by the leakage inductance of the coupled inductor. On the contrary, the latter suffers from the synchronizing of the two power switches [9]. By merging both the coupled inductor and the cascaded techniques, a novel single-switch high conversion ratio DC--DC converter is thus proposed to alleviate these problems. In addition to the analysis and circuit principles, the circuit is implemented and tested to demonstrate its feasibility. II. ANALYSIS AND CIRCUIT OPERATION The circuit diagram and the key waveforms of the proposed converter are shown in Fig. 1 and Fig., respectively. It consists a coupled-inductor with two windings, L1 and L, with N ()N:N1 turns-ratio, one switch S1, three diodes D1, D, D3, one inductor, and two output capacitors, C1 and C. To simplify the analysis of the proposed converter, the capacitors, C1 and C, are assumed to be sufficiently large that the voltages can be assumed to be constant. Figures 3(a) and 3(b) illustrate the equivalent circuits during the switch-on and the switch-off period, respectively. The Fig. 1. Circuit diagram of the proposed converter. Fig. Key waveforms of the proposed converter. [T0-T1]: When the switch S1 is turned on at T0, the diode D1 starts to conduct. Inductor L1 and are charged by and Vc1, respectively. In addition to charging the inductor, the voltage across the capacitor C1 provides power to the output load via the capacitor C. [T1-T0]: When the switch S1 is turned off at T1, the diode D1 is reverse-biased and the current of the IL1 and 1097

2 I flows through the diode D and D3 to charge the capacitor C1 and C, respectively. In addition to charging capacitors C1 and C, the current I provides the output load current Io and the current I L1 flows through the coupled inductor L1, L is decreased with a slope of (Vc1-)/(L1+L) to charge the capacitor C1. The ideal voltage gain verse the duty cycle is plotted with N as the running parameter as shown in Fig. 4. With a higher turns-ratio, N4, the voltage gain be up to 0 by employing the proposed converter with 0.6 duty cycle. D N1 N L C1 C L1 D1 D3 +Vo Q R Gnd (a) N1 L1 N L D D1 Q D3 C1 C +Vo R Fig. 4 Ideal voltage gain verse duty cycle of the proposed converter In practically, the inductor winding resistor, the forward voltage drop of the diode V F, and MOSFET s turn-on resistor r DS are considered in deriving the voltage gain as follows: Including the non-ideal components, the circuit diagram is shown in Fig.5. Gnd (b) Fig. 3 Equivalent circuit stages of the proposed converter. From the voltage-second balance of the inductor L1,, the equations can be obtained as: VC1 D+ 0 (1 + N) (1) V D+ ( Vo V ) 0 () C1 C1 The voltage gains of (V C1 /V i ) and (Vo/V C1 ) can be derived as Eq. (3) and Eq. (4), respectively. V V C1 1 i + ND 1 D VO 1 (4) VC1 1 D Therefore, the voltage gain of the proposed converter is derived as shown in Eq. (5). VO 1+ ND (5) V i (3) Fig. 5 Circuit diagram of the proposed converter including inductor resistors (r e1,r e and r e3), MOSFET s turn-on resistor, r DS, and the diode forward voltage drop (V F1,V F and V F). The Ampere-Second balance of the capacitors, C1 and C, are expressed as Eq. (6) and Eq. (7), respectively. ( I + Io) D ( I I + I ) 0 (6) C Io D ( I Io) 0 (7) Therefore, I, I can be expressed as: Io I (8) 1098

3 Io I (9) 1 L1I 1 1 L1( N + 1) I (10) Both terms in Eq. (10) represent the inductor energy under the switch S1 turned on-off transition. As a result, I 1 is expressed as ( N + 1) Io I1 ( N + 1) I (11) From Voltage-Second balance of the inductors, L1 and L, Eq. (1) and Eq. (13) can be obtained, respectively [ ] V I r ( I + I ) r D ( V V + I r + V ) 0 c1 e3 1 ds o c1 e3 F3 [( 1 e1 ( 1 ) ds F1) ] [ V ] + I ( r + r ) + V I r I + I r V D C1 e1 e F 1+ N (1 D) Therefore, the voltage gain Vo/n can be derived as Vo 1 IL 3 re3 Dr DS( I1+ IL 3) V F3 n n [ ] (1 DV ) F + I( re 1+ re ) ( N+ 1) DV [ F1 + rds( I1+ IL 3) + I1 re 1] + ( N+ 1) (1 D) (1) (13) (14) According to Eq. (14), the voltage gain verse duty cycle by using the turns-ratio of the coupled-inductor as the running parameter is plotted as shown in Fig. 6. Fig. 6 Voltage gain verse duty cycle by using the turns ratio as the running parameter. As illustrated, the maximum voltage gain is highly constrained by the ESRs of the inductors. However, to obtain a higher voltage gain without operating at extreme duty cycle, higher turns-ratio of coupled inductor is recommended. III. EXPERIMENT RESULTS A V input, 400 V output and 40 W output power converter is implemented. It operates at 100 KHz. The turns-ratio of the coupled-inductor, L:L1, is set to 1:1. Figures 7(a) and 7(b) show the oscillograms of the key waveforms of the proposed converter under low-line full-load and high-line light-load operating conditions, respectively. First, a high voltage gain (400/3611) of the converter is verified as shown in channel 1 in each diagram. 400V output voltage is obtained with 0.6 duty cycle under lowline operating condition. As shown in channel in each diagram, the voltage waveform across the switch is spike free and clamped to 400V, Vo. The voltage stress of the diodes can be read from channels 5, 6 and 9 of each diagram. As shown, D3 is clamped the output voltage, Vo. On the contrary, D1 and D are dependent on the operating conditions and are always smaller than the output voltage. As shown in channel 11, the Vc1 is clamped to 160V and 00V for the low-line full load and high-line light load conditions, respectively. Finally, the measured efficiency of the proposed converter under different line and load operating conditions is plotted in Fig. 8. As shown, the maximum efficiency 91.% occurs at 75V input 400V/0.5A output operating condition IV. CONCLUSIONS By employing the coupled-inductor and cascadedconverter techniques, a single-switch high conversion ratio converter is proposed. A higher voltage gain is verified from the experimental results under low input voltage 36V operating condition. A 400V output-voltage is obtained with 0.6 duty cycle. Moreover, the voltage waveforms of the switch S1 and diodes D1, D, D3 are all well clamped without voltage spike. A maximum 91.% efficiency is achieved under high-line and 85% load operating condition. It can be further improved by paralleling the MOSFET and/or employing the MOSFET to replace the diodes. Therefore, the proposed converter is favorable for the high conversion ratio power conversion applications. 1099

4 (1)V GS 0V/div (1)V GS 0V/div ()V DS ()V DS (3)I Q (3)I Q (4)I in (4)I in (5)V D1 (6)V D (7)I D1 (8)I D (9)V D3 (10)I D3 (11)V C1 00V/div (1) V o (5)V D1 (6)V D (7)I D1 (8)I D (9)V D3 (10)I D3 A/div (11)V C1 00V/div (1) V o (a) (b) Fig. 7. Oscillograms of the converter under (a) low-line full-load, and (b) high-line light-load operating conditions. Fig. 8. Measured efficiency of the power stage of the proposed converter REFERENCE [1] K.C. Tseng, T.J. Liang. Novel High Efficiency Step-up Converter IEE Proc. Electr. Power Applications, Vol 151, No, March 004, pp [] R.J. Wai, R.Y. Duan. High Step-up Converter with Coupled-Inductor IEEE Transactions on Power Electronics, Vol 0, No 5, September 005. pp [3] T.J. Liang, KC Tseng. Analysis of Integrated Boost-Flyback Step-up Converter IEE Proc. Electr. Power Applications, Vol 15, No, March 005, pp [4] Q. Zhao, F.C. Lee. High Efficiency, High Step-up DC-DC Converters IEEE Transactions on Power Electronics, Vol 18, No 1, January 003.pp [5] Q Zhao, Fengfeng Tao, and Fred C. Lee, A Front-End DC-DC Converter for Network Server Applications, in Proc. IEEE-PESC 01, pp [6] R.J. Wai, C.Y. Lin, R.Y. Duan, and Y.R. Chang High-Efficiency DC- DC Converter with High Voltage Gain and Reduced Switch Stress IEEE Transactions [7] L. Huber and M. M. Jovanovic, A design approach for server power supplies for networking, in Proc. IEEE Appl. Power Electron. Conf., 1100

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