THE USE OF power-factor preregulators (PFP s), also

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1 IEEE TRANSACTIONS ON POWER ELECTRONICS, OL. 12, NO. 6, NOEMBER Improving Dynamic Response of Power-Factor Preregulators by Using Two-Input High-Efficient Postregulators Javier Sebastián, Member, IEEE, Pedro J. illegas, Member, IEEE, Fernando Nuño, Member, IEEE, Oscar García, and Jaime Arau, Member, IEEE Abstract A new method to improve dynamic response of power-factor preregulators (PFP s) is developed in this paper. The method is based on the use of a very high efficient postregulator with two inputs instead of only one. This two-input postregulator exhibits very high efficiency due to the fact that only a part of the total power undergoes a power-conversion process. They need two-output PFP s at their inputs, which can be easily obtained in PFP s with transformers or with two PFP s working in parallel. Index Terms Fast regulation of the output voltage, highquality rectifiers, postregulators, power-factor correctors. I. INTRODUCTION THE USE OF power-factor preregulators (PFP s), also called power-factor correctors (PFC s) [1], [2], is the usual way to get a high power factor on off-line switching power supplies. When a PFP is made up of only one stage, the static output voltage is accurately regulated, whereas the output voltage usually exhibits poor dynamic regulation. This is due to the fact that a low-pass filter must be included in the output voltage feedback loop when the bulk capacitor used to remove the low-frequency ripple ( Hz) is placed at the output [2]. To improve dynamic regulation and to decrease bulk capacitor size, a first option [see Fig. 1] is to connect a second dc-to-dc converter in cascade with the first converter, with the bulk capacitor placed in between. These two stages in cascade mean a complicated power circuit, which is an interesting option only in medium-power applications (more than 1 kw). Some efforts have been reported to simplify the two-cascade stage system [3] [5]. They are based on the use of only one stage [see Fig. 1] with a single transistor. Due to the fact that the power is handled twice for the stage, the transistor current and voltage stress are very high, therefore, converter Manuscript received April 19, 1996; revised March 4, This work was supported by ALCATEL Telecom Research Division, Energy Department. Recommended by Associate Editor, K. D. T. Ngo. J. Sebastián, P. J. illegas, and F. Nuño are with the Departamento de Ingeniería Eléctrica, Electrónica, de Computadores y Sistemas de la Universidad de Oviedo, Gijón, Spain. O. García is with the Departamento de Automática, Ingeniería Electrónica e Informática Industrial de la Universidad Politécnica de Madrid, Madrid, Spain. J. Arau is with the Centro Nacional de Investigación y Desarrollo Tecnológico (CENIDET), Departamento de Electrónica Interior Internado Palmira, CP Cuernavaca, Morelos, Mexico. Publisher Item Identifier S (97)08085-X. efficiency is relatively low. In [6], another one-stage option is presented in which a four-transistor topology handles the power. In this topology, the power recycled (which undergoes two power-conversion processes) is typically about 60% of the full derived power [see Fig. 1(c)]. Other topologies [7] with several switches (four or five, some of them with high voltage stress) are based on two stages in which the first stage handles the total input power, whereas the second one only handles 32% of the input power [see Fig. 1(d)]. So, only 32% of the input power needs to be processed twice. These topologies are called parallel power-factor correctors (PPFC s). Other types of PPFC s with only one power stage, which processes both input power and the extra 32% power, have also been developed [8, Fig. 1(e)]. In this case, two implementations have been presented: one for low-power applications (up to 200 W) based on a Flyback topology with two additional switches, all of them high-voltage switches, and the other for medium-power applications (more than several hundred watts), based on a full-bridge Boost converter with one additional switch. Good efficiency is achieved in this case, but the topology is very complex, and the control unit in this case and in the former is not standard, but complex. In this paper, we introduce an alternative method to reduce the bulk capacitor size and to improve the dynamic response of PFP s with almost no efficiency penalty. This method is based on the use of a very highly efficient postregulator [9]. In this case [see Fig. 1(f)], the first stage is a two-output PFP, which supplies two poorly regulated (from the dynamic point of view) outputs instead of one, both at relatively close voltages, and [see Fig. 2]. This last condition can be easily accomplished in any PFP with a transformer and, even in PFP s with no transformer, some alternatives can be found (two main PFP s with their inputs connected in parallel, for example). The proposed postregulator is connected at the outputs of this two-output main PFP, as can be seen in Fig. 2, therefore, it is a two-input dc-to-dc postregulator. In this postregulator, a considerable fraction of the input power (typically 85% 90%) comes up to the load with no power processing [9], therefore, with efficiency 1, whereas the remaining power undergoes a power processing based on a Buck topology, therefore, with a typical efficiency of 80% 95%. As a result, the overall efficiency of the postregulator is very high (typically 97% 99%), therefore, the complete first-stage postregulator efficiency is very near to that of the first stage /97$ IEEE

2 1008 IEEE TRANSACTIONS ON POWER ELECTRONICS, OL. 12, NO. 6, NOEMBER 1997 (c) (d) (e) (f) Fig. 1. Different options to improve both dynamic response and bulk capacitor size in PFP. Two stages in cascade. Solutions reported in [3] [5]. (c) Solution reported in [6]. (d) Solution reported in [7] (PPFC). (e) Solution reported in [8] (PPFC as well). (f) Solution proposed in this paper. Fig. 2 shows the basic block diagram of the proposed PFP. The control circuitry corresponding to each converter (first-stage and postregulator) is completely independent and therefore can be based on standard controllers. Fig. 2 (d) shows several possible implementations of the proposed PFP. The first two are based on converters with a transformer (Flyback and push pull Boost), whereas the third is based on two Boost converters with their inputs connected in parallel. The same postregulator is used in the three implementations: the two-input Buck (TIBuck) converter (see Fig. 3). The properties of this converter have been studied in [9] and are summarized in Table I, where they are compared with those of a conventional Buck postregulator. The main advantages of this type of postregulator are 1) low-voltage stress across diode and transistor; 2) standard controller; 3) small inductor (in comparison with a Buck postregulator); 4) low price; 5) small overall converter size; 6) very high efficiency. The price to pay for these advantages is as follows. 1) The range of output voltages is limited by the input voltages (see Table I). 2) A short-circuit protection cannot be implemented in this postregulator and must be implemented in the main two-output PFP [first stage in Fig. 2]. II. USING TIBUCK POSTREGULATOR IN POWER-FACTOR CORRECTION As we have explained in Section I, a TIBuck postregulator can be connected at the outputs of any topology of a two-

3 SEBASTIÁN et al.: IMPROING RESPONSE OF POWER-FACTOR PREREGULATORS 1009 (c) Fig. 2. Proposed PFP. Basic block diagram. Flyback + TIBuck. (c) Push pull Boost + TIBuck. (d) Parallel Boost + TIBuck. (d) output PFP (see Fig. 2) in order to decrease the size of the bulk capacitor and to improve the dynamic response with almost no efficiency penalty in either. Fig. 4 shows the main power and voltage waveforms in a typical two-stage PFP [Fig. 4] and in the proposed twostage PFP based on a two-input postregulator [Fig. 4]. In the

4 1010 IEEE TRANSACTIONS ON POWER ELECTRONICS, OL. 12, NO. 6, NOEMBER 1997 Fig. 3. TIBuck postregulator. Fig. 5. Power processing in a TIBuck postregulator working as a PFP and its equivalent circuit from [9]. Fig. 4. Main voltage and power waveforms in a standard two-stage PFP and in the proposed structure. Fig. 6. Input and output voltages in a TIBuck postregulator. former structure, only one bulk capacitor is used. Moreover, the second converter handles all the output power, therefore, the total power is handled twice. It should be noted that whichever of the two structures is chosen, the bulk capacitor or capacitors used are much smaller than the one used in a typical one-stage PFP to obtain the same line-frequency ripple at the output, due to postregulator operation. In the latter structure, two bulk capacitors (instead of one) must be used. The total size of these capacitors are similar to the one in a typical two-stage PFP structure and, therefore, much smaller than the size of the capacitor in one-stage PFP s. However, complete PFP efficiency is almost the same as for one-stage PFP s. This is because the second stage has very high efficiency since it is based on a TIBuck, therefore, the postregulator does not process the total output power [9]. Fig. 5 shows the main power and voltage waveforms in a TIBuck working as a second stage in a PFP (top) at its equivalent circuit obtained after the topological transformations explained in [9] (bottom). Thus, the input power is divided into two similar values, and (top), which are filtered by the two-input bulk capacitors. The voltages across both capacitors exhibit a relatively high line-frequency ripple ( Hz), which is removed by the postregulator. However, from the circuit shown at the bottom part of Fig. 5, the input power can be divided into two values and The latter of these values is the part of the total power, which does not undergo power processing and, therefore, comes up to the load with efficiency This power is and will be very close to the total output power if and are very close. The rest of the input power is processed with efficiency, which reaches the typical values of any real dc-to-dc converter operating from an input voltage to obtain an output voltage The closer input and output voltages are in this dc-to-dc converter, the higher is (as in any Buck dc-to-dc converter). Therefore, the conditions to achieve high efficiency in the total converter are that should be as high as possible and that and should be as close as possible. In conclusion, both conditions can be summarized as follows: the closer and are, the higher the efficiency is. (1)

5 SEBASTIÁN et al.: IMPROING RESPONSE OF POWER-FACTOR PREREGULATORS 1011 Fig. 7. TIBuck postregulator used in a distributed power-supply system. Fig. 8. Static and dynamic equivalent circuit for a TIBuck and its transfer function. However, the choice of and must be made bearing in mind the TIBuck regulation range. Fig. 6 shows how voltages and must be chosen, that is, satisfying in any possible condition, even under transient steps in the load and always taking into account the voltage ripple in the bulk capacitors and These capacitors can be designed with a considerable voltage ripple, therefore, their values will be considerably lower as well. However, the lower and are (therefore, the higher the ripple is), the higher the difference must be chosen to satisfy It should be noted that to get the best postregulator behavior (efficiency, stress in semiconductors, inductor size, etc.), and must be chosen as close as possible [9]. So, a tradeoff must be established between, on the one hand, bulk capacitor sizes and transient response and, on the other hand, postregulator size and efficiency. Thus, a good compromise between them is to choose in the range of and In this case, reductions in the bulk capacitor of 25 times and postregulator efficiencies around 97% 98% can be easily achieved. The estimation of the voltage ripple across both bulk capacitors is an important task. When these capacitors have been designed for relatively high ripple levels, an accurate Fig. 9. Block diagram of the TIBuck control. oltage mode. oltage mode and feedforward. determination of this ripple is not very easy. However, sometimes the ripple across the bulk capacitor is relatively small in comparison with the dc level, and the use of a TIBuck can be very interesting in order to obtain an especially low ripple at the output (less than 1%). A very good example of this case could be a PFP with a 48- battery connected at its output, following the typical structure of a distributed power system (see Fig. 7). In such cases, the ripples across and can be approached taking into account that the average value of the input currents and are and that the peak value of ripple across each capacitor can also be approached as in any PFP [10] (2) (3) (4) (5) where and are both peak ripples and is times line frequency. To reduce the voltage ripple across the output capacitor, the feedback control loop of the TIBuck postregulator must be

6 1012 IEEE TRANSACTIONS ON POWER ELECTRONICS, OL. 12, NO. 6, NOEMBER 1997 TABLE I optimized in order to obtain as high a crossover frequency as possible. For this purpose, its ac small-signal model must be known [9] (see Fig. 8). Moreover, the typical control scheme given in Fig. 9 (voltage mode without feedforward) can be modified to include feedforward control, as is given in Fig. 9. The study of this type of control can be easily carried out by perturbing the dc voltage conversion ratio (see Table I) where quantities with hats are the perturbed ones and quantities in capitals are their static values. To cancel the influence of and in by variations of, these variations must be chosen as follows: (6) Fig. 10. Feedforward implementation. Moreover, the pulse-width modulation (PWM) equation is where is the valley-to-peak value of the PWM ramp and is the error amplifier output voltage. Perturbing (8), we obtain In feedforward control, the value of necessary to cancel (7) should be obtained without variations of, at least under ideal conditions. Therefore, (9) becomes (7) (8) (9) (10) and from (7) and (10) we obtain the way in which the valleyto-peak value of the ramp must be changed (11) Fig. 10 shows a practical implementation of this type of control. Resistor and must be chosen as follows: where (12) (13) is the switching period of the controller (usually ) and are two coupling capacitors. III. EXPERIMENTAL RESULTS Two PFP prototypes with two TIBuck postregulators have been built and tested. Their characteristics are as follows. A. Prototype 1 This prototype consists of two standard Boost converters and a TIBuck postregulator. Both Boost converters have the same input voltage, but slightly different outputs (see Fig. 11).

7 SEBASTIÁN et al.: IMPROING RESPONSE OF POWER-FACTOR PREREGULATORS 1013 Fig. 11. Prototype 1. Their main characteristics are rms khz A A. The TIBuck postregulator used in this prototype is TIBuck 1 from [9], and it has the following characteristics: A khz mh (E30 3C80 Philips) nf (MKP) Although the input and output voltages in this postregulator are in the 400- range, both semiconductor devices ( and ) have been chosen with 100 maximum voltage, therefore, their conduction and switching losses are very low. The output power at full load is 380 W. It can be easily deduced from Fig. 5 and (1) that 340 W are passing directly with no power processing (efficiency 1) from the input to the output. The rest of the output power (40 W) comes up to the load with efficiency (Fig. 5). This is the efficiency, which can be measured in TIBuck 1 prototype when input and output voltages are modified as Fig. 5 shows, that is,,, and W. In these conditions, the measured efficiency is about which means that W, therefore, only 3 W have been lost. These 3 W are the total losses of TIBuck 1 as well. Therefore, total efficiency will be at full load. This efficiency agrees with the one measured in [9] for TIBuck 1. It should be noted that these efficiencies include the drive losses. Fig. 12 (c) shows postregulator input and output voltages. Thus, Fig. 12 shows both input voltages, whereas one input voltage and the output voltage have been given in Fig. 12, all of them to the same scale. On the other hand, this scale has been changed in Fig. 12(c) to show the output ripple. In order to show the bulk capacitor saving obtained using the proposed postregulator, the postregulator was removed and 225 W were supplied by only one output. In these conditions, a 470- F capacitor had to be used to obtain 0.53% voltage ripple at the output. On the other hand, with the postregulator and with both Boost converters working together, only two capacitors of 33 F allow us to obtain 0.26% voltage ripple. This ripple became 0.13% using feedforward control in the postregulator. Therefore, the same ripple could be obtained either using one (or two if the power was high enough) standard Boost converters with a total amount of 2000 F without the postregulator or using the proposed topology with feedforward control with a total amount of 70 F and reducing the PFP efficiency 1% 2%. It should be noted that this reduction in the total bulk capacitance (about 30 times) has been achieved with an efficiency penalty of 1% 2%. However, by changing the switching frequency and, therefore, the TIBuck output filter, both the above figures could be changed. Thus, the higher the switching frequency is, the higher the bandwidth can be and, therefore, the higher the total bulk capacitance reduction is. However, the higher the switching frequency is, the higher the switching losses are, and, therefore, the higher the efficiency penalty is. Therefore, a tradeoff between total bulk capacitance reduction and efficiency can be established in each case. Finally, Fig. 13 shows the transient response of the input and output when load is instantaneously changed from As this figure shows, the minimum value of (ripple transient response) is, higher than. In the same way, the maximum value of

8 1014 IEEE TRANSACTIONS ON POWER ELECTRONICS, OL. 12, NO. 6, NOEMBER 1997 (c) Fig. 12. oltages in prototype 1: input voltages, input and output voltages, and (c) input and output voltages (different scales). (which is not shown in Fig. 13) is than as well., lower B. Prototype 2 This prototype (see Fig. 14) consists of a two-output Flyback converter and a TIBuck postregulator. The Flyback converter has the following characteristics: (rms) khz A A. The TIBuck postregulator used in this prototype is TIBuck 2 from [9]. It was designed according to the following characteristics: A khz Fig. 13. Transient response in Prototype 1.

9 SEBASTIÁN et al.: IMPROING RESPONSE OF POWER-FACTOR PREREGULATORS 1015 Fig. 14. Prototype 2. Fig. 15. Overall Prototype 2 efficiency. H IRF T045 F Fig. 16. oltage ripple across bulk capacitor in Prototype 2 when d = 0:67: In this postregulator, the power passing directly (with no power processing) at full load is 188 W, whereas the total power at full load is 218 W. The rest of the power undergoes a power processing, whose efficiency is the same as TIBuck 2 s efficiency operating from and to obtain 7.5. This efficiency is (drive circuit included), lower than the one obtained for TIBuck 1 due to the fact that the converter is operating with lower voltage levels in this case. The output power is W, whereas the input power is W, and, therefore, the power losses are W, which are the power losses of the TIBuck 2 postregulator as well. Final TIBuck 2 efficiency will be %, which agrees with the efficiency measured in [9]. The overall efficiency of the complete converter (input rectifier Flyback TIBuck, including drive and control circuitry) is shown in Fig. 15. The voltage ripple in both bulk capacitors has been studied to verify (4) and (5); Fig. 16 shows theoretical and experimental results, using two capacitors of 1500 F/70 The line ripple obtained at the output is 9 12 times lower than at the inputs (as is given in Fig. 17) without feedforward and times lower with feedforward. To obtain the same line ripple at the output without using a postregulator, the bulk capacitor should be 53 mf [2] (instead of two capacitors of 1.5 mf). Therefore, the total capacitance used with TIBuck 2 is 18 times lower. The other important advantage is that the output exhibits very good dynamic regulation when the load changes. Fig. 17. Input and output voltage ripple waveforms in the TIBuck used in Prototype 2 (IO =2:5A). Fig. 18 shows the transient response when the output current is changed from A and vice versa. The characteristics of the step are: frequency: 0.5 Hz, duty cycle: 0.5, slew rate: 0.01 A/ s The feedback loop of the Flyback was optimized according to [10] to obtain high power factor (see Fig. 15). In these conditions, the transient response at the output is very slow, as Fig. 18 shows, whereas exhibits a very fast response, as Fig. 18 also shows. I. CONCLUSIONS Two-input postregulators are very interesting postregulators to be used with PFP s due to their inherent high efficiency. This very high efficiency is based on the fact that not all the postregulator input power undergoes a switching conversion, but only a part of it. The remainder of the power passes directly through the converter with no switching conversion

10 1016 IEEE TRANSACTIONS ON POWER ELECTRONICS, OL. 12, NO. 6, NOEMBER 1997 Fig. 18. Transient response in Prototype 2. Javier Sebastián (M 88) was born in Madrid, Spain, in He received the M.Sc. degree from the Polytechnical University of Madrid, Madrid, Spain, and the Ph.D. degree from the University of Oviedo, Gijón, Spain, in 1981 and 1985, respectively. He was an Assistant Professor at the Polytechnical University of Madrid in 1982 and the University of Oviedo from 1983 to 1986 and an Associate Professor at Oviedo University from 1987 to 1989 and at the Polytechnical University of Madrid from 1990 to Since 1992, he has been with the University of Oviedo, where he is currently a Professor. His research interests are switching-mode power supplies, resonant power conversion, converter modeling, and high power-factor rectifiers. process, therefore, with efficiency 1. The greater this power is in comparison with the total power, the greater the total efficiency is. The use of this type of postregulator to improve the dynamic response of a PFP has been analyzed in this paper. The improvement of the dynamic response is materialized in both lower bulk capacitor size and faster transient response when the load changes. The results obtained in two prototypes show that the same ripple can be obtained either with this postregulator or with times more bulk capacitor. The dynamic response has also been improved with this postregulator. Finally, it should be noted that all of these results have been obtained when the switching frequency was 100 khz and with an overall postregulator efficiency of 97% 99%. If switching frequency is increased, efficiency will decrease, but the postregulator bandwidth could be increased (by decreasing the output filter), therefore, dynamic response would improve (this means lower bulk capacitors and faster transient response). REFERENCES [1] R. J. Kocher and R. L. Steigerwald, An dc-to-dc converter with high quality input waveforms, IEEE Trans. Ind. Applicat., vol. IA-19, no. 4, pp , [2] L. H. Dixon, High power factor preregulators for off-line power supplies, in Unitrode Power Supply Design Seminar, 1988, pp [3] I. Takahashi and R. Y. Igarashi, A switching power supply of 99% Power factor by the dither rectifier, in Proc. Int. Telecommunications Energy Conf., 1991, pp [4] M. Madigan, R. Erickson, and E. Ismail, Integrated high quality rectifier-regulators, in Proc. IEEE PESC 92, pp [5] R. Redl, L. Balogh, and N. Sokal, A new family of single-stage isolated power-factor correctors with fast regulation of the output voltage, in Proc. IEEE PESC 94, pp [6] M. H. Kheraluwala, R. L. Steigerwald, and R. Gurumoorthy, A fastresponse high power factor converter with a single power stage, in Proc. IEEE PESC 91, pp [7] Y. Jiang, F. C. Lee, G. Hua, and W. Tang, A novel single-phase power factor correction scheme, in Proc. IEEE APEC 93, pp [8] Y. Jiang and F. C. Lee, Single-stage single-phase parallel power factor correction scheme, in Proc. IEEE PESC 94, pp [9] J. Sebastián, P. illegas, F. Nuño, and M. M a Hernando, ery efficient two-input DC-to-DC switching post-regulators, in Proc. IEEE PESC 96, pp [10] L. H. Dixon, High power factor switching preregulator design optimization, in Unitrode Power Supply Design Seminar, 1988, pp Pedro J. illegas (M 96) was born in Suances, Spain, in He received the M.Sc. degree in electrical engineering from the University of Oviedo, Gijón, Spain, in Since 1994, he has been an Assistant Professor at the University of Oviedo. His research interests are switching-mode power supplies, converter modeling, and high power-factor rectifiers. Fernando Nuño (M 95) was born in Pola de Siero, Spain, in He received the M.Sc. and Ph.D. degree in electrical engineering from the University of Oviedo, Gijón, in January 1988 and December 1991, respectively. From 1988 to 1993, he was an Assistant Professor at the University of Oviedo. Since May 1993, he has been an Associate Professor at the University of Oviedo. His research interests are switching-mode power supplies, resonant power conversion, modeling of magnetic devices, and high power-factor rectifiers. Oscar García was born in Madrid, Spain, in He received the M.Sc. degree from the Universidad Politécnica de Madrid, Madrid, in Since 1992, he has been an Assistant Professor of Power Electronics at the Polytechnical University of Madrid. His research interests are switchingmode power supplies and high power-factor ac/dc converters. Jaime Arau (M 91) was born in eracruz, México, in He received the B.Sc. degree in electronic engineering from the Instituto Tecnológico de Minatitlan, México, and the Ph.D. degree in electrical engineering from the Universidad Politécnica de Madrid, Spain, in 1982 and 1991, respectively. Currently, he is a Full-Time Professor at the Centro Nacional de Investigación y Desarrollo Tecnológico (CENIDET), where he reaches and conducts research in the power electronics area. His fields of interest are power-factor correction, softswitching techniques, electronics ballasts, and other topics related to power electronics. Dr. Arau was the Founding President of the Morelos Section Power Electronics Chapter, and he is currently serving as the PELS AdCom Region no. 9 (Latinoamérica) Liasion. He is also President of the Mexican Academy of Research in Electronic Engineering.