MAX11044/MAX11044B/MAX11045/ MAX11045B/MAX11046/MAX11046B/ MAX11054/MAX11055/MAX /6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs

Transcription

1 EVALUATION KIT AVAILABLE MAX1144/MAX1144B/MAX1145/ MAX1145B/MAX1146/MAX1146B/ MAX1154/MAX1155/MAX1156 General Description The MAX1144/MAX1144B/MAX1145/MAX1145B/ MAX1146/MAX1146B 16-bit and MAX1154/MAX1155/ MAX bit ADCs offer 4, 6, or 8 independent input channels. Featuring independent track and hold (T/H) and SAR circuitry, these parts provide simultaneous sampling at 25ksps for each channel. The MAX1144/MAX1144B/MAX1145/MAX1145B/ MAX1146/MAX1146B and MAX1154/MAX1155/ MAX1156 accept a ±5V input. All inputs are overrange protected with internal ±2mA input clamps providing overrange protection with a simple external resistor. Other features include a 4MHz T/H input bandwidth, internal clock, and internal or external reference. A 2MHz, bidirectional, parallel interface provides the conversion results and accepts digital configuration inputs. The MAX1144/MAX1144B/MAX1145/MAX1145B/ MAX1146/MAX1146B and MAX1154/MAX1155/ MAX1156 operate with a 4.75V to 5.25V analog supply and a separate flexible 2.7V to 5.25V digital supply for interfacing with the host without a level shifter. The MAX1144/ MAX1144B/MAX1145/MAX1145B/MAX1146/ MAX1146B are available in a 56-pin TQFN and 64-pin TQFP packages while the MAX1154/MAX1155/ MAX1156 are available in TQFP only and operate over the extended -4 C to +85 C temperature range. Applications Automatic Test Equipment Power-Factor Monitoring and Correction Power-Grid Protection Multiphase Motor Control Vibration and Waveform Analysis Ordering Information PART PIN-PACKAGE CHANNELS MAX1144ETN+ 56 TQFN-EP* 4 MAX1144ECB+ 64 TQFP-EP* 4 MAX1144BETN+ 56 TQFN-EP* 4 MAX1144BECB+ 64 TQFP-EP* 4 MAX1145ETN+ 56 TQFN-EP* 6 MAX1145ECB+ 64 TQFP-EP* 6 MAX1145BETN+ 56 TQFN-EP* 6 MAX1145BECB+ 64 TQFP-EP* 6 Ordering Information continued at end of data sheet. Note: All devices are specified over the -4 C to +85 C operating temperature range. +Denotes a lead(pb)-free/rohs-compliant package. *EP = Exposed pad. Pin Configurations appear at end of data sheet. Features 16-Bit ADC (MAX1144/MAX1144B/MAX1145/ MAX1145B/MAX1146/MAX1146B) and 14-Bit ADC (MAX1154/MAX1155/MAX1156) 8-Channel ADC (MAX1146/MAX1146B/MAX1156) 6-Channel ADC (MAX1145/MAX1145B/MAX1155) 4-Channel ADC (MAX1144/MAX1144B/MAX1154) Single Analog and Digital Supply High-Impedance Inputs Up to 1GΩ On-Chip T/H Circuit for Each Channel Fast 3µs Conversion Time High Throughput: 25ksps for Each Channel 16-Bit/14-Bit, High-Speed, Parallel Interface Internal Clocked Conversions 1ns Aperture Delay 1ps Channel-to-Channel T/H Matching Low Drift, Accurate 4.96V Internal Reference Providing an Input Range of ±5V External Reference Range of 3.V to 4.25V, Allowing Full-Scale Input Ranges of ±4.V to ±5.2V 56-Pin (8mm x 8mm) TQFN and 64-Pin (1mm x 1mm) TQFP Packages Evaluation Kit Available CH CH7 REFIO CLAMP S/H 16-/14-BIT ADC CLAMP S/H 16-/14-BIT ADC MAX1144/MAX1144B/ MAX1145/MAX1145B/ MAX1146/MAX1146B MAX1154/MAX1155/MAX1156 BANDGAP REFERENCE 1kΩ INT REF EXT REF Functional Diagram REF BUF *CONNECTED INTERNALLY TO ON THE TQFN PARTS 8 x 16-/14-BIT REGISTERS CONFIGURATION REGISTERS INTERFACE AND CONTROL BIDIRECTIONAL DRIVERS DVDD DB15** DB4 DB3/CR3 DB/CR WR RD CS CONVST SHDN EOC DGND **MAX1144/MAX1145/MAX1146 MAX1146/MAX1156 _SENSE* For pricing, delivery, and ordering information, please contact Maxim Direct at , or visit Maxim s website at ; Rev 6; 5/13

2 ABSOLUTE MAXIMUM RATINGS to...-.3v to +6V DVDD to and DGND...-.3V to +6V DGND to...-.3v to +.3V to...-.3v to +.3V CH CH7 to v to +7.5V REFIO, to...-.3v to the lower of (V +.3V) and +6V EOC, WR, RD, CS, CONVST to...-.3v to the lower of (V DVDD +.3V) and +6V DB DB15 to...-.3v to the lower of (V DVDD +.3V) and +6V Maximum Current into Any Pin Except, DVDD,, DGND...±5mA Continuous Power Dissipation 56-Pin TQFN (derate 47.6mW/ C above +7 C) mW 64-Pin TQFP (derate 43.5mW/ C above +7 C) mW Operating Temperature Range...-4 C to +85 C Junction Temperature C Storage Temperature Range C to +15 C Lead Temperature (soldering, 1s)...+3 C Soldering Temperature (reflow) C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (V = +4.75V to +5.25V, V DVDD = +2.7V to +5.25V, V = V = V DGND = V, V REFIO = internal reference, C = 4 x 33μF, C REFIO =.1μF, C = 4 x.1μf 1μF, C DVDD = 3 x.1μf 1μF; all digital inputs at DVDD or DGND, unless otherwise noted, f SAMPLE = 25ksps. T A = -4 C to +85 C, unless otherwise noted. Typical values are at.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS STATIC PERFORMANCE (Note 1) Resolution N MAX1144/MAX1145/MAX MAX1154/MAX1155/MAX Bits MAX1144/MAX1145/MAX ±.4 +2 Integral Nonlinearity INL MAX1154/MAX1155/MAX ± LSB MAX1144B/MAX1145B/MAX1146B Differential Nonlinearity DNL MAX1144/MAX1145/MAX ± MAX1154/MAX1155/MAX ± LSB MAX1144/MAX1144B/MAX1145/ 16 No Missing Codes MAX1145B/MAX1146/MAX1146B Bits MAX1154/MAX1155/MAX Offset Error ±.1 ±.15 %FSR Channel Offset Matching ±.1 ±.15 %FSR Offset Temperature Coefficient ±.8 μv/ C Gain Error ±.15 %FSR Positive Full-Scale Error ±.15 %FSR Negative Full-Scale Error ±.15 %FSR Positive Full-Scale Error Matching ±.1 %FSR Negative Full-Scale Error Matching ±.1 %FSR Channel Gain-Error Matching Between all channels ±.1 %FSR Gain Temperature Coefficient ±.5 ppm/ C DYNAMIC PERFORMANCE Signal-to-Noise Ratio SNR MAX1144/MAX1144B/ f IN = MAX1145/MAX1145B/ kHz, MAX1146/MAX1146B full-scale input M AX1154/M AX 1155/ M AX1156 db 2 Maxim Integrated

3 ELECTRICAL CHARACTERISTICS (continued) (V = +4.75V to +5.25V, V DVDD = +2.7V to +5.25V, V = V = V DGND = V, V REFIO = internal reference, C = 4 x 33μF, C REFIO =.1μF, C = 4 x.1μf 1μF, C DVDD = 3 x.1μf 1μF; all digital inputs at DVDD or DGND, unless otherwise noted, f SAMPLE = 25ksps. T A = -4 C to +85 C, unless otherwise noted. Typical values are at.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Signal-to-Noise and Distortion Ratio Spurious-Free Dynamic Range Total Harmonic Distortion SINAD SFDR THD f IN = 1kHz, full-scale input f IN = 1kHz, full-scale input f IN = 1kHz, full-scale input MAX 1144/ MAX1145/ MAX1146 MAX 1154/ MAX1155/ MAX1156 MAX1144B/MAX1145B/ MAX1146B MAX 1144/ MAX1145/ MAX1146 MAX 1154/ MAX1155/ MAX1156 MAX1144B/MAX1145B/ MAX1146B MAX 1144/ MAX1145/ MAX1146 MAX 1154/ MAX1155/ MAX1156 MAX1144B/MAX1145B/ MAX1146B Channel-to-Channel Crosstalk f IN = 6Hz, full scale and ground on adjacent channel (Note 2) db ANALOG INPUTS (CH CH7) Input Voltage Range (Note 3) ±1.22 x V REFIO V Input Leakage Current μa Input Capacitance 15 pf Input-Clamp Protection Current Each input simultaneously ma TRACK AND HOLD Throughput Rate Per channel 1 25 ksps Acquisition Time t ACQ 1 1 μs Full-Power Bandwidth -3dB point 4 -.1dB point >.2 MHz Aperture Delay 1 ns Aperture-Delay Matching 1 ps Aperture Jitter 5 ps RMS INTERNAL REFERENCE REFIO Voltage V REF V REFIO Temperature Coefficient ±5 ppm/ C EXTERNAL REFERENCE Input Current μa REF Voltage-Input Range V REF V REF Input Capacitance 15 pf -9 db db db Maxim Integrated 3

4 ELECTRICAL CHARACTERISTICS (continued) (V = +4.75V to +5.25V, V DVDD = +2.7V to +5.25V, V = V = V DGND = V, V REFIO = internal reference, C = 4 x 33µF, C REFIO =.1µF, C = 4 x.1µf 1µF, C DVDD = 3 x.1µf 1µF; all digital inputs at DVDD or DGND, unless otherwise noted, f SAMPLE = 25ksps. T A = -4 C to +85 C, unless otherwise noted. Typical values are at.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DIGITAL INPUTS (CR CR3, RD, WR, CS, CONVST) Input Voltage High V IH V DVDD = 2.7V to 5.25V 2 V Input Voltage Low V IL V DVDD = 2.7V to 5.25V.8 V Input Capacitance C IN 1 pf Input Current I IN V IN = V or V DVDD ±1 µa DIGITAL OUTPUTS (DB DB15, EOC) Output Voltage High V OH I SOURCE = 1.2mA V DVDD -.4 Output Voltage Low V OL I SINK = 1mA.25.4 V Three-State Leakage Current DB DB15, V RD V IH or V CS V IH 1 µa Three-State Output Capacitance DB DB15, V RD V IH or V CS V IH 15 pf Analog Supply Voltage V Digital Supply Voltage DVDD V Analog Supply Current I MAX1146/MAX1146B/MAX1156, V = 5V 48 MAX1145/MAX1145B/MAX1155, V = 5V 39 MAX1144/MAX1144B/MAX1154, V = 5V 3 V ma MAX1146/MAX1146B/MAX1156, V DVDD = 3.3V 7. Digital Supply Current (Note 9) I DVDD MAX1145/MAX1145B/MAX1155, V DVDD = 3.3V 6.5 ma MAX1144/MAX1144B/MAX1154, V DVDD = 3.3V 5.5 Shutdown Current I DVDD 1 I 1 µa Power-Supply Rejection PSR V = 4.9V to 5.1V (Note 5) MAX1144/MAX1144B/ MAX1145/MAX1145B/ MAX1146/MAX1146B MAX1154/MAX1155/ MAX1156 TIMING CHARACTERISTICS (Note 4) CONVST Rise to EOC t CON Conversion time (Note 6) 3 µs Acquisition Time t ACQ 1 1 µs CS Rise to CONVST Rise t Q Sample quiet time (Note 6) 5 ns CONVST Rise to EOC Rise t ns EOC Fall to CONVST Fall t 1 CONVST mode B = only (Note 7) ns CONVST Low Time t 2 CONVST mode B = 1 only 2 ns ±1 ±.25 LSB 4 Maxim Integrated

5 MAX1144/MAX1144B/MAX1145/MAX1145B/ ELECTRICAL CHARACTERISTICS (continued) (V = +4.75V to +5.25V, VDVDD = +2.7V to +5.25V, V = V = VDGND = V, VREFIO = internal reference, C = 4 x 33μF, CREFIO =.1μF, C = 4 x.1μf 1μF, CDVDD = 3 x.1μf 1μF; all digital inputs at DVDD or DGND, unless otherwise noted, fsample = 25ksps. TA = -4 C to +85 C, unless otherwise noted. Typical values are at TA = +25 C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS CS Fall to WR Fall t3 WR Low Time t4 2 ns CS Rise to WR Rise t5 ns Input Data Setup Time t6 1 ns Input Data Hold Time t7 1 ns ns ns CS Fall to RD Fall t8 RD Low Time t9 3 ns RD Rise to CS Rise t1 ns RD High Time t11 1 RD Fall to Data Valid t12 RD Rise to Data Hold Time t13 ns 35 (Note 7) ns 5 ns See the Definitions section at the end of the data sheet. Tested with alternating channels modulated at full scale and ground. See the Input Range and Protection section for more details. CLOAD = 3pF on DB DB15 and EOC. Inputs (CH CH7) alternate between full scale and zero scale. fconv = 25ksps. All data is read out. Note 5: Defined as the change in positive full scale caused by a ±2% variation in the nominal supply voltage. Note 6: It is recommended that RD, WR, and CS are kept high for the quiet time (tq) and conversion time (tcon). Note 7: Guaranteed by design. Note 1: Note 2: Note 3: Note 4: Typical Operating Characteristics (V = 5V, VDVDD = 3.3V, TA = +25 C, fsample = 25ksps, internal reference, unless otherwise noted.) INTEGRAL NONLINEARITY vs. CODE (B-GRADE) INL (LSB) INL (LSB) V = 5.25V VDVDD = 3.3V fsample = 25ksps TA = +25 C V = 4.96V 64 HITS PER CODE V = 5.25V VDVDD = 3.3V fsample = 25ksps TA = +25 C V = 4.96V 64 HITS PER CODE V = 5.25V VDVDD = 3.3V fsample = 25ksps TA = +25 C V = 4.96V 64 HITS PER CODE OUTPUT CODE (DECIMAL) Maxim Integrated OUTPUT CODE (DECIMAL) DNL (LSB) 1.6 MAX1144 toc1a MAX1144 toc1 2. DIFFERENTIAL NONLINEARITY vs. CODE (A-GRADE) MAX1144 toc2 INTEGRAL NONLINEARITY vs. CODE (A-GRADE) OUTPUT CODE (DECIMAL) 5

6 Typical Operating Characteristics (continued) (V = 5V, V DVDD = 3.3V,, f SAMPLE = 25ksps, internal reference, unless otherwise noted.) DIFFERENTIAL NONLINEARITY vs. CODE (B-GRADE) MAX1144 toc2a INL AND DNL vs. ANALOG SUPPLY VOLTAGE (MAX114_) 1..6 MAX INL MAX1144 toc INL AND DNL vs. TEMPERATURE (MAX114_) MAX INL MAX1144 toc4 DNL (LSB) OUTPUT CODE (DECIMAL) V = 5.25V V DVDD = 3.3V f SAMPLE = 25ksps V = 4.96V 64 HITS PER CODE INL AND DNL (LSB) MAX DNL MIN INL MIN DNL V (V) V DVDD = 3.3V f SAMPLE = 25ksps V = 4.96V INL AND DNL (LSB).5 MIN INL -.5 V = 5.V MIN DNL V -1. DVDD = 3.3V f SAMPLE = 25ksps V = 4.96V TEMPERATURE ( C) MAX DNL I (ma) ANALOG SUPPLY CURRENT vs. SUPPLY VOLTAGE MAX1146 STATIC MAX1145 STATIC MAX1146 CONVERTING MAX1145 CONVERTING MAX1144 CONVERTING MAX1144 STATIC V (V) f SAMPLE = 25ksps MAX1144 toc5 I (ma) ANALOG SUPPLY CURRENT vs. TEMPERATURE MAX1146 STATIC MAX1145 STATIC MAX1146 CONVERTING MAX1145 CONVERTING MAX1144 CONVERTING MAX1144 STATIC TEMPERATURE ( C) V = 5.V f SAMPLE = 25ksps MAX1144 toc6 IDVDD (ma) DIGITAL SUPPLY CURRENT vs. SUPPLY VOLTAGE f SAMPLE = 25ksps MAX1146 CONVERTING MAX1144 CONVERTING MAX1145 CONVERTING MAX1144/MAX1145/MAX1146 STATIC V DVDD (V) MAX1144 toc7 6 Maxim Integrated

7 Typical Operating Characteristics (continued) (V = 5V, V DVDD = 3.3V,, f SAMPLE = 25ksps, internal reference, unless otherwise noted.) IDVDD (ma) DIGITAL SUPPLY CURRENT vs. TEMPERATURE MAX1145 CONVERTING V DVDD = 3.3V f SAMPLE = 25ksps C DBxx = 15pF MAX1146 CONVERTING MAX1144 CONVERTING MAX1144/MAX1145/MAX1146 STATIC MAX1144 toc8 SHUTDOWN CURRENT (μa) ANALOG AND DIGITAL SHUTDOWN CURRENT vs. TEMPERATURE I I DVDD V = 5.V V DVDD = 3.3V MAX1144 toc9 SHUTDOWN CURRENT (μa) ANALOG AND DIGITAL SHUTDOWN CURRENT vs. SUPPLY VOLTAGE I DVDD I MAX1144 toc9a TEMPERATURE ( C) TEMPERATURE ( C) V OR V DVDD (V) VREF (V) INTERNAL REFERENCE VOLTAGES vs. SUPPLY VOLTAGE V MAX196 toc1 VREFIO (V) INTERNAL REFERENCE VOLTAGE vs. TEMPERATURE UPPER TYPICAL LIMIT V = 5.V MAX196 toc V REFIO LOWER TYPICAL LIMIT V (V) TEMPERATURE ( C).1.6 OFFSET ERROR AND OFFSET ERROR MATCHING vs. SUPPLY VOLTAGE f SAMPLE = 25ksps V = 4.96V MAX1144 toc OFFSET ERROR AND OFFSET ERROR MATCHING vs. TEMPERATURE f SAMPLE = 25ksps V = 5.V V REFIO = 4.96V MAX1144 toc13 ERRORS (%FS) OFFSET ERROR MATCHING OFFSET ERROR ERRORS (%FS) OFFSET ERROR MATCHING OFFSET ERROR V (V) TEMPERATURE ( C) Maxim Integrated 7

8 Typical Operating Characteristics (continued) (V = 5V, V DVDD = 3.3V,, f SAMPLE = 25ksps, internal reference, unless otherwise noted.) ERRORS (%FS) GAIN ERROR AND GAIN ERROR MATCHING vs. SUPPLY VOLTAGE f SAMPLE = 25ksps V = 4.96V GAIN ERROR GAIN ERROR MATCHING MAX1144 toc14 ERRORS (%FS) GAIN ERROR AND GAIN ERROR MATCHING vs. TEMPERATURE f SAMPLE = 25ksps V = 5.V V REFIO = 4.96V GAIN ERROR GAIN ERROR MATCHING MAX1144 toc15 MAGNITUDE (db) FFT PLOT (A-GRADE) f IN = 1kHz f SAMPLE = 25ksps V = 5.V SNR = 92.3dB SINAD = 92.dB THD = -14dB SFDR = 15.7dB MAX1144 toc V (V) TEMPERATURE ( C) FREQUENCY (khz) MAGNITUDE (db) FFT PLOT (B-GRADE) f IN = 1kHz f SAMPLE = 25ksps V = 5.V SNR = 92.3dB SINAD = 88.8dB THD = -91.3dB SFDR = 91.4dB MAX1144 toc16a MAGNITUDE (db) TWO-TONE IMD PLOT (MAX114_) f IN1 = 9838Hz f IN2 = 1235Hz f SAMPLE = 25ksps V = 5.V V = 4.96V V IN = -.1dBFS MAX1144 toc17 SNR AND SINAD (db) SIGNAL-TO-NOISE RATIO AND SIGNAL-TO-NOISE AND DISTORTION RATIO vs. TEMPERATURE (MAX114_) f IN = 1kHz f SAMPLE = 25ksps V = 5.V V = 4.96V V IN = -.25dB FROM FS SINAD SNR MAX1144 toc FREQUENCY (khz) THD (db) TOTAL HARMONIC DISTORTION vs. TEMPERATURE (MAX114_) f IN = 1kHz f SAMPLE = 25ksps V = 5.V V = 4.96V V IN = -.25dB FROM FS TEMPERATURE ( C) FREQUENCY (khz) MAX1144 toc19 SNR AND SINAD (db) TEMPERATURE ( C) SNR AND SINAD vs. ANALOG SUPPLY VOLTAGE (MAX114_) f IN = 1kHz f SAMPLE = 25ksps V = 4.96V V IN = -.25dB FROM FS V (V) SNR SINAD MAX1144 toc2 8 Maxim Integrated

9 Typical Operating Characteristics (continued) (V = 5V, V DVDD = 3.3V,, f SAMPLE = 25ksps, internal reference, unless otherwise noted.) THD (db) THD vs. ANALOG SUPPLY VOLTAGE (MAX114_) f IN = 1kHz f SAMPLE = 25ksps V = 4.96V V IN = -.25dB FROM FS V (V) MAX1144 toc21 SINAD (db) SIGNAL-TO-NOISE AND DISTORTION RATIO vs. FREQUENCY (MAX114_) f SAMPLE = 25ksps V = 5.V V = 4.96V V IN = -.25dB from FS FREQUENCY (khz) MAX1144 toc22 THD (db) THD vs. INPUT FREQUENCY (MAX114_) f SAMPLE = 25ksps V = 5.V V = 4.96V V IN = -.25dB from FS FREQUENCY (khz) MAX1144 toc23 CROSSTALK (db) CROSSTALK vs. FREQUENCY f IN = 6Hz f SAMPLE = 25ksps V = 5.V V = 4.96V V IN = -.25dB FROM FS INACTIVE CHANNEL AT MAX1144 toc24 NUMBER OF OCCURANCES 2, 15, 1, 5, OUTPUT NOISE HISTOGRAM WITH INPUT CONNECTED TO (MAX114_) V CH_ = V V = 5.V V = 4.96V f SAMPLE = 25ksps MAX1144 toc25 CONVERSION TIME (μs) FREQUENCY (khz) CONVERSION TIME vs. ANALOG SUPPLY VOLATAGE MAX1144 toc26 CONVERSION TIME (μs) OUTPUT CODE (DECIMAL) CONVERSION TIME vs. TEMPERATURE V = 5.V MAX1144 toc V (V) TEMPERATURE ( C) Maxim Integrated 9

10 MAX1144/ MAX1144B (TQFN-EP) PIN MAX1145/ MAX1145B (TQFN-EP) MAX1146/ MAX1146B (TQFN-EP) NAME FUNCTION Pin Description DB13 16-Bit Parallel Data Bus Digital Output Bit DB12 16-Bit Parallel Data Bus Digital Output Bit DB11 16-Bit Parallel Data Bus Digital Output Bit DB1 16-Bit Parallel Data Bus Digital Output Bit DB9 16-Bit Parallel Data Bus Digital Output Bit DB8 16-Bit Parallel Data Bus Digital Output Bit 8 7, 21, 5 7, 21, 5 7, 21, 5 DGND Digital Ground 8, 2, 51 8, 2, 51 8, 2, 51 DVDD Digital Supply. Bypass to DGND with a.1μf capacitor at each DVDD input DB7 16-Bit Parallel Data Bus Digital Output Bit DB6 16-Bit Parallel Data Bus Digital Output Bit DB5 16-Bit Parallel Data Bus Digital Output Bit DB4 16-Bit Parallel Data Bus Digital Output Bit DB3/CR3 16-Bit Parallel Data Bus Digital Output Bit 3/ Configuration Register Input Bit DB2/CR2 16-Bit Parallel Data Bus Digital Output Bit 2/ Configuration Register Input Bit DB1/CR1 16-Bit Parallel Data Bus Digital Output Bit 1/ Configuration Register Input Bit DB/CR 16-Bit Parallel Data Bus Digital Output Bit / Configuration Register Input Bit EOC Active-Low End-of-Conversion Output. EOC goes low when conversion is completed. EOC goes high when a conversion is initiated CONVST SHDN 22, 28, 35, 43, 49 23, 27, 33, 38, 44, 48 22, 28, 35, 43, 49 23, 27, 33, 38, 44, 48 22, 28, 35, 43, 49 23, 27, 33, 38, 44, 48 C onver t S tar t Inp ut. Ri si ng ed g e of C ON V S T end s sam p l e and star ts a conver si on on the cap tur ed sam p l e. The AD C i s i n acq ui si ti on m od e w hen C ON V S T i s l ow and C ON V S T m od e =. Shutdown Input. If SHDN is held high, the entire device will enter and stay in a low-current state. Contents of the configuration register are not lost when in the shutdown mode. Refer ence Buffer D ecoup l i ng. C onnect al l RD C outp uts tog ether. Byp ass to AG N D w i th at l east an 8μF total cap aci tance. S ee the Layout, Gr ound i ng, and Byp assi ng secti on. Signal Ground. Connect all and inputs together on PCB. 1 Maxim Integrated

11 Pin Description (continued) MAX1144/ MAX1144B (TQFN-EP) MAX1145/ MAX1145B (TQFN-EP) MAX1146/ MAX1146B (TQFN-EP) NAME FUNCTION 24, 3, 41, 47 24, 3, 41, 47 24, 3, 41, 47 Analog Supply Input. Bypass to with a.1μf capacitor at each input. 25, 31, 4, 46 25, 31, 4, 46 25, 31, 4, 46 Analog Ground. Connect all inputs together CH Channel Analog Input CH1 Channel 1 Analog Input CH2 Channel 2 Analog Input CH3 Channel 3 Analog Input REFIO External Reference Input/Internal Reference Output. Place a.1μf capacitor from REFIO to CH4 Channel 4 Analog Input CH5 Channel 5 Analog Input 42 CH6 Channel 6 Analog Input 45 CH7 Channel 7 Analog Input WR Active-Low Write Input. Drive WR low to write to the ADC. Configuration registers are loaded on the rising edge of WR CS RD Active-Low Chip-Select Input. Drive CS low when reading from or writing to the ADC. Active-Low Read Input. Drive RD low to read from the ADC. Each rising edge of RD advances the channel output on the data bus DB15 16-Bit Parallel Data Bus Digital Output Bit DB14 16-Bit Parallel Data Bus Digital Output Bit 14 26, 29, 42, 45 26, 45 I.C. Internally Connected. Connect to. EP E xp osed P ad. Inter nal l y connected to AG N D. C onnect to a l ar g e g r ound p l ane to m axi m i ze ther m al p er for m ance. N ot i ntend ed as an el ectr i cal connecti on p oi nt. Maxim Integrated 11

12 MAX1144/ MAX1144B (TQFP-EP) PIN MAX1145/ MAX1145B (TQFP-EP) MAX1146/ MAX1146B (TQFP-EP) NAME Pin Description (continued) FUNCTION DB14 16-Bit Parallel Data Bus Digital Output Bit DB13 16-Bit Parallel Data Bus Digital Output Bit DB12 16-Bit Parallel Data Bus Digital Output Bit DB11 16-Bit Parallel Data Bus Digital Output Bit DB1 16-Bit Parallel Data Bus Digital Output Bit DB9 16-Bit Parallel Data Bus Digital Output Bit DB8 16-Bit Parallel Data Bus Digital Output Bit 8 8, 22, 59 8, 22, 59 8, 22, 59 DGND Digital Ground 9, 21, 6 9, 21, 6 9, 21, 6 DVDD Digital Supply. Bypass to DGND with a.1μf capacitor at each DVDD input DB7 16-Bit Parallel Data Bus Digital Output Bit DB6 16-Bit Parallel Data Bus Digital Output Bit DB5 16-Bit Parallel Data Bus Digital Output Bit DB4 16-Bit Parallel Data Bus Digital Output Bit DB3/CR3 16-Bit Parallel Data Bus Digital Output Bit 3/ Configuration Register Input Bit DB2/CR DB1/CR DB/CR EOC CONVST SHDN 23, 28, 32, 38, 43, 49, 53, 58 24, 29, 35, 46, 52, 57 25, 3, 36, 45, 51, 56 23, 28, 32, 38, 43, 49, 53, 58 24, 29, 35, 46, 52, 57 25, 3, 36, 45, 51, 56 23, 28, 32, 38, 43, 49, 53, 58 24, 29, 35, 46, 52, 57 25, 3, 36, 45, 51, Bit Parallel Data Bus Digital Output Bit 2/ Configuration Register Input Bit 2 16-Bit Parallel Data Bus Digital Output Bit 1/ Configuration Register Input Bit 1 16-Bit Parallel Data Bus Digital Output Bit / Configuration Register Input Bit Active-Low End-of-Conversion Output. EOC goes low when conversion is completed. EOC goes high when a conversion is initiated. C onver t S tar t Inp ut. Ri si ng ed g e of C ON V S T end s sam p l e and star ts a conver si on on the cap tur ed sam p l e. The AD C i s i n acq ui si ti on m od e w hen C ON V S T i s l ow and C ON V S T m od e =. Shutdown Input. If SHDN is held high, the entire device will enter and stay in a low-current state. Contents of the configuration register are not lost when in the shutdown mode. Signal Ground. Connect all and inputs together on PCB. Analog Supply Input. Bypass to with a.1μf capacitor at each input. Analog Ground. Connect all inputs together. 12 Maxim Integrated

13 Pin Description (continued) MAX1144/ MAX1144B (TQFP-EP) MAX1145/ MAX1145B (TQFP-EP) MAX1146/ MAX1146B (TQFP-EP) NAME 26, 55 26, 55 26, 55 _SENSE FUNCTION Reference Buffer Sense Feedback. Connect to plane. 27, 33, 4, 48, 54 27, 33, 4, 48, 54 27, 33, 4, 48, CH Channel Analog Input CH1 Channel 1 Analog Input CH2 Channel 2 Analog Input CH3 Channel 3 Analog Input Refer ence Buffer D ecoup l i ng. C onnect al l RD C outp uts tog ether. Byp ass to AG N D w i th at l east an 8μF total cap aci tance. S ee the Layout, Gr ound i ng, and Byp assi ng secti on REFIO External Reference Input/Internal Reference Output. Place a.1μf capacitor from REFIO to CH4 Channel 4 Analog Input CH5 Channel 5 Analog Input 47 CH6 Channel 6 Analog Input 5 CH7 Channel 7 Analog Input WR Active-Low Write Input. Drive WR low to write to the ADC. Configuration registers are loaded on the rising edge of WR CS RD Active-Low Chip-Select Input. Drive CS low when reading from or writing to the ADC. Active-Low Read Input. Drive RD low to read from the ADC. Each rising edge of RD advances the channel output on the data bus DB15 16-Bit Parallel Data Bus Digital Output Bit 15 31, 34, 47, 5 31, 5 I.C. Internally Connected. Connect to. EP E xp osed P ad. Inter nal l y connected to AG N D. C onnect to a l ar g e g r ound p l ane to m axi m i ze ther m al p er for m ance. N ot i ntend ed as an el ectr i cal connecti on p oi nt. Maxim Integrated 13

14 MAX1154 (TQFP-EP) PIN MAX1155 (TQFP-EP) MAX1156 (TQFP-EP) NAME Pin Description (continued) FUNCTION DB12 14-Bit Parallel Data Bus Digital Output Bit DB11 14-Bit Parallel Data Bus Digital Output Bit DB1 14-Bit Parallel Data Bus Digital Output Bit DB9 14-Bit Parallel Data Bus Digital Output Bit DB8 14-Bit Parallel Data Bus Digital Output Bit DB7 14-Bit Parallel Data Bus Digital Output Bit DB6 14-Bit Parallel Data Bus Digital Output Bit 6 8, 22, 59 8, 22, 59 8, 22, 59 DGND Digital Ground 9, 21, 6 9, 21, 6 9, 21, 6 DVDD Digital Supply. Bypass to DGND with a.1μf capacitor at each DVDD input DB5 14-Bit Parallel Data Bus Digital Output Bit DB4 14-Bit Parallel Data Bus Digital Output Bit DB3 14-Bit Parallel Data Bus Digital Output Bit DB2 14-Bit Parallel Data Bus Digital Output Bit DB1/CR3 14-Bit Parallel Data Bus Digital Output Bit 1/ Configuration Register Input Bit DB/CR2 14-Bit Parallel Data Bus Digital Output Bit / Configuration Register Input Bit CR1 Configuration Register Input Bit CR Configuration Register Input Bit EOC Active-Low End-of-Conversion Output. EOC goes low when conversion is completed. EOC goes high when a conversion is initiated CONVST SHDN C onver t S tar t Inp ut. Ri si ng ed g e of C ON V S T end s sam p l e and star ts a conver si on on the cap tur ed sam p l e. The AD C i s i n acq ui si ti on m od e w hen C ON V S T i s l ow and C ON V S T m od e =. Shutdown Input. If SHDN is held high, the entire device will enter and stay in a low-current state. Contents of the configuration register are not lost when in the shutdown mode. 23, 28, 32, 38, 43, 49, 53, 58 24, 29, 35, 46, 52, 57 25, 3, 36, 45, 51, 56 23, 28, 32, 38, 43, 49, 53, 58 24, 29, 35, 46, 52, 57 25, 3, 36, 45, 51, 56 23, 28, 32, 38, 43, 49, 53, 58 24, 29, 35, 46, 52, 57 25, 3, 36, 45, 51, 56 Signal Ground. Connect all and inputs together on PCB. Analog Supply Input. Bypass to with a.1μf capacitor at each input. Analog Ground. Connect all inputs together. 26, 55 26, 55 26, 55 _SENSE Refer ence Buffer S ense Feed b ack. C onnect to RD C p l ane. 14 Maxim Integrated

15 MAX1154 (TQFP-EP) 27, 33, 4, 48, 54 PIN MAX1155 (TQFP-EP) 27, 33, 4, 48, 54 MAX1156 (TQFP-EP) 27, 33, 4, 48, 54 NAME Pin Description (continued) FUNCTION Refer ence Buffer D ecoup l i ng. C onnect al l RD C outp uts tog ether. Byp ass to AG N D w i th at l east an 8μF total cap aci tance. S ee the Layout, Gr ound i ng, and Byp assi ng secti on CH Channel Analog Input CH1 Channel 1 Analog Input CH2 Channel 2 Analog Input CH3 Channel 3 Analog Input REFIO External Reference Input/Internal Reference Output. Place a.1μf capacitor from REFIO to CH4 Channel 4 Analog Input CH5 Channel 5 Analog Input 47 CH6 Channel 6 Analog Input 5 CH7 Channel 7 Analog Input WR Active-Low Write Input. Drive WR low to write to the ADC. Configuration registers are loaded on the rising edge of WR CS Active-Low Chip-Select Input. Drive CS low when reading from or writing to the ADC RD Acti ve- Low Read Inp ut. D r i ve RD l ow to r ead fr om the AD C. E ach r i si ng ed g e of RD ad vances the channel outp ut on the d ata b us DB13 14-Bit Parallel Data Bus Digital Output Bit 13 31, 34, 47, 5 31, 5 I.C. Internally Connected. Connect to. EP E xp osed P ad. Inter nal l y connected to AG N D. C onnect to a l ar g e g r ound p l ane to m axi m i ze ther m al p er for m ance. N ot i ntend ed as an el ectr i cal connecti on p oi nt. Detailed Description The MAX1144/MAX1144B/MAX1145/MAX1145B/ MAX1146/MAX1146B and MAX1154/ MAX1155/ MAX1156 are fast, low-power ADCs that combine 4, 6, or 8 independent ADC channels in a single IC. Each channel includes simultaneously sampling independent T/H circuitry that preserves relative phase information between inputs making the MAX1144/MAX1144B/MAX1145/ MAX1145B/MAX1146/MAX1146B and MAX1154/ MAX1155/MAX1156 ideal for motor control and power monitoring. The MAX1144/MAX1144B/MAX1145/ MAX1145B/MAX1146/MAX1146B and MAX1154/ MAX1155/MAX1156 are available with ±5V input ranges that feature ±2mA overrange, fault-tolerant inputs. The MAX1144/MAX1144B/MAX1145/MAX1145B/ Maxim Integrated MAX1146/MAX1146B and MAX1154/MAX1155/ MAX1156 operate with a single 4.75V to 5.25V supply. A separate 2.7V to 5.25V supply for digital circuitry makes the devices compatible with low-voltage processors. The MAX1144/MAX1144B/MAX1145/MAX1145B/ MAX1146/MAX1146B and MAX1154/MAX1155/ MAX1156 perform conversions for all channels in parallel by activating independent ADCs. Results are available through a high-speed, 2MHz, parallel data bus after a conversion time of 3μs following the end of a sample. The data bus is bidirectional and allows for easy programming of the configuration register. The MAX1144/MAX1144B/MAX1145/MAX1145B/ MAX1146/MAX1146B and MAX1154/MAX1155/ MAX1156 feature a reference buffer, which is driven by 15

16 an internal bandgap reference circuit (V REFIO = 4.96V). Drive REFIO with an external reference or bypass with.1μf capacitor to ground when using the internal reference. Analog Inputs Track and Hold (T/H) To preserve phase information across all channels, each input includes a dedicated T/H circuitry. The input tracking circuitry provides a 4MHz small-signal bandwidth, enabling the device to digitize high-speed transient events and measure periodic signals with bandwidths exceeding the ADC s sampling rate by using undersampling techniques. Use anti-alias filtering to avoid high-frequency signals being aliased into the frequency band of interest. Input Range and Protection The full-scale analog input voltage is a product of the reference voltage. For the MAX1144/MAX1144B/ MAX1145/MAX1145B/MAX1146/MAX1146B and MAX1154/MAX1155/MAX1156, the full-scale input is bipolar in the range of: 5 ±( VREFIO x ) When in external reference mode, drive VREFIO with a 3.V to 4.25V source, resulting in an input range of ±3.662V to ±5.188V, respectively. All analog inputs are fault-protected to up to ±2mA. The MAX1144/MAX1144B/MAX1145/MAX1145B/ MAX1146/MAX1146B and MAX1154/MAX1155/ MAX1156 include an input clamping circuit that activates when the input voltage at the analog input is above (V + 3mV) or below (V + 3mV). The clamp circuit remains high impedance while the input signal is within the range of ±V and draws little or almost no current. However, when the input signal exceeds ±V, the clamps begin to turn on and shunt current to/from the supply. Consequently, to obtain the highest accuracy, ensure that the input voltage does not exceed ±(V +.3V). To make use of the input clamps (see Figure 1), connect a resistor (R S ) between the analog input and the voltage source to limit the voltage at the analog input so that the fault current into the MAX1144/MAX1144B/ MAX1145/MAX1145B/MAX1146/MAX1146B and MAX1154/MAX1155/MAX1156 does not exceed ±2mA. Note that the voltage at the analog input pin limits to approximately 7V during a fault condition so the following equation can be used to calculate the value of RS: INPUT SIGNAL R S SOURCE PIN VOLTAGE CH CH7 CLAMP S/H 16-/14-BIT ADC CLAMP S/H 16-/14-BIT ADC 8 x 16-/14-BIT REGISTERS BIDIRECTIONAL DRIVERS DVDD DB15** DB4 DB3/CR3 DB/CR MAX1144/MAX1144B/ MAX1145/MAX1145B/ MAX1146/MAX1146B MAX1154/MAX1155/MAX1156 INT REF 1kΩ BANDGAP REFERENCE REF BUF CONFIGURATION REGISTERS INTERFACE AND CONTROL WR RD CS CONVST SHDN EOC DGND REFIO EXT REF _SENSE* Figure 1. Required Setup for Clamp Circuit *CONNECTED INTERNALLY ON THE TQFN PARTS TO **MAX1144/MAX1145/MAX1146 MAX1146/MAX Maxim Integrated

17 VFAULT_ MAX -7V RS = 2mA where VFAULT_MAX is the maximum voltage that the source produces during a fault condition. Figures 2 and 3 illustrate the clamp circuit voltage-current characteristics for a source impedance RS = 128Ω. While the input voltage is within the ±(V + 3mV) range, no current flows in the input clamps. Once the input voltage goes beyond this voltage range, the clamps turn on and limit the voltage at the input pin. Applications Information Digital Interface The bidirectional, parallel, digital interface, CR CR3, sets the 4-bit configuration register. This interface configures the following control signals: chip select (CS), read (RD), write (WR), end of conversion (EOC), and convert start (CONVST). Figures 6 and 7 and the Timing Characteristics in the Electrical Characteristics table show the operation of the interface. DB DB15/DB13 output the 16-/14-bit conversion result. All bits are high impedance when RD = 1 or CS = 1. CR3 (Int/Ext Reference) CR3 selects the internal or external reference. The POR default =. = internal reference, REFIO internally driven through a 1kΩ resistor, bypass with.1μf capacitor to. 1 = external reference, drive REFIO with a high-quality reference. CR2 (Output Data Format) CR2 selects the output data format. The POR default =. = offset binary. 1 = two s complement. CR1 must be set to. CR1 (Reserved) CR (CONVST Mode) CR selects the acquisition mode. The POR default =. = CONVST controls the acquisition and conversion. Drive CONVST low to start acquisition. The rising edge of CONVST begins the conversion. 1 = acquisition mode starts as soon as the previous conversion is complete. The rising edge of CONVST begins the conversion. Programming the Configuration Register To program the configuration register, bring the CS and WR low and apply the required configuration data on CR3 CR of the bus and then raise WR once to save changes. CAUTION: When the configuration register is not being programmed, the host driving CR3 CR must relinquish the bus when the conversion results of the ADC are being read! Table 1. Configuration Register CR3 CR2 CR1 CR Int/Ext Reference Output Data Format Must be set to CONVST Mode ICLAMP (ma) R S = 128Ω V = 5V AT CH_ INPUT AT SOURCE MAX1144 fig2 ICLAMP (ma) R S = 128Ω V = 5V AT SOURCE AT CH_ INPUT MAX1144 fig SIGNAL VOLTAGE AT SOURCE AND PIN (V) Figure 2. Input Clamp Characteristics SIGNAL VOLTAGE AT SOURCE AND PIN (V) Figure 3. Input Clamp Characteristics (Zoom In) Maxim Integrated 17

18 Starting a Conversion CONVST initiates conversions. The MAX1144/MAX1144B MAX1145/MAX1145B/MAX1146/MAX1146B and MAX1154/MAX1155/MAX1156 provide two acquisition modes set through the configuration register. Allow a quiet time (t Q ) of 5ns prior to the start of conversion to avoid any noise interference during readout or write operations from corrupting a sample. In default mode (CR = ), drive CONVST low to place the MAX1144/MAX1144B/MAX1145/MAX1145B/ MAX1146/MAX1146B and MAX1154/MAX1155/ MAX1156 into acquisition mode. All the input switches are closed and the internal T/H circuits track the respective input voltage. Keep the CONVST signal low for at least 1μs (t ACQ ) to enable proper settling of the sampled voltages. On the rising edge of CONVST, the switches are opened and the MAX1144/MAX1144B/MAX1145/MAX1145B/ MAX1146/MAX1146B and MAX1154/MAX1155/ MAX1156 begin the conversion on all the samples in parallel. EOC remains high until the conversion is completed. In the second mode (CR = 1), the MAX1144/ MAX1144B/MAX1145/MAX1145B/MAX1146/ MAX1146B and MAX1154/MAX1155/MAX1156 enter acquisition mode as soon as the previous conversion is completed. CONVST rising edge initiates the next sample and conversion sequence. CONVST needs to be low for at least 2ns to be valid. Provide adequate time for acquisition and the requisite quiet time in both modes to achieve accurate sampling and maximum performance of the MAX1144/ MAX1144B/MAX1145/MAX1145B/MAX1146/MAX1 146B and MAX1154/MAX1155/MAX1156. Reading Conversion Results The CS and RD are active-low, digital inputs that control the readout through the 16-/14-bit, parallel, 2MHz data bus (D D15/D13). After EOC transitions low, read the conversion data by driving CS and RD low. Each low period of RD presents the next channel s result. When CS or RD are high, the data bus is high impedance. CS may be driven high between individual channel readouts or left low during the entire 8-channel readout. Reference Internal Reference The MAX1144/MAX1144B/MAX1145/MAX1145B/ MAX1146/MAX1146B and MAX1154/MAX1155/ MAX1156 feature a precision, low-drift, internal bandgap reference. Bypass REFIO with a.1μf capacitor to to reduce noise. The REFIO output voltage may be used as a reference for other circuits. The output impedance of REFIO is 1kΩ. Drive only high impedance circuits or buffer externally when using REFIO to drive external circuitry. External Reference Set the configuration register to disable the internal reference and drive REFIO with a high-quality external reference. To avoid signal degradation, ensure that the integrated reference noise applied to REFIO is less than 1μV in the bandwidth of up to 5kHz. CS (USER SUPPLIED) t 5 CS (USER SUPPLIED) t 3 t 4 t 8 t 9 t 1 t 11 WR (USER SUPPLIED) t 7 RD (USER SUPPLIED) t 12 t 13 t 6 DB DB15/DB13 S n S n + 1 CR CR3 (USER SUPPLIED) CONFIGURATION REGISTER Figure 4. Programming Configuration-Register Timing Requirements Figure 5. Readout Timing Requirements 18 Maxim Integrated

19 SAMPLE t CON t ACQ CONVST t 1 EOC t O t Q CS RD DB DB15/DB13 S S 1 S 6 S 7 Figure 6. Conversion Timing Diagram (CR = ) SAMPLE t CON t ACQ CONVST t 2 EOC t O t Q CS RD DB DB15/DB13 S S 1 S 6 S 7 Figure 7. Conversion Timing Diagram (CR = 1) Maxim Integrated 19

20 Reference Buffer The MAX1144/MAX1144B/MAX1145/MAX1145B/ MAX1146/MAX1146B and MAX1154/MAX1155/ MAX1156 have a built-in reference buffer to provide a low-impedance reference source to the SAR converters. This buffer is used in both internal and external reference mode. The reference buffer output feeds five pins. The pins should be all connected V LSB = (1/4.96) x (V REF /65,536) together on the PCB. The reference buffer is externally compensated and requires at least 1μF on the node. For best performance, provide a total of at least 8μF on the outputs. Transfer Functions Figures 8 and 9 show the transfer functions for all the formats and devices. Code transitions occur halfway between successive-integer LSB values. V LSB = (1/4.96) x (V REF /65,536) 7FFF 7FFE +FS = 32,767 x V LSB FULL-SCALE TRANSITION FFFF FFFE +FS = 32,767 x V LSB FULL-SCALE TRANSITION OUTPUT CODE (hex) 1 FFFF FFFE -FS = -32,768 x V LSB V OUTPUT CODE = IN VLSB + 32,768 OUTPUT CODE (hex) FFF 7FFE -FS = -32,768 x V LSB V IN OUTPUT CODE = V LSB FS +FS -32,767.5 x V LSB +32,766.5 x V LSB INPUT VOLTAGE (LSB) Figure 8. Two s Complement Transfer Function for 16-Bit Devices -FS +FS -32,767.5 x V LSB +32,766.5 x V LSB INPUT VOLTAGE (LSB) Figure 9. Offset-Binary Transfer Function for 16-Bit Devices V LSB = (1/4.96) x (V REF /16,384) V LSB = (1/4.96) x (V REF /16,384) 1FFF 1FFE +FS = 8191 x V LSB FULL-SCALE TRANSITION 3FFF 3FFE +FS = 8191 x V LSB FULL-SCALE TRANSITION OUTPUT CODE (hex) 1 3FFF 3FFE -FS = x V LSB V OUTPUT CODE = IN VLSB OUTPUT CODE (hex) FFF 1FFE -FS = x V LSB V OUTPUT CODE = IN VLSB FS +FS x V LSB x V LSB INPUT VOLTAGE (LSB) Figure 8b. Two s Complement Transfer Function for 14-Bit Devices -FS +FS x V LSB x V LSB INPUT VOLTAGE (LSB) Figure 9b. Offset-Binary Transfer Function for 14-Bit Devices 2 Maxim Integrated

21 PHASE 1 VOLTAGE TRANSFORMER OPT ADC CURRENT TRANSFORMER OPT ADC VN ADC NEUTRAL IN ADC LOAD 1 MAX1146 MAX1146B MAX1156 LOAD 2 LOAD 3 I3 ADC PHASE 2 I2 V2 V3 ADC ADC ADC PHASE 3 Figure 1. Power-Grid Protection Maxim Integrated 21

22 DSP-BASED DIGITAL PROCESSING ENGINE IGBT CURRENT DRIVERS MAX1144 MAX1144B MAX1145 MAX1145B MAX1146 MAX1146B MAX1154 MAX1155 MAX /14-BIT ADC 16-/14-BIT ADC 16-/14-BIT ADC 16-/14-BIT ADC 16-/14-BIT ADC I PHASE1 I PHASE3 I PHASE2 3-PHASE ELECTRIC MOTOR POSITION ENCODER Figure 11. DSP Motor Control 22 Maxim Integrated

23 Layout, Grounding, and Bypassing For best performance use PCBs with ground planes. Ensure that digital and analog signal lines are separated from each other. Do not run analog and digital lines parallel to one another (especially clock lines), and avoid running digital lines underneath the ADC package. A single solid GND plane configuration with digital signals routed from one direction and analog signals from the other provides the best performance. Connect DGND,, and pins on the MAX1144/MAX1144B/MAX1145/ MAX1145B/MAX1146/MAX1146B and MAX1154/ MAX1155/MAX1156 to this ground plane. Keep the ground return to the power supply for this ground low impedance and as short as possible for noise-free operation. To achieve the highest performance, connect all the pins (22, 28, 35, 43, 49 for the TQFN package, or pins 27, 33, 4, 48, 54 for the TQFP package) to a local plane on the PCB. In addition, on the TQFP package, the _SENSE pins 26 and 55 should be directly connected to this plane as well. Bypass the outputs with a total of at least 8μF of capacitance. If two capacitors are used, place each as close as possible to pins 22 and 49 (TQFN) or pins 27 and 54 (TQFP). If four capacitors are used, place each as close as possible to pins 22, 28, 43, and 49 (TQFN) or pins 27, 33, 48, and 54 (TQFP). For example, two 47μF, 1V X5R capacitors in 121 case size can be placed as close as possible to pins 22 and 49 (TQFN package) will provide excellent performance. Alternatively, four 22μF, 1V X5R capacitors in 121 case size placed as close as possible to pins 22, 28, 43, and 49 (TQFN package) will also provide good performance. Ensure that each capacitor is connected directly into the plane with an independent via. If Y5U or Z5U ceramics are used, be aware of the highvoltage coefficient these capacitors exhibit and select higher voltage rating capacitors to ensure that at least 8μF of capacitance is on the plane when the plane is driven to 4.96V by the built-in reference buffer. For example, a 22μF X5R with a 1V rating is approximately 2μF at 4.96V, whereas, the same capacitor in Y5U ceramic is just 13μF. However, a Y5U 22μF capacitor with a 25V rating cap is approximately 2μF at 4.96V. Bypass and DVDD to the ground plane with.1μf ceramic chip capacitors on each pin as close as possible to the device to minimize parasitic inductance. Add at least one bulk 1μF decoupling capacitor to and DVDD per PCB. Interconnect all of the inputs and DVDD inputs using two solid power planes. For best performance, bring the power plane in on the analog interface side of the MAX1144/MAX1144B/MAX1145/MAX1145B/ MAX1146/MAX1146B and MAX1154/MAX1155/ MAX1156 and the DVDD power plane from the digital interface side of the device. For acquisition periods near minimum (1μs) use a 1nF CG ceramic chip capacitor between each of the channel inputs to the ground plane as close as possible to the MAX1144/MAX1144B/MAX1145/MAX1145B/ MAX1146/MAX1146B and MAX1154/MAX1155/ MAX1156. This capacitor reduces the inductance seen by the sampling circuitry and reduces the voltage transient seen by the input source circuit. Typical Application Circuits Power-Grid Protection Figure 1 shows a typical power-grid protection application. DSP Motor Control Figure 11 shows a typical DSP motor control application. Definitions Integral Nonlinearity (INL) INL is the deviation of the values on an actual transfer function from a straight line. For these devices, this straight line is a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. Differential Nonlinearity (DNL) DNL is the difference between an actual step width and the ideal value of 1 LSB. For these devices, the DNL of each digital output code is measured and the worst-case value is reported in the Electrical Characteristics table. A DNL error specification of greater than -1 LSB guarantees no missing codes and a monotonic transfer function. For example, -.9 LSB guarantees no missing code while -1.1 LSB results in missing code. Offset Error The offset error is defined as the input voltage required to cause the MAX1144/MAX1144B/MAX1145/ MAX1145B/MAX1146/MAX1146B digital output to be centered on code x8 (offset binary) or x (two s complement) and the MAX1154/MAX1155/ MAX1156 digital output to be centered on code x (offset binary) or x (two s complement). Ideally, this input voltage should be V with respect to. Gain Error Gain error is defined as the difference between the change in analog input voltage required to produce a top code transition minus a bottom code transition, subtracted from the ideal change in analog input voltage on (1/4.96) x V REF x (65,534/65,536) for 16-bit, or Maxim Integrated 23

24 (1/4.96) x V REF x (16,382/16,384) for 14-bit devices. For the MAX1144/MAX1144B/MAX1145/MAX1145B/ MAX1146/MAX1146B, top code transition is x7ffe to x7fff in two s complement mode and xfffe to xffff in offset binary mode. The bottom code transition is x8 and x81 in two s complement mode and x and x1 in offset binary mode. For the MAX1154/MAX1155/MAX1156, top code transition is x1ffe to x1fff in two s complement mode and x3ffe to x3fff in offset binary mode. The bottom code transition is x2 and x21 in two s complement mode and x and x1 in offset binary mode. For the MAX1144/MAX1144B/MAX1145/MAX1145B/ MAX1146/MAX1146B and MAX1154/MAX1155/ MAX1156, the analog input voltage to produce these code transitions is measured and the gain error is computed by subtracting (1/4.96) x V REF x (65,534/65,536) or (1/4.96) x VREF x (16,382/16,384), respectively from this measurement. Signal-to-Noise Ratio (SNR) For a waveform perfectly reconstructed from digital samples, SNR is the ratio of the full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization noise error only and results directly from the ADC s resolution (N bits): SNR = (6.2 x N )dB where N = 16/14 bits. In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter, etc. SNR is computed by taking the ratio of the RMS signal to the RMS noise, which includes all spectral components not including the fundamental, the first five harmonics, and the DC offset. Signal-to-Noise Plus Distortion (SINAD) SINAD is the ratio of the fundamental input frequency s RMS amplitude to the RMS equivalent of all the other ADC output signals: Signal SINAD db RMS ( ) = 1 log ( Noise + Distortion )RMS Effective Number of Bits (ENOB) The ENOB indicates the global accuracy of an ADC at a specific input frequency and sampling rate. An ideal ADC s error consists of quantization noise only. With an input range equal to the full-scale range of the ADC, calculate the ENOB as follows: ENOB = SINAD Total Harmonic Distortion (THD) THD is the ratio of the RMS of the first five harmonics of the input signal to the fundamental itself. This is: expressed as: V + V + V + V THD = log V 1 where V1 is the fundamental amplitude and V 2 through V 5 are the 2nd- through 5th-order harmonics. Spurious-Free Dynamic Range (SFDR) SFDR is the ratio of the RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next-largest frequency component. Aperture Delay Aperture delay (t AD ) is the time delay from the sampling clock edge to the instant when an actual sample is taken. Aperture Jitter Aperture jitter (taj) is the sample-to-sample variation in aperture delay. Channel-to-Channel Isolation Channel-to-channel isolation indicates how well each analog input is isolated from the other channels. Channel-to-channel isolation is measured by applying DC to channels 1 to 7, while a -.4dBFS sine wave at 6Hz is applied to channel. A 1ksps FFT is taken for channel and channel 1. Channel-to-channel isolation is expressed in db as the power ratio of the two 6Hz magnitudes. Small-Signal Bandwidth A small -2dBFS analog input signal is applied to an ADC in a manner that ensures that the signal s slew rate does not limit the ADC s performance. The input frequency is then swept up to the point where the amplitude of the digitized conversion result has decreased 3dB. Full-Power Bandwidth A large -.5dBFS analog input signal is applied to an ADC, and the input frequency is swept up to the point where the amplitude of the digitized conversion result has decreased by 3dB. This point is defined as fullpower input bandwidth frequency. 24 Maxim Integrated

25 Positive Full-Scale Error The error in the input voltage that causes the last code transition of FFFE to FFFF (hex) for 16-bit or 3FFE to 3FFF (hex) for 14-bit devices (in default offset binary mode) or 7FFE to 7FFF (hex) for 16-bit or 1FFE to 1FFF (hex) for 14- bit devices (in two s complement mode) from the ideal input voltage of 32,766.5 x (1/4.96) x (V REF /65,536) for 16-bit or x (1/4.96) x (V REF /16,384) for 14-bit devices after correction for offset error. Negative Full-Scale Error The error in the input voltage that causes the first code transition of to 1 (hex) (in default offset binary mode) or 8 to 81 (hex) for 16-bit or 2 to 21 (hex) for 14-bit devices (in two s complement mode) from the ideal input voltage of -32,767.5 x (1/4.96) x (V REF /65,536) for 16-bit or x (1/4.96) x (V REF /16,384) for 14-bit devices after correction for offset error. Pin Configurations TOP VIEW I.C. /CH7* DGND DVDD WR CS RD DB15 DB CH6*/CH5 /I.C. CH5*/CH4 /CH3 CH4*/CH3 /CH2 REFIO CH3*/CH2 /CH1 CH2*/CH1 /CH MAX1144 MAX1144B MAX1145 MAX1145B MAX1146 MAX1146B CH1*/CH /I.C. *EP CH*/I.C. DGND DVDD SHDN CONVST EOC DB/CR DB1/CR1 I.C. /CH7* _SENSE DGND DVDD WR CS RD DB CH6*/CH5 /I.C CH5*/CH4 /CH3 CH4*/CH3 /CH2 REFIO CH3*/CH2 /CH1 MAX1144 MAX1144B MAX1145 MAX1145B MAX1146 MAX1146B CH2*/CH1 /CH CH1*/CH /I.C. *EP CH*/I.C. _SENSE DGND DVDD SHDN CONVST EOC DB/CR DB13 DB12 DB11 DB1 DB9 DB8 DGND DVDD DB7 TQFN 8mm x 8mm DB6 DB5 DB4 CR3/DB3 CR2/DB2 MAX1144 MAX1145 *MAX DB14 DB13 DB12 DB11 DB1 DB9 DB8 DGND DVDD DB7 DB6 TQFP 1mm x 1mm DB5 DB4 CR3/DB CR2/DB2 CR1/DB1 Maxim Integrated 25