OPTICAL coherence tomography (OCT) is a noninvasive

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1 IEEE TRANSACTIONS ON BIOMEDICAL ENGINEERING, VOL. 55, NO. 2, FEBRUARY Analog CMOS Design for Optical Coherence Tomography Signal Detection and Processing Wei Xu, David L. Mathine, Member, IEEE, and Jennifer K. Barton*, Member, IEEE Abstract A CMOS circuit was designed and fabricated for optical coherence tomography (OCT) signal detection and processing. The circuit includes a photoreceiver, differential gain stage and lock-in amplifier based demodulator. The photoreceiver consists of a CMOS photodetector and low noise differential transimpedance amplifier which converts the optical interference signal into a voltage. The differential gain stage further amplifies the signal. The in-phase and quadrature channels of the lock-in amplifier each include an analog mixer and switched-capacitor low-pass filter with an external mixer reference signal. The interferogram envelope and phase can be extracted with this configuration, enabling Doppler OCT measurements. A sensitivity of 80 db is achieved with faithful reproduction of the interferometric signal envelope. A sample image of finger tip is presented. Index Terms Biomedical imaging, CMOS analog integrated circuits, optical tomography. I. INTRODUCTION OPTICAL coherence tomography (OCT) is a noninvasive biomedical imaging technique with micron-scale resolution and cross-sectional imaging capability [1]. OCT has developed rapidly in the past decade into a versatile imaging technology. OCT applications have been reported in Ophthalmology, Dermatology, Gastroenterology, Dentistry, Cardiology, and Urology, among other fields [2] [4]. Time domain OCT is based on low-coherence interferometry theory, with depth scanning enabled by changing the pathlength in the reference arm. Typically, a discrete photoreceiver, analog filtering and demodulation are used for signal detection and processing. This analog instrumentation may be bulky and expensive. Demodulation may also be performed digitally, but real-time operation generally requires a high-performance digital signal processor. Parallel OCT imaging systems can achieve high-quality, real-time imaging and potential elimination of lateral scanning. For such systems, analog demodulation with discrete components may become impractical, while high data rates make direct digitization and digital demodulation Manuscript received July 12, 2006; revised May 28, This work was supported in part by the National Institutes of Health under Grant R01 EB Asterisk indicates corresponding author. W. Xu was with the Department of Systems and Industrial Engineering, The University of Arizona, Tucson, AZ USA. He is now with the High Performance Analog Division, Texas Instruments, Tucson, AZ USA ( vpecxuwei@gmail.com). D. L. Mathine is with the the College of Optical Sciences and the Electrical and Computer Engineering Department, The University of Arizona, Tucson, AZ USA ( mathine@u.arizona.edu). *J. K. Barton is with the the Division of Biomedical Engineering, Electrical and Computer Engineering, and the College of Optical Sciences, 1657 East Helen Street, The University of Arizona, Tucson, AZ USA ( barton@u.arizona.edu). Digital Object Identifier /TBME difficult. Analog CMOS technology offers the advantages of low recurring cost, small size, and single chip integration for parallel channel acquisition. Previous CMOS designs for OCT system detection and processing have been reported by Kariya [5], Bourquin [6], and Egan [7]. Kariya [5] reported a single-channel analog CMOS circuit (with separate detector) that included phase locked loop, mixer and low-pass filter (LPF) for demodulation. Images of onion were obtained at approximately 7000 pixels/second with a reported sensitivity of db. Bourquin [6] reported a D smart detector array on an mm chip area for parallel OCT signal detection and demodulation. This chip enabled very rapid image acquisition, up to approximately pixels/second with a sensitivity of db. Egan [7] reported a full-field OCT system using a CMOS camera with integrated digital signal processing (DSP). This system performs 2-D lateral scanning electronically by addressing the pixels of the camera. Demodulation was performed digitally using the DSP of the camera. The speed of this system was pixels/second with an unreported sensitivity. In contrast to these previous approaches, this paper presents a unique single-channel OCT detection and demodulation design that provides high sensitivity. By incorporating low-noise differential photoreceiver design and lock-in amplifier (LIA) based demodulation, this chip achieves near -db sensitivity. Additionally, the LIA- based design supplies in-phase and quadrature components of the interferogram, thus enabling Doppler-based velocity measurements [8]. This design can be easily scaled up to 100 parallel channels on a mm CMOS chip. In a parallel implementation, an acquisition speed of more than pixels/second could be achieved. II. OCT SYSTEM The block diagram of an OCT system with the CMOS detection and demodulation circuitry is shown in Fig. 1. The OCT system light source is a superluminescent diode (SLD) (Superlum Diodes, Ltd., Russia) with 890-nm center wavelength and 90-nm full-width at half-maximum (FWHM) bandwidth. Light from the fiber-coupled source is divided by a 2 2 fiber coupler into reference and sample beams. A retroreflecting mirror mounted on a galvanometer performs 2 mm of pathlength modulation in the reference arm. Light reflected from the reference mirror and backscattered from a sample are combined by the fiber coupler and directed to the on-chip photodiode, with which the optical power is converted into photo current. Then the transimpedance amplifier (TIA) converts current into a voltage signal, which is demodulated by a LIA with a two channel (X, Y) chip output. Finally, the signal is sampled by the DAQ board and displayed on the computer screen /$ IEEE

2 486 IEEE TRANSACTIONS ON BIOMEDICAL ENGINEERING, VOL. 55, NO. 2, FEBRUARY 2008 Fig. 1. OCT system block diagram. TIA: Transimpedance amplifier. LIA: Lock-in amplifier. X and Y: In-phase and quadrature components of coherence signal harmonics. DAQ: Data acquisition board. PC: Personal computer. The photo current by [2] at the photodiode output is given Fig. 2. Block diagram of the CMOS chip, showing the major stages of the TIA, DGS, and mixer and LPF. where and are the intensity of light backscattered from the reference and sample, is the detector quantum efficiency, is the electronic charge, is the photon energy, is the pathlength difference between the sample backscatterer and the reference and is the light center wavelength. In (1), is the combined DC signal from reference and sample arms. The interferogram signal is an amplitude modulated (AM) signal obtained when the reference mirror scans at a constant speed, and contains the depth-dependent backscattering information. The relationship between the interferogram signal carrier frequency and light center wavelength is where is the mirror scanning speed. The relationship between the interferogram signal bandwidth and the optical wavelength FWHM bandwidth is Using (2) and (3), with our SLD source, the OCT interferogram signal has a carrier frequency of khz and a bandwidth of khz. The CMOS circuit was designed to detect this optical signal, then amplify and process the signal into a form suitable for analog to digital conversion. Digital processing is limited to logarithmic compression and conversion to image format. III. CIRCUIT PRINCIPLE A. Overview The overall CMOS chip block diagram is shown in Fig. 2. The on-chip photodiode linearly converts the optical power in the detection arm into photo current, then the photo current is converted into a voltage by the TIA. (1) (2) (3) The rest of the CMOS chip is a LIA [9]. The LIA has a differential gain stage (DGS) to further amplify the voltage signal. Two mixers and two LPFs are used to extract the in-phase (X) and quadrature (Y) components of the 100-kHz signal. Because the LPF is a switched-capacitor design, an on-chip clock circuit is needed to provide the nonoverlapping clock signal [10]. An external reference signal generator provides the necessary signals at 100 khz and 0, 180,90, and 270 phase (S1, S2, S3, and S4, respectively) for the mixers. A similar reference signal generator has been previously described [11]. The outputs of the chip are the X and Y components. A personal computer (PC) is used to digitally compute the fringe amplitude as. Besides the X and Y output and reference signals, there are three control signals for the TIA gain, high-pass filter corner frequency, and LPF corner frequency. Each section of the chip is described in more detail as follows. B. Photoreceiver The photoreceiver includes a buried double junction photodiode and a TIA, and has been described previously [12]. Briefly, the photoreceiver has a fully differential topology, low noise, large DC rejection capability, and a ten-fold variable gain range. The differential topology and low-noise TIA design gives the photoreceiver a high signal-to-noise ratio (SNR). The TIA DC rejection capability serves to suppress the unwanted DC photo current, which may be orders of magnitude greater than the interferometric signal. The high-pass corner frequency and TIA gain are tunable using an external voltage. The RC feedback in the TIA is designed to provide a first stage of out-of-band noise reduction. The gain varies by less than 2% over the band of interest ( khz) and the -db bandwidth ranges from 30 to 500 khz. C. Differential Gain Stage (DGS) The DGS is used to further amplify the TIA output signal and provide a common mode voltage required by the mixer input. The DGS employs a similar structure to the single clipping amplifier designed by Khorram et al. [13]. However, instead of using NMOS, PMOS is used to construct the circuit because

3 XU et al.: ANALOG CMOS DESIGN FOR OPTICAL COHERENCE TOMOGRAPHY SIGNAL DETECTION AND PROCESSING 487 Fig. 3. Analog mixer block diagram. the required mixer input common mode voltage is closer to the negative supply voltage. A symmetrical design is used for the differential pairs of input and load transistors, so that the DGS gain primarily depends upon the device width to length (W/L) ratio of the transistors. The gain was designed to be approximately 4.3. D. Mixer A LIA is created from two mixers and LPFs. The mixer shifts the 100-kHz modulated signal to a frequency band centered about DC [9]. The mixers have two differential inputs and one single-ended output. As shown in Fig. 2, the first mixer takes complementary square wave pair, 100 khz and 100 khz, as reference signals to extract the in-phase component from the DGS output. The second mixer takes phase-shifted complementary square wave pair, 100 khz and 100 khz as reference signals to extract the quadrature component. The mixer circuit diagram is shown in Fig. 3. The design is based on an analog Gilbert multiplier cell [14]. The mixer generates an output current that is proportional to the multiplication of the input and reference signals. The output current is then converted to a voltage using a TIA with a gain of 50-k. The overall transfer function of the mixer is where is the input signal, is complementary reference signal pair input. is the mixer gain determined by the Gilbert cell bias voltage, the W/L ratio of the transistors in the Gilbert multiplier cell and the 50-k resistance. E. Switched Capacitor LPF (SC-LPF) Two LPFs are used to remove the sum frequency (200 khz) of the mixer outputs while preserving the low-frequency difference signal. The LPF was designed as a third-order Butterworth LPF with a 5-kHz -db cutoff frequency and 18 db per octave slope. At this frequency range, an on-chip resistor-capacitor filter size was estimated to be about ten times of that of SC-LPF. In addition to smaller size, the SC-LPF has the advantages of high accuracy and a tunable cutoff frequency [10]. The designed SC-LPF transfer function is (4) (5) where, and. The transfer function of the SC-LPF has a single pole and a pair of complex conjugate poles realized by cascading a first-order SC-LPF and a low-q biquad design of a second-order SC-LPF [10]. A two-phase nonoverlapping clock [10] is required by the SC-LPF to switch transistors on and off for signal filtering. The signals are made nonoverlapping to prevent short circuits during the switching process. In the design, a Schmitt trigger based voltage controlled oscillator (VCO) [15] is used to provide a single-phase clock, which subsequently is used to generate a two-phase nonoverlapping signal by introducing a delay circuit into a cross-coupled RS flip-flop [16]. A simple on-chip first-order R-C LPF is used as a delay circuit. The first-order R-C LPF, composed of a 10-k poly-silicon resistor and a 2-pF poly-silicon capacitor, provides a nonoverlapping time of approximately 25 ns. A control voltage is used to tune the VCO frequency, which in turn controls the CLOCK frequency and the SC-LPF cutoff frequency. The optimum VCO frequency is approximately 250 khz from simulation. IV. MEASUREMENT All the subcomponents were tested separately before measuring the performance of the OCT system. The performance of the photoreceiver has been reported previously [12]. The photoreceiver was measured to have a ten-fold gain range (250-k to 2.5-M ), input referred current noise density of 2 pa/ at 100 khz, a gain of 1.1-M, bandwidth of 500 khz, and a greater than 55-dB DC rejection capability. The DGS gain was tested with a 100 khz sinusoidal signal input and calculated as the ratio of output to input peak to peak voltage. The measured gain of 4.5 matches well to the simulated value. The measured mixer gain is 14. When the CLOCK frequency was set to the simulated value of 250 khz, the SC-LPF -db cutoff frequency was measured to be 4.5 khz. The difference between simulated and measured cutoff frequency was due to CMOS process variations. However, because the cutoff frequency can be adjusted by the external LPF control voltage, process variations do not limit performance. A small control voltage change moved the measured cutoff frequency to 5 khz. If desired for larger bandwidth applications, the cutoff frequency could be set as large as 50 khz. Fig. 4 shows the measured and simulated SC-LPF transfer functions for a cutoff frequency of 5 khz. The measured slope is close to db per octave as expected. The CMOS detection and demodulation chip was integrated into the time domain OCT system. A mirror was placed in the sample arm and the reference mirror scanning speed was adjusted so that the carrier frequency was 100 khz. First, the OCT system optical output was connected to a photoreceiver (2001-FC, New Focus, San Jose, CA). The interferogram was converted to a voltage signal by 2001-FC, measured by an oscilloscope (Tektronix, Inc., Beaverton, OR, TDS224). The interferogram output was time based data, which was converted to a depth signal through multiplication by the mirror scanning speed. The resulting interferogram is shown as a solid line in Fig. 5. Subsequently, the CMOS chip was connected to the OCT system to perform signal sensing and processing. The

4 488 IEEE TRANSACTIONS ON BIOMEDICAL ENGINEERING, VOL. 55, NO. 2, FEBRUARY 2008 Fig. 4. Switched capacitor LPF transfer function. Diamonds: Measured data points. Solid line: Simulated response. Standard deviation of measured data is smaller than data point symbols. Fig. 6. Output of the CMOS circuit for a 036-dB reflector in the OCT system sample arm. Fig. 5. (Solid line) Measured OCT system interferogram from a mirror using a commercial photoreceiver and (dashed line) and measured envelope calculated from the CMOS chip outputs. envelope, which is shown as a dashed line in Fig. 5, was computed from the CMOS chip outputs as [9]. A large center peak with two small sidelobes appears in all signals, demonstrating that the interferogram envelope can be faithfully extracted by the CMOS chip. The FWHM of the interferogram was measured to be 5.6 m, whereas the FWHM of the envelope was 6.4 m, a 14% broadening of the interferogram, and consequently axial resolution. This resolution degradation is primarily due to slight attenuation of higher frequency components by the SC-LPF, and could be mitigated by increasing the cutoff frequency. The asymmetry in both the interferogram and envelope is due to optical dispersion mismatch between the sample and reference arms of the OCT interferometer. System sensitivity was measured by placing a 1.8 neutral density filter proximal to a mirror in the sample arm, to create a sample with -db reflectivity. The signal envelope is shown Fig. 7. OCT images of the volar surface of finger tip showing microscope slide (MS), sweat duct (SD), stratum corneum (SC), stratum spinosum (SS), and dermis (D), taken with (a) the CMOS circuit and (b) conventional analog demodulation circuitry. in Fig. 6, indicating that the sensitivity is near db. The theoretical sensitivity can be calculated using the equation for the SNR [17] where is the detector quantum efficiency, is the power on the sample, is the reflectivity of the sample, is Planck s constant, is the optical frequency, and NEB is the noise equivalent bandwidth. Setting as the limit of sensitivity, and using measures values of W, and khz, the system could detect a sample reflection of db in the shot noise limit. The difference between measured and theoretical sensitivity is due to electronic noise in the CMOS circuit. An image of the volar surface of a finger tip, Fig. 7(a), was taken to qualitatively demonstrate the CMOS-based OCT (6)

5 XU et al.: ANALOG CMOS DESIGN FOR OPTICAL COHERENCE TOMOGRAPHY SIGNAL DETECTION AND PROCESSING 489 system imaging quality. The finger was pressed against a microscope slide, with index matching performed by a drop of saline. The image dimensions are mm, pixels, acquisition time 52 s/pixel. Fig. 7(b) is an image of finger tip taken with the same OCT system but using conventional signal detection and processing components (New Focus 2001 optical receiver and Stanford Research Systems SRS 810 LIA). In both images, multiple sweat ducts and three skin layers are clearly visible, demonstrating excellent image quality with depth limited to the upper dermis as is typical for OCT systems operating in the 800-nm wavelength range. V. CONCLUSION A low-cost analog CMOS circuit was demonstrated that performs high-quality OCT system signal detection and demodulation. A sensitivity of db was achieved with low-power incident on the sample, a 20-dB improvement over previously published designs. The CMOS circuit was demonstrated in our relatively slow, lower center frequency and small bandwidth OCT system. However, because the transimpedance gain and filter cutoff frequencies are adjustable with external control voltages, this CMOS chip is a flexible choice for OCT systems with center frequencies up to 500 khz and bandwidths up to 50 khz. Future efforts will involve scale-up of the design to 100 parallel channels on a mm CMOS chip, enabling very rapid image acquisition. REFERENCES [1] D. Huang, E. A. Swanson, C. P. Lin, J. S. Schuman, W. G. Stinson, W. Chang, M. R. Hee, T. Flotte, K. Gregory, C. A. Puliafito, and J. G. Fujimoto, Optical coherence tomography, Science, pp , 1991, 254(5035). [2] B. E. Bouma and G. J. Tearney, Handbook of Optical Coherence Tomography. New York: Marcel Dekker, [3] A. F. Fercher, W. Drexler, C. K. Hitzenberger, and T. Lasser, Optical coherence tomography principles and applications, Rep. Progr. Phys., vol. 66, no. 2, pp , [4] J. M. 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Princeton, NJ: Princeton Applied Res. Corp., [10] P. E. Allen and D. R. Holberg, CMOS analog circuit design, 2nd ed. New York: Oxford Univ. Press, 2002, pp [11] W. Xu, G. T. Bonnema, K. W. Gossage, N. H. Wade, J. Medford, and J. K. Barton, Customized analog circuit design for fiber-based optical coherence microscopy, Rev. Sci. Instrum., vol. 77, no. 1, p , [12] W. Xu, D. L. Mathine, and J. K. Barton, A high-gain differential CMOS transimpedance amplifier with on-chip buried double junction photodiode, Electron. Lett., vol. 42, no. 14, pp , [13] S. Khorram, A. Rofougaran, and A. A. Abidi, A CMOS limiting amplifier and signal strength indicator, in Proc. IEEE Symp. VLSI Circuits, Tokyo, Japan, 1995, pp [14] P. R. Gray, P. J. Hurst, S. H. Lewis, and R. G. Meyer, Analysis and Design of Integrated Circuits, 4th ed. Hoboken, NJ: Wiley, 2001, pp [15] R. J. Baker, H. W. Li, and D. E. Boyce, CMOS Circuit Design, Layout and Simulation. New York: IEEE Press, 1997, pp , pp [16] N. Weste and K. Eshraghian, Principles of CMOS VLSI Design, 2nd ed. Boston, MA: Addison-Wesley, 2000, pp [17] E. A. Swanson, D. Huang, M. R. Hee, J. G. Fujimoto, C. P. Lin, and C. A. Puliafito, High-speed optical coherence domain reflectometry, Opt. Lett., vol. 17, pp , Wei Xu was born in Jiaojiang, Zhejiang, China. He received the B.S. and M.S. degrees in electrical engineering from Zhejiang University in 1996 and 1999, respectively, and the Ph.D. degree in systems and industrial engineering from the University of Arizona, Tucson, in His dissertation work involved the development of analog signal processing techniques for optical coherence imaging systems. He is currently an analog and mixed-signal IC Design Engineer in the High Performance Analog (HPA) Division, Texas Instruments, Tucson. David L. Mathine (S 82 M 83) was born in Lincoln, NE, on November 13, He received the B.S. and M.S. degrees in electrical engineering from the University of Nebraska, Lincoln, in 1981 and 1983, respectively, and the Ph.D. degree in electrical engineering from Purdue University, West Lafayette, IN, in His thesis work involved the optical study of materials by spectroscopic ellipsometry. His dissertation work involved the MBE growth and material characterization of the wide gap II-VI selinides and tellurides as well as the III-V antimonides and arsenides. Before receiving the Ph.D. degree, he hoined Rockwell International as a Device Engineer where he aided in the development of HgCdTe IR Focal Plane Arrays integrated with silicon circuitry. From 1991 to 1996, he was a Faculty Associate at Arizona State University, Tempe, where he was involved with the integration ov VCSELs, MESFETs, and photodiodes with CMOS circuitry. In 1996, he joined the faculty of the College of Optical Sciences, University of Arizona, Tucson. His current interests involve the development of a biochip for toxicity testing of chemicals, a high-bandwidth electrooptic modulator, microphotonic integration with CMOS circuitry, and the development of electrooptic eyeglasses. Jennifer K. Barton (S 95 M 98) received the B.S. and M.S. degrees in electrical engineering from the University of Texas at Austin and University of California, Irvine, respectively, and the Ph.D. degree in biomedical engineering from the University of Texas at Austin in She was with McDonnell Douglas on the Space Station program before returning to The University of Texas at Austin for her Ph.D. studies. Since that time, she has been an Assistant and Associate Professor of biomedical engineering, electrical and computer engineering, and optical sciences at the University of Arizona. Her research interests include optical coherence imaging of tissue and laser-blood vessel interaction.