Modeling and simulation of UPFC using PSCAD/EMTDC

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1 Internatonal Journal of Physcal Scences Vol. 7(45), , 30 November, 2012 Avalable onlne at htt:// DOI: /IJPS ISSN Academc Journals Full Length Research Paer Modelng and smulaton of UPFC usng PSCAD/EMTDC Pramod Kumar Gouda 1, Ashwn K. Sahoo 2 * and P. K. Hota 3 1 Deartment of Electrcal Engneerng, A. M. S. College of Engneerng, Chenna, Inda. 2 Deartment of Electrcal Engneerng, S. S. N. College of Engneerng, Chenna, Inda. 3 Deartment of Electrcal Engneerng, VSSUT, Burla, Sambalur, Odsha, Inda. Acceted 3 August, 2012 Ths aer rooses to model and smulate a unfed ower flow controller (UPFC) n ower system comuter aded desgn and electromagnetc transent drect current (PSCAD/EMTDC) envronment. The seres converter of the UPFC controls the transmsson lne real/reactve ower flow and the shunt converter of the UPFC controls the UPFC bus voltage/shunt reactve ower and the DC lnk caactor voltage. The real ower demand of the seres converter s suled by the shunt converter of the UPFC va the DC lnk caactor. The control of transmsson lne reactve ower flow leads to excessve voltage excurson of the UPFC bus voltage. In ths roosed work, we have consdered two system cases. The frst case s to cause a sudden ncrease n the system load. The second case s to ntroduce a transent fault n the system. In both cases, excessve bus voltage excursons occur. A UPFC s modeled and desgned to reduce these bus voltage excursons, and also roer coordnaton between the seres and shunt converter controllers of the UPFC s mantaned to lmt the collase of DC caactor voltage. PSCAD/EMTDC software s utlzed to desgn and smulate the model. Key words: Unfed ower flow controller (UPFC), coordnated control, roortonal ntegral (PI), ower system comuter aded desgn and electromagnetc transent drect current (PSCAD/EMTDC). INTRODUCTION The technology of ower system utltes around the world has radly evolved wth consderable changes n the technology along wth mrovements n ower system structures and oeraton. The ongong exansons and growth n the technology, demand more otmal and roftable oeraton of a ower system. In the resent scenaro, most of the ower systems n the develong countres wth large nterconnected networks share the generaton reserves to ncrease the relablty of the ower system. However, the ncreasng comlextes of large nterconnected networks had fluctuatons n relablty of ower suly, whch resulted n system nstablty, dffcult to control the ower flow and securty roblems that resulted large number blackouts n dfferent arts of the world. The reasons behnd the stated fault sequences may be due to the systematcal errors n lannng and oeraton, weak nterconnecton of the ower system, lack of mantenance or due to overload of *Corresondng author. E-mal: ashwnsahoo@ssn.edu.n. the network. In order to overcome these consequences and to rovde the desred ower flow along wth system stablty and relablty, nstallatons of new transmsson lnes are requred. However, nstallaton of new transmsson lnes wth the large nterconnected ower system are lmted to some of the factors lke economc cost, envronment related ssues. These comlextes n nstallng new transmsson lnes n a ower system challenges the ower engneers to research on the ways to ncrease the ower flow wth the exstng transmsson lne wthout reducton n system stablty and securty (Hngoran and Gyugy, 2000; Mohan Mathur and Rajv, 2002; Acha et al., 2002). Gyugy (1992) roosed the unfed ower flow controller (UPFC). It s the most versatle and comlex ower electronc devce ntroduced to control the ower flow and voltage n the ower systems. It s desgned by combnng the features of FACTS controllers - statc synchronous seres comensator (SSSC) and statc synchronous comensator (STATCOM). It has the ablty to control actve and reactve ower flow of a transmsson lne smultaneously n adon to controllng

2 5966 Int. J. Phys. Sc. Transmsson Lne V u V c V u Shunt Transformer STATCOM (Shunt Inverter) SSSC (Seres Inverter) Seres Transformer + V dc dc - V u V u V c DC lnk CONTROLLER Fgure 1. Basc crcut confguraton of the UPFC. all the transmsson arameters (voltage, medance and hase angle) affectng the ower flow n a transmsson lne. The basc control for the UPFC s such that the seres converter of the UPFC controls the transmsson lne real or reactve ower flow and the shunt converter of the UPFC controls the UPFC bus voltage/shunt reactve ower and the DC lnk caactor voltage. Several artcles are reorted on UPFC for dfferent studes, namely mrovement n transent stablty and damng of rotor swng. Padyar and Kulkurn (1998) roosed a control strategy for the UPFC for real ower flow control by reactve voltage njecton and ndrect reactve ower flow control by control of voltage at the two orts of the UPFC. The controllers are desgned ndeendently and use locally avalable measurement. Krshna and Padyar (2005) roosed a method that nvolves the soluton of a constraned otmzaton roblem to determne the voltage and current njected by the UPFC, so as to maxmze or mnmze the ower flow n the lne n whch t s located at each ste. Kannan et al. (2004) roosed a cascaded roortonal ntegral (PI) controller desgn to lmt excessve voltage excursons durng reactve ower transfers. In steady state, the real ower demand of the seres converter s suled by the shunt converter of the UPFC. To avod nstablty/loss of DC lnk caactor voltage durng transent conons, a real ower coordnaton controller was desgned. Also, the need for reactve ower coordnaton controller for UPFC arses from the fact that excessve bus voltage (the bus to whch the shunt converter s connected) excursons occur durng reactve ower transfers. Here, the UPFC s modeled and desgned to reduce these bus voltage excursons and also roer coordnaton between the seres and shunt converter controllers of the UPFC s mantaned to lmt the collase of DC caactor voltage. The smulaton results for a case study ndcate that ths s a vable control scheme, whle ths aer gves basc strategy and desgn consderaton, further refnement s ossble n the context of the recent advances n control strategy. In ths aer, frst, the modelng of synchronous generator along wth automatc voltage regulator (AVR), ower system stablzer (PSS) and modelng of UPFC were derved. Subsequently, the coordnated control schemes of UPFC were desgned n PSCAD/EMTDC envronment (Introducton to PSCAD/EMTDC, 2000) and smulaton results are dscussed under dfferent loadng and transent dsturbance conon. BASIC CIRCUIT CONFIGURATION OF UPFC The rncal functon of the UPFC s to control the flow of real and reactve ower by njectng a voltage n seres wth the transmsson lne. The UPFC conssts of two sold-state voltage source nverters (VSIs) connected by a common DC lnk that ncludes a storage caactor shown n Fgure 1. The frst nverter (shunt nverter) known as a STATCOM njects an almost snusodal current of varable magntude at the ont of connecton. The second nverter (seres nverter), known as SSSC rovdes the man functonalty

3 Gouda et al E q 0 ~ P, Q x d, d q Vt δ t x t1 Vs R s V c Local Load Vu δ u P u, Q u c P ref, Q ref, bd bq L P L, Q L V UPFC Fgure 2. One-lne crcut dagram model of UPFC nstalled n a ower system. of the UPFC by njectng an alternatng current (AC) voltage V c, wth a controllable magntude (0 V c V c max ) and hase angle ( 0, 360 ). Thus, the comlete confguraton oerates as an deal AC to AC ower converter n whch real ower can flow freely n ether drecton between the AC termnals of the two nverters. The hasor dagram n Fgure 1 shows that the UPFC s able to nject a controlled seres voltage V c nto the transmsson lne. Thus, the magntude and angle between the sendng and recevng end of the transmsson lne are modulated resultng n ower flow control n the transmsson lne. Therefore, the actve ower controller can sgnfcantly affect the level of reactve ower flow and vce versa. In order to mrove the dynamc erformance and reduce the nteracton between the actve and reactve ower control, the wattvar decouled control algorthm was roosed. In adon, each nverter can ndeendently modulate reactve ower at ts own AC outut termnal (Sharma and Jagta, 2010). MATHEMATICAL MODEL OF UPFC Sngle machne nfnte bus ower system s consdered n ths work. The mathematcal models for the system comonents along wth ther control systems are descrbed as follows: Synchronous generator modelng The synchronous generator s descrbed by a thrd-order nonlnear mathematcal model gven by Equatons 1 to 3. dδ Δω (1) dδ 1 M de q 1 T do P m E E fd Where 0 q q q E x x q d x d x d d q and 0. Dynamcal modelng of UPFC Fgure 2 shows the equvalent crcut model of a ower system equed wth a UPFC. The seres and shunt VSIs are reresented by controllable voltage sources V c and V, resectvely. R and L reresent the resstance and leakage reactance of the shunt transformer. The dynamc model of UPFC s derved by erformng standard d-q transformaton of the current through the shunt transformer and seres transformer and s resented n Equatons 4 to 7. Shunt nverter d d d (2) (3) R 1 d ωq (Vsd Vd ) (4) L L dq R 1 q ωd (Vsq Vq ) (5) L L

4 5968 Int. J. Phys. Sc. Seres nverter d d bd bq w bre w b bd ωbq (Vud Vbsn ) (6) x x e e w bre w b bq ωbd (Vuq Vbcos) (7) x x e e Where s the angular frequency of the voltages and currents. For fast voltage control, the net nut ower should nstantaneously meet the chargng rate of the caactor energy. Thus, by alyng ower balance conons, we get Equaton 8. P P V ( s u V dc dc sd d bd ) V sq ( q bq ) (V ud bd V uq bq dvdc V dcc g cvdc (8) Thus, Equaton 8 can be rearranged and wrtten as gven n Equaton 9. dv dc g cω V b c dc 1 CV dc Vsd d Vsq (Vsd Vud) q bd (V sq V COORDINATED CONTROL STRATEGY FOR UPFC Proer coordnaton between the seres and shunt converter control system n the UPFC has to be establshed. If roer coordnaton s not establshed, t could lead to collase of the DC lnk caactor voltage. The voltage level of the DC lnk caactor s mantaned by the shunt converter. Real ower demanded by the seres converter s also suled by the shunt converter va the DC lnk caactor. Durng sudden changes n the system such as system load or transent faults, there wll be reducton n the bus voltages. Regulaton of the bus voltages can be done by arorate reactve ower transfers. Durng such reactve ower transfers, roer coordnaton has to be mantaned n the UPFC to avod collase of DC lnk caactor voltage. Thus, roer coordnaton of real and reactve ower n the UPFC has to be mantaned. In ths aer, a smultaneous control of the UPFC controllers s done to enable arorate coordnaton n the UPFC thereby enablng bus voltage regulaton and avodance of DC caactor voltage collase. Therefore, n the PI control scheme, the control strateges for both the nverters are addressed uq ) bq ) (9) searately. The modelng and control desgn are carred out n the standard synchronous d-q frame (Juan et al., 2005). Seres nverter control An arorate seres voltage (both magntude and hase) should be njected for obtanng the commanded actve and reactve ower flow n the transmsson lne, that s, P u, Q u. The current references are comuted from the desred ower references and are gven by Equatons 10 and 11. P V Q V ref ref ud ref uq cd (10) 2 Vu ref cq Pref Vuq Qref Vud (11) V 2 u The ower flow control s then realzed by usng arorately desgned controllers to force the lne currents to track ther resectve reference values. Conventonally, two searate PI controllers are used for ths urose. These controllers outut the amount of seres njected voltages V, V ) Shunt nverter control (. cd cq As mentoned earler, the conventonal control strategy for ths nverter concerns wth the control of AC-bus and DC-lnk voltage. The dual control objectves are met by generatng arorate current reference (for d and q axs) and then, by regulatng those currents. PI controllers are conventonally emloyed for both the tasks, whle attemtng to decoule the d and q axs current regulators. The nverter current ( ) s slt nto real (n hase wth ac-bus voltage) and reactve comonents. The reference value for the real current s decded so that the caactor voltage s regulated by ower balance. The reference for reactve comonent s determned by AC-bus voltage regulator. As er the strategy, the orgnal currents n d-q frame ( d, q) are now transformed nto another frame, d q frame, where d axs concdes wth the ac-bus voltage ( Vs ), as shown n Fgure 3. Thus, n d q frame, the currents d and q reresent the real and reactve currents and are gven by Equatons 12 and 13. cosδ snδ d d s q s (12)

5 Gouda et al q q d d q R q u q (22) L s V s Fgure 3. Phasor dagram showng d-q and d -q frame. d Conventonally, the control sgnals u d and u q are determned by lnear PI controllers. In ths study, the stated desgn was used for demonstraton of UPFC control scheme. Ths aroach led to good control as llustrated by the smulaton results shown n later secton. CIRCUIT DESCRIPTION AND PROBLEM STATEMENT q cosδ snδ (13) q s q s Now, for current control, the same rocedure has been adoted by re-exressng the dfferental equatons as gven n Equatons 14 to 18. d d d' q' where V V d' q' and R 1 d' ωq' (Vs Vd' ) (14) L L R 1 d' q' ( Vq' ) (15) L L V cos δs V sn δs (16) d q V cosδ V sn δs (17) q d s s d 0 (18) The VSI voltages are controlled as gven n Equatons 19 and 20. V V q' d' ( L L u ) (19) q' d' s q ωl V L u (20) d By substtutng the above exressons for Vd and Vq n Equatons 14 and 15, the followng sets of decouled equatons are obtaned. In order to llustrate the desgn and mlementaton of the UPFC, a sngle hase crcut where the UPFC s connected between the source and the load s selected as shown n Fgure 4. It conssts of a 3-hase source connected to Bus1. Loads 1 and 2 are connected to Bus 2. There are two transmsson lnes connectng Buses 1 and 2. The shunt converter of the UPFC s connected to Bus 1 through a shunt coulng transformer. The seres converter of the UPFC s connected to transmsson Lne 2 through a seres coulng transformer. Controllers are desgned to co-ordnate real and reactve ower transfer n the UPFC and thereby to effcently oerate the UPFC. Load 1 s ermanently connected to the system Bus 2. Load 2 s connected to Bus 2 only at a secfc tme nterval. Due to the sudden ncrease n the system load, there s a dro n the bus voltages. Also, a transent 3- hase fault s ntroduced nto the system at a secfc tme. Due to the sudden transent fault, there s a dro n the bus voltages. UPFC should be oerated n such a manner to comensate the dro n the bus voltage by generatng the requred amount of reactve ower and sulyng t to ts connected bus. Also, the collase of the DC caactor voltage has to be avoded. The electromagnetc transent modelng of UPFC for the test case study usng PSCAD/EMTDC s shown n Fgure 5. CONTROLLER CIRCUIT The controller crcut rovdes detaled descrton regardng the generaton of frng ulses for both shunt and seres converter under varous oeratng conons. The methodology by whch roer co-ordnaton s mantaned between the shunt and seres converter s also dscussed. The assocated control schemes are shown n Fgures 6 and 7. Shunt converter controller d d R d u d (21) L Shunt converter controller crcut descrbes the technque by whch the angle order s generated based on changes n arameters of the man crcut. Utlzng ths angle, the

6 5970 Int. J. Phys. Sc. Fgure 4. Basc block dagram of the crcut Fgure 5. Electromagnetc transent modelng usng PSCAD/EMTDC. Fgure 6. Crcut for generatng angle order.

7 Gouda et al Fgure 7. Control crcut for generatng ulses. order requred frng sgnals for the shunt converter s generated. Measured reactve ower and root mean square (RMS) voltage (n er unt) s gven as the nut. The measured reactve ower s dvded wth the rated reactve ower of the crcut. Ths outut s dvded wth the measured RMS voltage (n er unt). After allowng a dro of about 3% the outut of ths block s summed u agan wth the measured RMS voltage. Ths summed outut s assed through flters. The reference voltage (n er unt), s summed wth the outut sgnal of the flters. Ths s gven as nut to the PI controller. The outut of PI controller s the angle order. It reresents the requred shft between system voltage and voltage generated by shunt converter (STATCOM). Ths shft determnes the drecton and amount of ower flow. Manual tunng of the roortonal and ntegral gan of the PI controller s done. The outut angle order s converted to degrees. Frng sgnals are generated by ulse wh modulaton technque. The nstantaneous voltage measured s slt nto ts 3-hase comonents. Ths s gven as nut to the 3-hase PI controlled hase locked loo. It generates a ram sgnal that s synchronzed n hase to the nut voltage sgnal. Ths s then multled wth a real constant to obtan the necessary carrer frequency. From ths trangular waveforms synchronzed wth system AC voltage are generated. Now snusodal waveforms synchronzed wth system AC voltage and shfted by the angle order are to be generated. Agan, the nstantaneous voltage slt nto ts 3-hase comonents s gven as nut to the 3-hase PI controlled hase locked loo. The generated sgnal that s synchronzed n hase to the nut voltage sgnal s shfted by the obtaned angle order. Then, ths outut sgnal s sent to the snusodal functon block to generate the requred snusodal waveforms. The generated trangular and

8 Voltage (.u.) 5972 Int. J. Phys. Sc. Fgure 8. RMS lne voltage durng normal conon. Tme (s) Tme (s) Fgure 9. Bus 1 voltage waveform durng normal conon. snusodal waveforms are sent to the nterolated frng ulse generaton block. Two sets of nut sgnals (reference and trangular ones) are needed; one set for turnng on and the second one (a negaton of the frst set of sgnals) for turnng off. Frng ulses are generated usng comarson of snusodal sgnals to trangular sgnals. The outut sgnals generated are of two element arrays. The frst element determnes the frng sgnals whch ndcate the gate turn-off (GTOs) to turn-on and turn-off. The second element determnes the exact moment of swtchng whch s used by nterolaton rocedure for swtchng between tme stes. (SSSC). If the voltage generated by the seres converter s n hase wth the lne current, t exchanges a real ower and f the voltage generated by the seres converter s n quadrature wth lne current, t exchanges a reactve ower. TEST CASES AND SIMULATION RESULTS Fve cases were consdered to examne the valy of the roosed model. In all the cases, Load 1 s always connected to the system. Seres converter controller The controller crcut for the seres converter s smlar to that of the shunt converter. But here the nut values for the generaton of angle order are the measured real ower and the RMS value of voltage. The generated angle order reresents the requred shft between system voltage and voltage generated by seres converter Case A There s no change n load; UPFC s not connected to the system; no transent fault s ncluded n the system. The lne voltage, the RMS voltage at Buses 1 and 2 are shown n Fgures 8, 9 and 10, resectvely under normal oeratng conon and Table 1 shows the corresondng values.

9 Voltage (.u.) Gouda et al Tme (s) Fgure 10. Bus 2 voltage waveform durng normal conon. Table 1. Voltages durng ncreased load and UPFC dsconnected conon. Normal load (only Load 1) Increased load (Loads 1 and 2) (Tme nterval of 0.5 to 1 s) RMS voltage (u) Bus 1 voltage (kv) Bus 2 voltage (kv) RMS voltage (u) Bus 1 voltage (kv) Bus 2 voltage (kv) Fgure 11. RMS lne voltage durng ncreased load. Tme (s) Case B There s an ncrease n system load durng the tme nterval of 0.5 to 1 s; the UPFC s not connected to the system; no transent fault s ncluded. Under ths conon, the voltage at the lne and bus ont dros by as shown n Fgures 11, 12 and 13. Voltage dros as much as 23%, gvng a V rms value equal to u. as shown n Table 1. Case C There s an ncrease n system load durng the tme nterval of 0.5 to 1 s; the UPFC s connected to the system; no transent fault s ncluded n the system. From Fgures 14, 15 and 16, t s shown that when the UPFC s connected n the system, voltage regulaton s done durng sudden ncreased system load conons. Ths can be observed from the ncrease n reactve ower durng the tme nterval of 0.5 to 1 s as shown n Fgure 17. The normal level of RMS voltage (.u.) s mroved u to a value of u. from a value of u. (Case B) as shown n Table 2. So the UPFC mroves the ntal voltage rofle, regulates the voltage durng ncreased system load conons and the DC caactor voltage collase s also avoded (Fgure 18). Case D There s no ncrease n system load; the UPFC s not

10 Voltage (.u.) 5974 Int. J. Phys. Sc. Tme (s) Fgure 12. Bus 1 voltage waveform durng ncreased load. Fgure 13. Bus 2 voltage waveform durng ncreased load. Tme (s) Tme (s) Fgure 14. RMS lne voltage durng ncreased load and UPFC connected conon.

11 Q (MVAR) Gouda et al Tme (s) Fgure 15. Bus 1 voltage waveform durng ncreased load and UPFC connected conon. Tme (s) Fgure 16. Bus 2 voltage waveform durng ncreased load and UPFC connected conon. Tme (s) Fgure 17. Reactve ower waveform durng ncreased load and UPFC connected conon.

12 Voltage (.u.) 5976 Int. J. Phys. Sc. Table 2. Voltages durng ncreased load and UPFC connected conon. Normal load (Only load 1) Increased load (Loads 1 and 2) (Tme nterval of 0.5 to 1 s) RMS voltage (u) Bus 1 voltage (kv) Bus 2 voltage (kv) RMS voltage (u) Bus 1 voltage (kv) Bus 2 voltage (kv) Tme (s) Fgure 18. DC caactor voltage waveform durng ncreased load and UPFC connected conon. Tme (s) Fgure 19. RMS lne voltage when transent fault s aled. connected to the system; a 3-hase transent fault s ncluded durng the tme nterval of 1 to s. From Fgures 19, 20 and 21, and Table 3, we get to know that durng transent fault conons the RMS voltage and the two bus voltages are reduced. Case E There s no ncrease n system load; the UPFC s connected to the system; a 3-hase transent fault s ncluded durng the tme nterval of 1 to s. From Fgures 22, 23 and 24, and Table 4, t s clear that when the UPFC s connected n the system, voltage regulaton s done durng transent fault conons. So the UPFC mroves the ntal voltage rofle, regulates the voltage durng transent fault conons. The DC caactor voltage collase s also avoded, as evdent from Fgure 25. The ncreased n reactve ower suort by the UPFC durng transent fault s shown n Fgure 26. All voltage sgnals of Buses 1 and 2 voltages dslayed n the cases are RMS value of hase A to ground

13 Gouda et al Tme (s) Fgure 20. Bus 1 voltage waveform when transent fault s aled. Tme (s) Fgure 21. Bus 2 voltage waveform when transent fault s aled. Table 3. Voltages durng transent fault and UPFC dsconnected conon. Wthout fault Wth fault (Durng 1 to s) RMS voltage (u) Bus 1 voltage (kv) Bus 2 voltage (kv) RMS voltage (u) Bus 1 voltage (kv) Bus 2 voltage (kv) voltage sgnals. Concluson Due to the sudden ncrease n the system load or due to certan transent faults, there s a dro n the bus voltages. To regulate the bus voltages, the UPFC s oerated n voltage control mode. In ths case, the RMS value of voltage (n er unt) s measured smultaneously. When there s a dro n the RMS value of voltage, the UPFC detects t. The necessary frng sgnals are gven to the converters by the controllers. The shunt converter generates or absorbs the necessary amount of reactve

14 Voltage (.u.) 5978 Int. J. Phys. Sc. Tme (s) Fgure 22. RMS voltage waveform when transent fault s aled and UPFC s connected. Tme (s) Fgure 23. Bus 1 voltage waveform when transent fault s aled and UPFC s connected. Tme (s) Fgure 24. Bus 2 voltage waveform when transent fault s aled and UPFC s connected. ower to regulate the bus voltages. Also, durng ths oeraton the collase of the DC caactor voltage s avoded. Ths s done through smultaneous control of the shunt and seres converter controllers, through whch roer real and reactve ower coordnaton n the UPFC s mantaned.

15 Q (MVAR) Gouda et al Table 4. Voltages durng transent fault and UPFC connected conon. Wthout fault Wth fault (Durng 1 to s) RMS voltage (u) Bus 1 voltage (kv) Bus 2 RMS voltage (u) Bus 1 voltage (kv) Bus 2 voltage (kv) Tme (s) Fgure 25. DC caactor voltage waveform when transent fault s aled and UPFC s connected. Tme (s) Fgure 26. Reactve ower waveform when transent fault s aled and UPFC connected conon. REFERENCES Acha E, Agelds VG, Lara OA, Mller THE (2002). Power Electronc Control n Electrcal Systems. New. Pow. Eng. Seres. Frst Eon. Gyugy L (1992). Unfed Power Flow Control Concet for FACTS. IEE Con. Proc. Gen. Trans. Dstr. 139(4): Hngoran NG, Gyugy L (2000). Understandng FACTS: Concet and Technology of Flexble AC Transmsson System. IEEE Press. Introducton to PSCAD / EMTDC (2000). Mantoba HVDC Research Centre. Juan D, José R, Rcardo D (2005). Reactve Power Comensaton Technologes: State-of-the-Art Revew. Proc. IEEE. 93(12): Kannan S, Jayaram S, Salama M (2004). Real and reactve ower coordnaton for a unfed ower flow controller. IEEE Trans. Pow. Syst. 19(3):

16 5980 Int. J. Phys. Sc. Krshna S, Padyar KR (2005). Dscrete control of unfed ower flow controller for stablty mrovement. Electrc Pow. Sys. Res. 75(2): Mohan Mathur TR, Rajv KV (2002). Thyrstor based FACTS Controllers for Electrcal Transmsson Systems. Frst Eon, a John Wley & Sons, Inc. Publcaton. Padyar KR, Kulkurn AM (1998). Control desgn and smulaton of a unfed ower flow controller. IEEE Trans. Pow. Delv. 13(4): Sharma NK, Jagta PP (2010). Modellng and alcaton of Unfed Power Flow Controller (UPFC). IEEE Thrd Int. Con. Emergng Trends Eng. Technol. 93(12):