Comparisons between Synchronizing Circuits to Control Algorithms for Single-Phase Active Converters

Transcription

1 H. Carnero, L. F. C. Montero, João L. Afonso, Comparsons between Synchronzng Crcuts to Control Algorthms for Sngle- Phase Actve Converters, IECON 9 - The 5th Annual Conference of the IEEE Industral Electroncs Socety, -5 November 9, Porto, Portugal. Comparsons between Synchronzng Crcuts to Control Algorthms for Sngle-Phase Actve Converters H. Carnero 1, L. F. C. Montero, J. L. Afonso 1 1 Unversty of Mnho Industral Electroncs Department, Campus de Azurém Gumarães, Portugal. PROQUALI, Estrada do Galeão 7 / 1, Ilha do Governador , Ro de Janero, Brazl. E-mal: Helder.carnero@gmal.com, lfcm@lemt.ufrj.br, jla@de.umnho.pt Abstract Ths paper presents a comparatve analyss between synchronzng crcuts appled to control algorthms for snglephase actve converters. One of these synchronzng crcuts corresponds to the sngle-phase PLL (Phase Locked Loop), mplemented n - coordnates, whereas the other one corresponds to the E-PLL (Enhanced PLL). These synchronzng crcuts are compared n several aspects as processng and settlng tme and memory space requrements. Moreover, the performance of a sngle-phase back-to-back converter s also presented, wth ts control algorthm based on these Synchronzng Crcuts. Each one of the control algorthms were mplemented n a DSP mcroprocessor TMSF81F from Texas Instruments. Smulaton and expermental results, through a back-to-back converter prototype, are presented. I. INTRODUCTION The prolferaton of nonlnear loads n resdences, offces and ndustres has contrbuted to ncrease the harmonc polluton observed n the power grd. Moreover, the harmonc current-components consumed by these nonlnear loads results n harmonc voltage-drop on the supply lne mpedances, whch deterorates the waveform of the voltages delvered to the load [1]. There are also other events as voltage sags or voltage swells that are resulted, respectvely, from connecton or dsconnecton of large loads [] []. All of these events are the most responsble ones for the observed problems n senstve loads as mproperly shut down, reduced lfetme, malfuncton, and so others. Power qualty problems can be overcome, n real tme, through the utlzaton of Custom Power devces. In ths paper a back-to-back converter s used, whch s composed by two power converters that are connected n seres and n shunt wth the power grd. The shunt converter conssts n an actve rectfer that njects or absorbs energy from the power grd, n order to keep the dc-lnk voltage regulated. The seres converter s responsble to compensate the major power qualty problems related wth the system voltages, such that the voltage delvered to the load reman regulated and wth low harmonc dstorton. To control these converters, control algorthms based on the nstantaneous power theory (p q Theory) are appled [4] together wth a synchronzng crcut. The synchronzng crcut s responsble to produce, n real tme, snusods that are synchronzed wth the fundamental component of the system voltage. Thus t can be observed ts mportance, snce the voltage produced by the seres converter depends, drectly, on the generated snusod by the synchronzng crcut. Due to the mportance of the synchronzng crcut, ths paper nvestgates two dfferent topologes. The frst one corresponds to the sngle-phase PLL (Phase - Locked - Loop) [4] [5] [6] [7] [8], mplemented n - coordnates, whereas the other one corresponds to the E-PLL (Enhanced PLL) [9] [1] [11]. The comparson nvolvng these PLL topologes s focused n processng and settlng tme and memory space requrements. Both controllers where mplemented n a DSP mcroprocessor TMSF81F from Texas Instruments. Beng a real tme processng system, computng speed and memory usage, as well as the settlng tme are mportant ssues. These characterstcs must be enhanced; moreover, they most provde compensated voltages that comprses wth the power qualty standards [1]. Smulaton and expermental results, through a back-to-back converter prototype, are presented. II. HARDWARE CONFIGURATION As aforementoned n ths paper and ndcated n Fg. 1, the back-to-back converter s composed by two power converters that are connected n seres and n shunt wth the power grd. A step-down transformer (5 kva V//115 V) s used to provde galvanc solaton between the power converters and the power grd. Another step-down transformer, wth the same characterstcs, s used to connect the shunt converter wth the power grd. The seres converter s drectly connected wth the power grd. Each one of the sngle-phase power converters s composed by two branches (4 IGBTs wth ant-parallel dodes) from model Semkron SKM-5GB6D [1]. The IGBTs of ths power module present as man features a collector-emtter voltage of 6 V and a collector current of 5 A (peak value). The dc-lnk s composed by three 47 F capactors connected n seres, whch corresponds to an equvalent capactor of, approxmately, F. Each one of these capactors presents a dc-voltage ratng of 45 V. The RLC couplng flter of the seres converter s composed by a 15 resstor (R fs ), an 8.8 F capactor (C fs ), and an ar-core nductor of.6 mh (L fs ). The RLC flter of the /9/$5. 9 IEEE 9

2 Fg. 1. Electrcal Dagram of the Sngle-Phase Back-to-Back Converter. shunt converter s comprehended by a.6 mh nductor (L fp ), an 4 resstor (R fp ), and an. F capactor (C fs ). The nonlnear load conssts of a sngle-phase dode rectfer, wth a RC Load on the dc-sde (C DC = 4,7 mf and R DC = 5 ). To smooth the current waveform, t s used a mh nductor (L 1 ). There s also a lnear load, connected n shunt wth the nonlnear load, composed by a resstor (R 1 ) and a 65 H nductor (L ). A dode rectfer, smlar to the nonlnear load, s used to ncrease the harmonc dstorton of the supply voltage. Ths rectfer s located between the transformer, connected n seres wth the power grd, and the seres converter. A soft-start crcut was mplemented to suppress the lack of electrc solaton of a couplng transformer that s present n the majorty of seres converters [1]. It also acts as a protecton system to overloads and short-crcuts. Moreover, contactors are employed to connect the shunt (C ) and seres (C 4,C 5,C 6 ) power converters, as well as to connect the loads wth the electrcal system (C 1,C ). The supply voltage s represented n Fg. 1 as beng v S, and the load voltage s. The produced voltage by the seres converter s represented as v comp. The load and source currents are represented as L and S, respectvely. The controlled current ( reg ) s produced by the shunt converter n order to regulate the DC lnk voltage. III. CONTROLLER OF THE BACK-TO-BACK CONVERTER As ntroduced n secton I the controller of the back-toback converter s consttuted by control algorthms to determne the reference sgnals to be produced by the power converters, plus swtchng algorthms to command the IGBTs. The control algorthms to determne the reference sgnals are comprehended by a synchronzng crcut, an algorthm to determne the compensatng currents and an algorthm to determne the compensatng voltages. In Fg. s shown a block dagram that represents the control algorthms to determne the reference sgnals. The control algorthms denomnated n Fg. as Current-Reference Algorthm and Voltage-Reference Algorthm are based on the concepts nvolvng the nstantaneous power theory (p q Theory) wth some smplfcatons. Hereafter, these control algorthms are descrbed, and, n sequence, the nvestgated synchronzng crcuts are ntroduced. A. Current-Reference Algorthm Snce there are no power sources on the dc sde of the power converter, a controller that keeps the dc-lnk voltage regulated has to be mplemented. It s worth to notce that, wth only ths control algorthm, the shunt converter does not provde actve flterng. In ths case, the shunt converter can be consdered as an actve rectfer. Based on the dc-lnk voltage (v DC ), the control sgnal p Reg s determned as descrbed as follows: k_dc p g (vref vdc ) (k p_dc ). (1) Re s The control sgnal p Reg can be understood as an amount of energy, per tme unt, that s draned or njected by the shunt converter n order to keep the dc-lnk voltage regulated. As ndcated n (1), the control sgnal v Ref corresponds to the S 1 v dc 1 S Current-Reference Algorthm Synchronzng Crcut Voltage-Reference Algorthm Ref v Ref Fg.. General control scheme of the algorthms that determne the reference sgnals /9/$5. 9 IEEE

3 reference value of the dc-lnk voltage, and the control sgnals pdc and dc represent, respectvely, to the proportonal and ntegral gans of the PI-Controller. In sequence, the mathematcal methodology to determne the reference sgnal Ref s descrbed. Snce ths algorthm s based on the p q Theory, consder that s necessary to determne the reference sgnals n coordnates ( Ref, Ref ) as descrbed as follows: Re f Re f 1 pre g, () where, the sgnals and are generated by the synchronzng crcut. For now, t s assumed that these sgnals are snusodal waveforms, wth untary ampltude, and are n phase wth the fundamental frequency of the control sgnals and, respectvely. After some smplfcatons n equaton (), Ref and Ref are gven by: p Re g Re f p Re g Re f p p Re g Re g Indeed, snce the control sgnals and are snusods wth untary ampltude and leads, t can be assumed that the sum of ther square values s equal to one. Based on the Clarke Transformaton [1] [14] and assumng a fcttous three-phase three-wre system, the control sgnal Ref s gven by: Re f Re f Re f (). (4) As t can be observed n (4), Ref s only assocated wth Ref. Combnng () and (4) the reference sgnal Ref can be determned n a very smple way as descrbed as follows: Re f p Re g. (5) Based on the aforementoned eplanaton, t can be noted that the computatonal effort to determne Ref s drectly related wth the synchronzng crcut and wth the PI- Controller. In sequence, the control algorthm that determnes the reference voltage v Ref s descrbed.. oltge-reference Algorthm As llustrated n Fg., ths algorthm presents as nputs the sgnals derved from the source current ( S ) n coordnates ( S, S ), the control sgnal obtaned from the system voltage( ), plus the sgnals generated by the synchronzng crcut (, ). In ths algorthm there s also a control block that determnes control voltages wth the objectve to damp resonance phenomena, denomnated as Dampng Algorthm block. Indeed, as descrbed n [6], nstablty problems due to the resonance phenomena, nvolvng the passve flters and the system mpedance, may occur. In order to enhance the overall system stablty, an aulary algorthm can be added to the controller of the seres converter. In sequence, t s descrbed a mathematcal methodology, based on the p q Theory, to determne the control sgnal. In a smlar way of the presented one n (4) the control sgnals S and are determned, respectvely, from the source current ( S ) and system voltage (v S ) as descrbed as follows: v v. The sgnal S s shfted by from S. The control sgnals S and S, together wth to the ones generated by the synchronzng crcut (, ) are appled to calculate the real and magnary powers as descrbed as follows: p q (6). (7) In sequence, the control sgnal S s determned accordng to the followng equaton: h S 1 S amng Algorthm + p q / Fg.. Dagram blocks of the Voltage-Reference Algorthm v Ref, () where, the powers p and corresponds to the oscllatng components of the real (p) and magnary () powers, and they can be obtaned through hgh-pass flters. The drect product nvolvng the control sgnal S by a gan denomnated as results n the harmonc controlled-voltage ( ). The gan can be understood as a resstance only for the harmonc components. Further detals nvolvng the dampng algorthm are descrbed n [14]. Fnally, the reference voltage (v Ref ) s determned as ndcated n Fg.. hen v Ref s produced by the seres converter, t s epected that power qualty problems /9/$5. 9 IEEE 1

4 q v + S Fg.. ngle-hase hase-ocke-oo. / obsere at the sstem oltages can be comensatean moreoert s eectethat roblems relateth resonance henomena can be aoe. n seence are resente the snchronng crcts aforementonen secton. C. Sngle-Phase Phase-Locked-Loop (Sngle-Phase PLL) hs snchronng crct s smlar to the one mlemente to three-hase sstems th some smlfcatons as ntrocen. n Fg. s llstratethe sngle-hase n coornates. As ncaten Fg. the feeback sgnals an are blt b the crct st sng the tme ntegral of ott of the -ontroller. hese feeback sgnals hae nt amlte an leas. he crct becomes stable onl f the aerage comonent of the fcttosmagnaroer reaches ero ale q ' an has mnme lo-freenc oscllatng ortons n ts oscllatng comonent q~ '. nce the crct s stablethe aerage ale of q s ero anth thsthe hase angle of the fnamental freencs reache. At ths contonthe feeback sgnal becomes n hase th the fnamental comonent of the control sgnal. Frther elanatons nolng ths for three-hase sstems are resenten. ereaftert follos some smlaton reslts relate th the sngle-hase. ntalln ths case testthe nt sgnal corresons to =1sn(t+45º). At t=.sthe hase angle of the nt sgnal s mofesch that the mofent sgnal corresons to =1sn(t+). n Fg. s shon the erformance of the sngle-hase trackng the nt sgnal =1sn(t + 45º). he starts at t=.1s. After cclesthe control sgnal tracks the nt sgnal. Fg. llstrates the control sgnal trackng the nt sgnal at the transent t=.shen the hase angle of the nt sgnal Ref s ncreasefrom to. As t can be seen n Fg. at t=.7sthe control sgnal tracks agan the nt sgnal. ase on these relmnar smlaton resltst can be notethe feasbltof ths snchronng crct. t can also be seen n lteratre the erformance of ths ner orse contons than the resenteones n ths aer. / t V(Volts) (degrees) ref PLL Tme(s) Fg.. erformance of the sngle-hase to track the nt sgnal ref PLL 4 (degrees) V(Volts) Tme(s) Fg.. erformance of the sngle-hase to track the nt sgnal hen the hase angle ref s mofefrom to. D. Sngle Phase Enhanced PLL n Fg.the roose algorthm s shon as a block agram of the nhance. rgnallthe comrses a control looto etermne the amlte ananother control loothat etracts the freencanhase angle of the nt sgnal. hereforefferent from the the - realletermnes the fnamental comonent of the nt sgnalhch one s comrehenebts amlte freencanhase angle. nfortnatelt s esrethat the generatesgnals bthe snchronng crct resent constant amlte. hsthe generatesgnals rocebthe E E can not be rectlse. n Fg. the sngle-hase s shon. ett follos a bref escrton nolng the strctre th the alemofcaton. he error sgnal e corresons to the total strbance beteen the nt sgnal an the generate one b the E. he feeback sgnals cos(t) ansn(t) are E e + / E Fg.. ngle-hase nhance. / t /9/$5. 9 IEEE

5 ref PLL (degrees) V(Volts) Tme(s) Fg. 8. Performance of the sngle-phase EPLL to track the nput sgnal ( ) ref PLL 4 (degrees) V(Volts) Tme(s) Fg. 9. Performance of the sngle-phase EPLL to track the nput sgnal ( ), when the phase angle ( ref ) s modfed from 45º to. blt sng the tme ntegral of ott of the - ontroller. he crct becomes stable onl f the aerage comonent of the error sgnal ereaches ero ale. nce ths crct s stablethe control sgnal E tracks the nt sgnal anas a conseencethe hase angle of the fnamental freenc s reache. Frther elanatons nolng the are resenten. n Fg. an Fg. are resentethe smlaton reslts th the same test cases aleto the sngle-hase. V. RA R he snchronng crcts ere mlementeon the eas nstrments FF D mcrorocessor. For memor rerements assessment arables se as measre. n able the arables nmber an se are shon an total memor sace emane for each snchronng crct s calclate. A R R R RR Memory Space Type Sngle-Phase PLL Enhanced PLL double (4 x ) 18 bts (6 x ) 19 bts long nt (14 x ) 448 bts (17 x ) 67 bts long nt array (64 x ) 48 bts - TOTAL 196 bts 864 bts The system voltage s sampled 64 tmes each grd perod. These nstantaneous values are stored n a 64 poston array, whch s used to create the 9 shfted sgnal used n the Sngle-Phase PLL. Ths causes the Sngle-Phase PLL 6V/dv 6V/dv 1A/dv memory requrements to be wder than the EPLL. Gven the vast amount of memory avalable n the selected mcroprocessor, ths matter has a small mportance. The processng speed of each synchronzng crcuts was also measured. Ths was made by countng the system clock cycles of the synchronzng crcut routne. The all control system has a 1.5 s avalable processng tme, actuatng 64 tmes by grd cycle. The DSP TMSF81F system clock frequency was set at 15MHz. The EPLL synchronzng crcut takes 197 system clock cycles, whch corresponds to 16.7 s. It occupes 5% of the control system routne avalable tme. The Three-Phase Adapted PLL takes 1511 system clock cycles, s, whch corresponds to 5.8% of the avalable processng tme. To evaluate performance characterstcs, the Seres Actve Condtoner was set to compensate the load voltage dstorton. For each proposed algorthm, the load voltage ( ) presents a 7.9% THD, and a RMS value of 1.V before compensaton. In Fg. 1 s shown the systems voltages and currents when the Condtoner starts wth the Sngle-Phase PLL. THD drops to.1%, and the RMS value rses to 114. V. In Fg. 11 s showed the same transent, beng the EPLL the synchronzng crcut. THD drops to.1% and RMS value s of 114. V. The two synchronzng crcuts present the same behavor n ths transent analyss. In both cases t can be seen that S rses, n order to regulate the DC lnk voltage. Another transent was appled to the system. It conssted n closng contactor C 1 (see Fg. 1,) thus connectng the shunt SeresConverterTurned on Fg. 1. Voltages and currents of the system when the Seres Actve Condtoner wth sngle-phase PLL s turned on. s s L L 6V/dv 6V/dv 1A/dv SeresConverterTurned on Fg. 11. Voltages and currents of the system when the Seres Actve Condtoner wth EPLL s turned on /9/$5. 9 IEEE

6 Sunteter Conneted rectfer to the system, wth the seres converter turned on. Ths acton would degrade THD to 8.8%, and the RMS value to 99.7V f there was no compensaton. In Fg. 1 can be seen the system voltages and currents when the rectfer s connected wth the Condtoner already compensatng, wth the Sngle-Phase PLL algorthm. It can be seen that v S becomes more dstorted, but mantans a low THD. It s of 1.8% and the RMS voltage s at 115 V. The same values where obtaned when the same transent was appled to the system wth the Condtoner compensatng usng the EPLL algorthm. Ths can be seen n Fg. 1. Snce the dstorton n ncreases, the seres converter has to nect more power n order to compensate t. Ths forces the shunt power converter of the Condtoner to dran more power to regulate the DC lnk. Thus, an ncreased system current ( S ) s also observed. Also, the compensated. THD s mproved when compared wth the frst analyss. Ths s due to the ncreasng of v ref that leads to a better modulaton ndex of the seres power converter. V. COCLSIOS s L 6V/dv 6V/dv 1A/dv Fg. 1. Seres Actve Condtoner wth Sngle-Phase PLL under the connecton of the shunt rectfer. Dot lne marks the connecton of the rectfer. A comparson between to synchronzng crcuts for the control algorthm of a Seres Actve Converter s made n ths paper. The Sngle-Phase PLL presents hgher memory requrements. ut gven the vast amount of memory avalable n the selected mcroprocessor, ths matter has a relatve mportance. Hs synchronzng crcut, however, presents s L 6V/dv 6V/dv 1A/dv Sunteter Conneted Fg. 1. Seres Actve Condtoner wth Sngle-Phase PLL under the connecton of the shunt rectfer. Dot lne marks the connecton of the rectfer. hgher speed performance. In a real tme processng control system, ths s an mportant advantage, snce t releases tme for other processng routnes. In ths partcular, the Sngle- Phase PLL can overtake the Enhanced PLL. Even though the EPLL uses less memory resources, ts processng tme s long. Thus, one can conclude that the Sngle-Phase PLL s more suted for real tme processng systems such as the one presented n ths paper. Expermental results also showed that the compensated load voltage ( ) delvered to the load s n accordance wth nternatonal standards that regulate harmonc dstorton and RMS value. These standards are CEI 61 and ASIIEEE for harmoncs. For RMS value, the standard taken n account s ASIIEEE , that descrbes power qualty problems. Ths was seen on both synchronzng crcuts. REFERECES 1 S. George, V. Agarwal, A DSP-ased Control Algorthm for Seres Actve Flter for Optmzed Compensaton nder onsnusodal and nbalanced Voltage Condtons, IEEE Transactons on Power Delvery, Vol., Issue 1, an. 7, pp-1. S. Dokc,. Mlanovc, M. McGranaghanD. Chapman, D. rschen, Shortfalls of exstng methods for classfcaton and presentaton of voltage reducton events, IEEE Transactons on Power Delvery, Vol., Issue, Aprl 5, pp osc. C. Costa, Rcardo L. Pregtzer, Tago. Sousa, osatsta, oo L. Afonso, A Case of Power ualty Assessment sng a Developed Power ualty Montor, CEE5 IEEE 1st Internatonal Conference on Electrcal Engneerng, Combra, Portugal, IS , 1 1 Out H. Akag,. anazawa, A. abae Generalzed theory of the Instantaneous reactve power n three-phase crcutsn Proc. IEEE IPEC - Toko, 198, pp M. Aredes, L. F. C. Montero,. M. Mguel, Control Strateges for Seres and Shunt Actve Flters, Power Tech Conference Proceedngs, IEEE ologna, Vol., 6 une, 6 pp. 6 L. F. C. Montero, M. Aredes,. A. Moor eto, A Control Strategy for nfed Power ualty Condtoner, IEEE Internatonal Symposum on Industral Electroncs, ISIE., Vol. 1, 9 11 une, pp A. F. C. Aquno et al, Synchronzng Crcuts Appled to on-lnear Loads, 4 IEEEPES Transmsson Dstrbuton Conference Center Conference Exposton, Latn Amerca, pp L. G.. Rolm, D. R. da Costa r., M. Aredes, Analyss and Software Implementaton of a Robust Synchronzng PLL Crcut ased on the pq Theory,IEEE Transactons on Industral Electroncs, Vol. 5, o. 6, December 6, pp M. arm-gharteman, M.R. Iravan, F. atrae, Extracton of sgnals for harmoncs, reactve current and network-unbalance compensaton, IEE Proceedngs Generaton, Transmsson and Dstrbuton, Vol. 15, Issue 1, 1 an. 5, pp M. arm-gharteman, M.R. Iravan, A onlnear Adaptve Flter for Onlne Sgnal Analyss n Power Systems Applcatons, IEEE Transactons on Power Delvery, Vol. 17, Issue, Aprl, pp M. arm-gharteman, M.R. Iravan, A new phase-locked loop (PLL) system, Proceedngs of the 44th IEEE 1 Mdwest Symposum on Crcuts and Systems, M SCAS 1, Vol. 1, Aug. 1, pp L. Afonso, H. R. Slva, lo Martns, Actve Flters for Power ualty Improvement, IEEE Power Tech1, 1-1 Set. 1, Porto, Portugal. 1 SemkronSuperfast PT-IGT Modules SM 5G6D Data Manual,September H. Akag, H. Futa, A ew Power Lne Condtoner for Harmonc Compensaton n Power Systems, IEEE Transactons on Power Delvery, Vol. 1, Issue, uly 1995, pp /9/$5. 9 IEEE 4