Reduction. CSCE 6730 Advanced VLSI Systems. Instructor: Saraju P. Mohanty, Ph. D. NOTE: The figures, text etc included in slides are

Transcription

1 Lecture e 8: Peak Power Reduction CSCE 6730 Advanced VLSI Systems Instructor: Saraju P. Mohanty, Ph. D. NOTE: The figures, text etc included in slides are borrowed from various books, websites, authors pages, and other sources for academic purpose only. The instructor does not claim any originality. 1

2 Introduction Outline of the talk Related work Target architecture Peak power model ILP Formulations Scheduling algorithm Experimental results Source: S. P. Mohanty and N. Ranganathan, "Simultaneous Peak and Average Power Minimization during Datapath Scheduling", IEEE Transactions on Circuits and Systems Part I (TCAS-I), Vol. 52, No. 6, June 2005, pp

3 Peak power? The peak power is the maximum power consumption of the circuit at any instance during its execution. 3

4 Why peak power reduction? Reduction of peak power consumption is essential : (i) to maintain supply voltage levels (ii) to increase reliability (iii) to use smaller heat sinks (iv) to make packaging g cheaper 4

5 Energy Vs Peak power efficient scheduling Fig. (a) Fig. (b) Fig.(a) is energy efficient schedule, whereas Fig.(b) is peak power efficient i schedule for same resource constraint t 5

6 Related work (Energy efficient scheduling using voltage reduction) Chang and Pedram [3], 1997 Dynamic programming Johnson and Roy [4], 1997 ILP based MOVER algorithm using multiple supply voltages Lin, Hwang and Wu [5], 1997 ILP and heuristic for variable voltages (VV) and multicycling (MC) Mohanty and Ranganathan [7], 2003 Heuristic based using multiple supply voltage and dynamic clocking 6

7 Related work (Peak Power efficient scheduling) Martin and Knight [6], 1996 Simultaneous assignment and scheduling. Raghunathan, Ravi and Raghunathan [10], 2001 data monitor operations in VHDL. Shiue [12], 2000 ILP based and modified force direct scheduling for peak power minimization. Shiue and Chakrabarti [13], ILP model to minimize peak power and area for single voltage. 7

8 Voltage, Frequency and Power Trade-offs (i) voltage reduction increase in delay (ii) frequency reduction reduction in power not energy (and increase in delay) Beyond of (i) and (ii) reduction of switching capacitance can be considered. 8

9 What is our approach? Adjust the frequency and reduce the supply voltage for peak power reduction during datapath scheduling. 9

10 Target architecture All functional units have one register each and one multiplexor. Each functional unit feeds one register only. The register and the multiplexor l operate at the same voltage level as that of the functional units. Level converters are used when a low-voltage functional unit is driving a high-voltage functional unit. Operational delay of a FU : (d FU +d Mux +d Reg +d Conv ). 10

11 Peak power model For a DFG let us assume : c = any control step or clock cycle in DFG N = total number of control steps in the DFG R c = number of resources active in step c (same as number of operations in step c) f c =cycle frequency for control step c c α i,c = switching at resource i active in step c C i,c = load capacitance of resource i active in step c V ic i,c =operating voltage of resource i active in step c 11

12 Peak power model. The power consumption for any control step c is given by, P c = i={1 Rc} α i,c C i,c V 2 i,c f c The peak power consumption of the DFG is the maximum power consumption over all the control steps, P peak = maximum( P c ) c={1 N} 12

13 Peak power model. Using the above two equations the peak power consumption of the DFG is described as, P peak = maximum ( i={1 Rc} α i,c C i,c V 2 i,c f c ) c={1 N} This would serve as an objective function for the scheduling algorithm. 13

14 ILP formulations for MVDFC : notations O : total number of operations in the DFG o i : any operation i, 1 <= i <= O F k,v : functional unit of type k operating at voltage level v M k,v :maximum number of functional units of type k operating at voltage level v S i : as soon as possible time stamp for the operation o i E i :as late as possible time stamp for the operation o i P(i,v,f) : power consumption of operation o i at voltage level v and operating frequency f x i,c,v,f : decision variable which takes the value of 1 if operation o i is scheduled in control step c using the functional unit F k,v and c has frequency f 14

15 ILP formulations for MVDFC. (i) Objective Function (ii) Uniqueness Constraints (iii) Precedence Constraints (iv) Resource Constraints (v) Frequency Constraints (vi) Peak Power Constraints 15

16 ILP formulations for MVDFC. Objective Function : Minimize (P peak ) Uniqueness Constraints : ensure that every operation o i is scheduled to one unique control step and represented as, i, 1 i O, Σ c Σ v Σ f x i,c,v,f =1 16

17 ILP formulations for MVDFC... Precedence Constraints : guarantee that for an operation o i, all its predecessors are scheduled in an earlier control step and its successors are scheduled in an later control step and are; i,j, o i belong to Pred(o j ), Σ vσ f Σ {d=s Ei}d x - Σ Σ Σ {d=s Ej}e x -1 Si i,c,v,f v f Sj j,c,v,f Resource Constraints t : make sure thatt no control step contains more than F k,v operations of type k operating at voltage v and are enforced as, c,1 c N and v, Σ {iεf k,v}σ f x i,c,v,f M k,v 17

18 ILP formulations for MVDFC. Frequency Constraints : lower operating voltage functional unit can't be scheduled in a higher frequency control step; these constraints are expressed as, i, 1 i O, c, 1 c N, if f < v, then x i,c,v,f =0. Peak Power Constraints : ensure that the maximum power consumption of the DFG does not exceed P peak for any control step and we enforce these constraints as follows, c, 1 c N and v, Σ {iεf k,v}σ f x i,c,v,f P(i,v,f) P peak 18

19 ILP formulations for MVMC : notations O : total number of operations in the DFG o i : any operation i, 1<= i <= O F k,v : functional unit of type k operating at voltage level v M k,v :maximum number of functional units of type k operating at voltage v S i : as soon as possible time stamp for the operation o i E i :as late as possible time stamp for the operation o i P(i,v,f clk ) : power consumption of operation o i at voltage level v and operating frequency f operating frequency f clk y i,v,l,m : decision variable which takes the value of 1 if operation o i is using the functional unit F k,v and scheduled in control steps l m,v L i,v : latency for operation o i using resource operating at voltage v (in terms of number of clock cycles) 19

20 ILP formulations for MVMC. (i) Objective Function (ii) Uniqueness Constraints (iii) Precedence Constraints (iv) Resource Constraints (v) Peak Power Constraints 20

21 ILP formulations for MVMC. Objective Function : Minimize (P peak ) Uniqueness Constraints : ensure that every operation o i is scheduled to one appropriate control step within the range (S i, E i ) and represented as, i, 1 i O, Σ v Σ {l=s y i (Si+Ei+1-Li v)} i,v,l,(l+l =1 iv-1) 21

22 ILP formulations for MVMC. Precedence Constraints : guarantee that for an operation o i, all its predecessors are scheduled in an earlier control step and its successors are scheduled in an later control step and are; i,j, o i belong to Pred(o j ), Σ v Σ {l=s i Ei}(l+L i,v -1)y i,v,l,(l+li,v-1) - Σ v Σ {l=s j Ej}l y j,v,l,(l+l j,v-1) -1 22

23 ILP formulations for MVMC. Resource Constraints : make sure that no control step contains more than F k,v operations of type k operating at voltage v and are enforced as, Σ {iεf k,v}σσ l y i,v,l,(l+l M i,v-1) k,v Peak Power Constraints : ensure that the maximum power consumption of the DFG does not exceed P peak for any control step and we enforce these constraints t as follows, for all c, 1 c N and for all v, Σ {iεf k,v}σ Σ v y i,v,l,(l+l P(i,v,f i,v-1) clk ) P peak 23

24 Scheduling algorithm Input : (i) unscheduled d DFG (ii) () resource constraints (iii) number of voltage levels (iv) number of frequencies (v) delay of resources Output : scheduled DFG, f base, N, cfi c, power estimates 24

25 Scheduling algorithm. Step 1: Find ASAP schedule of the UDFG. Step 2: Find ALAP schedule of the UDFG Step 3: Determine the mobility graphs for each node. Step 4: Modify the mobility graph for MVMC scheme. Step 5: Calculate operating frequency of afuusing delay model. Step 6: Construct the ILP formulations of the DFG Step 7: Solve the ILP formulations using LP-Solve. Step 8: Obtain the scheduled DFG. Step 9: Determine f c,f base and cfi c for MVDFC scheme. 25

26 Scheduling for MVDFC Example DFG (for RC1) 26

27 Scheduling for MVMC Example DFG (for RC1) 27

28 Experimental results : benchmarks 1. Example circuit it (EXP) (8 nodes, 3*, 3+, 9 edges) 2. FIR filter (11 nodes, 5*, 4+, 19 edges) 3. IIR filter (11 nodes, 5*, 4+, 19 edges) 4. HAL differential equation solver (13 nodes, 6*, 2+, 2-, 1 <, 16 edges) 5. Auto-Regressive filter (ARF) (15 nodes, 5*, 8+, 19 edges ) 28

29 Experimental results : resource constraints Multipliers ALUs 3.3V 5.0V 3.3V 5.0V Serial No RC RC RC RC RC5 29

30 Experimental results : notations P S : the peak power consumption (in mw) for single supply voltage and single frequency operation (SVSF) P DFC : the peak power consumption (in mw) for MVDFC operation P MC : the peak power consumption (in mw) for multiple supply voltages and multicycle operation PDP S : the power delay product (in nj) for SVSF operation PDP DFC : the power delay product (in nj) for MVDFC operation PDP MC : the power delay product (in nj) for MVMC operation P DFC = (P S - P DFC ) /P S * 100 : % peak power reduction for MVDFC P MC =(P S -P MC )/P S * 100 : % peak power reduction for MVMC PDP DFC = (PDP S - PDP DFC )/PDP S * 100 : % PDP reduction for MVDFC PDP MC = (PDP S - PDP MC ) /PDP S * 100 : % PDP reduction for MVMC 30

31 E X P Experimental results : (% reduction) RCs ΔP DFC ΔP MC ΔPDP DFC ΔPDP MC F I R I I R H A L

32 Percentage average reduction Average pe eak power reduc ction (%) > MVDFC 70 MVDFC (a) Different benchmark circuits > Different benchmark circuits > Average e PDP reduction (%) > (b) ion (%) > Average peak power reducti MVMC 25 MVMC (c) Different benchmark circuits > Different benchmark circuits > Average PDP reduction (%) > (d) 32

33 Reductions using different schedulers Benchmark Circuits MVDFC MVMC Shiue[12] Martin[6] Raghunathan[10] (2) FIR (4)HAL (5)ARF

34 Reduction of peak power is essential. Conclusions This paper describes peak power reduction schemes at behavioral level through datapath scheduling. The scheduling schemes use ILP based minimization for MVDFC and MVMC mode of circuit design. For both the modes the scheduler could achieve significant peak power reduction. For some resource constraints there is increase in PDP for MVMC mode design. The scheduling schemes are useful for data intensive applications. The applicability of the scheduling schemes for pipelining is to be investigated. The effect of switching activity is to be taken into account. The detail design of controller is to be done. The effect on clock network is to be studied. 34