Modeling of nonlinearities in MMC stations for real-time and offline simulation

Transcription

1 1 Modelng of nonlneartes n MMC statons for real-tme and offlne smulaton S. Dennetère, H. Saad, J. Mahseredjan, T. Ould-Bachr Abstract Multlevel Modular Converters (MMCs) are used n several HVDC projects around the world. Several hundreds of levels are commonly used n MMCs. Detaled modelng of converters has been demonstrated n offlne and real-tme tools, but several solutons are stll under development to mprove accuracy and performance of models. Ths paper focuses on modelng of nonlnear components n MMC staton: surge arresters, transformer magnetzaton and swtchng valves. It presents an MMC based benchmark for demonstratng accuracy needs n the smulaton of MMC statons wth nonlneartes. The proposed benchmark s used to valdate real-tme smulaton results n comparson wth EMT offlne solutons. It shows the compromse between computaton speed for real-tme constrant and smulaton accuracy n the presence of nonlnear devces. Index Terms Real-tme smulaton, nonlnear systems, HVDC, Modular multlevel converter (MMC), Voltage-Source Converter (VSC). T I. INTRODUCTION he modular multlevel converter (MMC) topology offers sgnfcant benefts compared to prevous voltage source converter (VSC) technologes. To study the global performance of MMCs n a grd, real-tme smulaton tools wth actual controllers n the loop (Hardware In the Loop HIL) are frequently used by HVDC manufacturers and owners. The man advantage of real-tme smulaton n ths context s to valdate the real controllers under varous network condtons. MMC modelng n electromagnetc transent type (EMTtype) tools s very challengng, because of the large number of semconductors used n such converters. Ths constrant usually mposes numercal ntegraton tme steps of a few µs and large amounts of I/Os. Several MMC models for EMT studes are presented n [1]. MMC models for real-tme smulaton are proposed n [2]-[8]. Compared to EMT offlne smulaton, HIL smulaton offers great opportuntes for performng detaled EMT studes wth actual controls. But real-tme electromagnetc transent smulaton has always been a compromse between computaton speed for real-tme constrant and smulaton accuracy. As a consequence, nonlneartes are often neglected or smplfed to meet the realtme constrant especally when small tme steps are used. In most real-tme applcatons wth HVDC controls, ths smplfcaton s acceptable. For nstance, the nonlnear characterstcs of surge arresters are usually not modeled n the real-tme smulaton of HVDC-LCC (Lne Commutated Converter) type controls, snce they have lmted mpact durng ac and dc faults. Ths s not necessary the case for HVDC-MMC lnk. Modelng MMCs n real-tme has been addressed n many S. Dennetère and H. Saad are wth RTE (Réseau de Transport d'electrcté), Pars France, J. Mahseredjan s wth Polytechnque Montréal, Canada T. Ould-Bachr s wth OPAL-RT Technologes, Montréal, Canada. Emal of correspondng author : sebasten.dennetere@rte-france.com papers, however, to the authors best knowledge, the nonlnear characterstcs of components n MMC-HVDC lnks have not been accounted for and ther mpact on smulaton accuracy has not been analyzed. Ths paper presents an MMC-HVDC lnk benchmark for analyzng accuracy ssues under varous condtons. Valdaton s based on an accurate offlne EMT-type teratve solver. It s shown that wthout teratons, real-tme smulaton results may become less accurate, but the teratve soluton requres more computng tme and consequently there s a tradeoff between accuracy and computng tme. Ths ssue s especally complex when actual MMC controls are nserted n the smulaton loop because they requre very small tme steps. Ths s due to the hgh samplng rates of controllers used to effcently balance capactor voltages of hundreds of submodules n each arm. Models mplemented on FPGA boards are usually requred n ths context. A mxed platform composed of FPGA and CPU ncreases further the complexty of real tme smulaton. The communcaton latency between CPU and FPGA may lead to numercal ssues and compromse model accuracy. Ths paper proposes and tests smplfcatons (compromses) to accurately solve MMCs on such platforms. The man compromse s to avod teratons to solve swtchng states n converter arms. Part of the work presented n ths paper has been performed n the context of the INELFE (France-Span ELectrcal INterconnecton) nterconnecton. Ths 2, MW nterconnecton s composed of 2 parallel HVDC-VSC lnks ncludng 4 XLPE cables (64.5 km long each). Ths paper starts wth a descrpton of nonlnear devces nvolved n an MMC staton. The proposed arm model swtchng state calculaton smplfcatons for avodng teratons n real-tme, are presented next. A bref overvew on teratve soluton technques presently avalable n real-tme smulaton tools s presented n secton III. Secton IV provdes practcal test cases that demonstrate the mpact of accurate modelng of nonlnear devces n converter statons. II. NONLINEARITIES IN MMC STATIONS A smplfed sngle lne dagram of an HVDC lnk composed of 2 MMC converters and dc cables s presented n Fg. 1. M1A Y RA1 BP_RA1 CB_SPRA1 SPRA1 HVDC lnk BP_RB1 SPRB1 Fg. 1 Smplfed sngle lne dagram of an HVDC lnk wth MMC - Paper submtted to the Internatonal Conference on Power Systems Transents (IPST217) n Seoul, Republc of Korea June 26-29, 217 RB1 CB_SPRB1 Y M1B

2 2 The number of I/O sgnals and the samplng rates used by the VSC controllers are the man constrants mposed on real-tme smulators. For one HVDC lnk smlar to the INELFE nterconnecton, the number of I/O sgnals s greater than 1,. The samplng tme for low level controls s below 1µs for such converters as explaned n [2]. The samplng tme plays an mportant role on the dynamc performance of the system. A. Swtchng devces 1) MMC models for EMT smulatons Varous EMT-type models for MMCs have been presented n [1]. Model 1 s the most detaled. It models the nonlnear characterstcs of dodes and IGBTs, requres an teratve solver and consequently causes very hgh computng tmes. Ths model s not sutable for real-tme smulaton, but t can be used to valdate and calbrate smplfed models. Model 2 [1] avods the nonlnear IGBT and dode models through the usage of swtchable resstances (Ron/Roff). Ths approach allows performng a converter arm crcut reducton for elmnatng nternal electrcal nodes and uses a Norton equvalent for each MMC arm. The model stll consders each submodule (SM) separately and mantans a record for each ndvdual capactor voltage. In [1] and [3] an teratve process s actvated durng the SM blockng state to obtan accurate results. EMT studes wth detaled controls can be performed wth ths type of model. For MMCs wth large number of levels (251 levels and more), the calculaton tme step shall be smaller than 15µs [2] to respect the smallest tme nterval between two dfferent levels and actual low level controllers usually need a samplng rate below 1µs. In Model 3 [1] each arm s averaged usng the swtchng functon concept of a half brdge converter. Ths model assumes that capactor voltages of each arm are perfectly balanced. Realtme mplementaton of ths type of model has been proposed n [6] and [7]. Second harmonc crculatng current controllers can be tested wth ths type of model. But t s not possble to test capactor voltage balancng controllers. Some solutons have been proposed to mplement Model 3 nterfaced wth detaled arm model to overcome ths lmtaton [9]. Model 4 [1] s the classcal average value model. It s not sutable for nterfacng wth real MMC controls because several controls loops cannot be tested wth ths type of model. 2) MMC models for real-tme smulaton Model 2 s currently the best canddate for real-tme mplementaton on CPU and FPGA. Due to tme-step constrants mposed by real-controllers to effcently balance capactor voltages, FPGA mplementaton s requred. Accurate solutons must be found wthout teratons wth the electrcal network nodal equatons. These constrants are analyzed n ths secton. A Model 2 mplementaton for real-tme s proposed n [2] but t does not support the blockng state. A Model 2 mplementaton s also proposed n [3], but teratons wth the nodal equatons are requred to get correct results. Implementaton on FPGA of ths soluton s not feasble wth the currently avalable hardware technologes due to communcaton latency between CPU (electrcal crcut nodal soluton) and FPGA (arm model). The computaton of ON/OFF states s a straghtforward process snce only gate sgnal values are requred. When the blocked state s set (.e. no gate sgnal s sent to IGBT), only the freewheelng dodes can conduct. The dode conducton states depend on voltage and current varables. The dscontnutes n state varables due to the blocked state can cause numercal oscllatons. Ths ssue s addressed through an teratve process for offlne smulaton n [1]. To apply a smlar teratve process n real-tme, CPU mplementaton cannot currently meet the calculaton tme constrants. FPGA mplementaton s requred. But FPGA mplementaton must nclude all component models n the converter staton wth the soluton of nodal equatons and refactorzaton at each soluton tme-pont. New hgh performance sparse matrx solvers have been proposed on FPGA [1], but mplementaton of such computatonally demandng EMT models on FPGA remans complex and requres further research. A non-teratve approach s proposed below. The SM states for blockng mode are presented n Fg. 2. When the arm current s postve, the dode D1 conducts and the SM s n ON state. The dode D2 voltage s postve and equal to the capactor voltage. When the current decreases and crosses zero, D1 stops conductng. Then, dependng on D2 voltage, D2 can conduct (the SM s n OFF state) or stay n blocked state (the SM s n hgh mpedance HZ state). Durng ths commutaton, the D2 voltage waveform and ts mpact on D2 state change depend on many parameters such as the external crcut connected to the arm (arm nductance, cables ) and the rate of rse of the arm current. In some cases, the SM goes from ON state to OFF state wthout passng n HZ state. In other cases, the SM goes from ON state, to HZ state for few ms and then goes to OFF state. D1 I arm > I arm < I arm = D2 State ON State OFF State HZ Fg. 2 SM states for blockng mode When teratons are not performed to fnd the correct state, a soluton s to force the arm current used to update the model, to zero durng one tme-step when current crosses zero. Ths s equvalent to forcng the HZ state durng one tme-step. Ths soluton has been mplemented n the paper. The dscretzed equvalent crcut for each SM s presented n Fg. 3 (see also [1]). The state of each submodule s selected based on arm current drecton and dode voltages (V D1 and V D2 ). Therefore ths selecton can be determned from arm current I arm and the equvalent current hstory source of capactor I c h. The arm model s reduced nto a Norton equvalent (R n(t), I n(t)) as presented n [1], and updated at each soluton tme pont based on the calculaton of each ndvdual cell. When the zero current crossng s detected, the arm current D1 D2 D1 D2

3 3 s set to zero. Ths settng forces all SMs n the arm to be n HZ state. The followng steps are performed at each tme-step for the proposed model: 1. Get Pulses(t) and V arm(t) 2. I arm(t) = V arm(t)/r n(t- t) I n(t- t) 3. If at least 1 SM s blocked goto 4, else goto 6 4. If I arm(t)*i arm(t- t)> goto 6, else goto 5 5. I arm(t)= 6. For each SM: select state based on I arm(t) and I ch (t- t) 7. Solve nodal equatons, next tme step and goto 1 Step 3 s only done when the arm was not n HZ state at the prevous tme pont and when the arm was blocked (no pulse receved). I arm(t) D 1 C I arm(t) V D1 R 1 R c I c h (t- t) Current (A) Fg. 5 Arm current of the smple test case n Fg. 4 Current (A) Proposed model 1µs Current reversal EMTP Model 2 and proposed model EMTP Model 1µs Proposed model 3µs D 2 V D2 R Fg. 6 Arm current (Zoom of Fg. 5) durng blockng state Fg. 3 Dscretzed equvalent crcut for th submodule The reduced voltage (32 V, 5 Hz) test system presented n Fg. 4 s used to compare the smulaton results of the proposed arm model aganst the offlne EMTP Model 2 presented n [1] whch ncludes an teratve process. In Model 2 the trapezodal ntegraton rule s swtched to the Backward Euler (BE) method for the next tme pont soluton for elmnatng numercal oscllatons [11] caused by dscontnutes n trapezodal ntegraton. EMTP Model 2 s the reference model used to valdate the proposed model. In Fg. 4, the arm s composed of 5 submodules. The proposed model uses the BE ntegraton method wth a 3 µs tme step n ths case. BE s used here to avod numercal oscllatons and t s suffcently accurate when the ntegraton tme step s small. Ls R1 Iarm 5mH 1 AC_5Hz 32 /_ 1 R2 Control Fg. 4 Smple test crcut for comparng arm models X 5 The arm s de-blocked between t=.1s and t=.2s. The arm current s presented n Fg. 5 and Fg. 6. The voltage of the frst capactor s presented n Fg. 7. C Ron = 1e-3 W Roff = 1e6W C = 7.5 mf Voltage (V) Fg. 7 Voltage of the frst capactor Both models gve smlar results. The only dfferences are notceable at zero current crossng (small spke), as presented n Fg. 6. When current reversal s detected, the arm current used n the arm model s set to zero to quckly account for state change (from ON/OFF to HZ) n the calculaton of I c h. The arm current resultng from the Norton equvalent provded to the nodal soluton s not zero because t s deduced from the nodal soluton at the prevous tme step. Fg. 6 compares smulaton results performed wth 3µs and 1µs tme steps. It demonstrates that when the tme step s smaller, the soluton s more accurate, as expected. B. Surge arresters Surge arresters are located on the dc and ac sdes. The dc sde arresters are shown n Fg. 8. When dc fault occurs at converter termnal (see fault locaton n Fg. 8), pole-to-ground overvoltage on the healthy pole can be observed due to the converter topology. Sde A EMTP Model 2 and proposed model A B Sde B - A- B- Fg. 8 Pole-to-ground fault locaton and dc sde arresters Due to the symmetrcal monopole confguraton, no

4 4 reference to ground s avalable on the dc sde. A ground fault on one pole wll shft the other pole to about twce the dc voltage. To lmt the overvoltage on the healthy pole, the followng soluton s usually mplemented (see Fg. 8). Frst, the severe healthy pole overvoltage s lmted by surge arresters nstalled on the dc pole bus as explaned n [12]. These specal surge arresters have a very hgh energy absorpton capablty because the overvoltage can last several tens of ms. Ths transent s smlar to a temporary overvoltage because t lasts 2-5 cycles. Second, the converters are blocked mmedately (~ 4 µs after fault detecton) and the ac crcut breakers at pont of connecton (pont of common couplng - PCC) are opened after 2-5 cycles. The surge arresters are desgned to lmt the dc overvoltages and absorb a sgnfcant amount of energy before the ac crcut breaker openng. Large currents are drven to ground by the surge arresters when lmtng the dc overvoltages. The protecton levels of arresters for ths applcaton are typcally around 1.8 pu. For testng actual (real) controls wth dc faults, the surge arresters must be modeled. Ths need ncreases the real tme smulaton complexty because a tme step typcally smaller than 3µs (due to the controller samplng rate) must be used and the nonlnear characterstcs of surge arresters must be treated wth teratons. The presented test case (see Fg. 1) ncludes delta connecton on secondary sde of transformers. Some VSC solutons [13] use Y/Y confguraton (nstead of Y/D) where the convertersde star pont s ungrounded. In ths case, pole-to-ground faults lead to overvoltages at cable termnals and also at the converter sde star pont of transformer, whch s protected by a surge arrester. As a consequence, smlar numercal challenges exst n ths confguraton and the mpact on accuracy of the teraton solver wth surge arrester s addressed n the next secton. C. Transformer saturaton HVDC converter statons consst of power converters, transformers, cables/lnes and flters (n some cases) are characterzed by low mpedance paths. When converter statons are energzed, they may cause a large nrush current due to capactor chargng and energzaton of transformer and cables. Ths results n system voltage dstorton, undesred harmoncs and overvoltages leadng to potental malfunctonng of protecton equpment, equpment falures and non-complance wth the grd codes. Inserton resstors are usually nstalled to lmt nrush currents durng converter energzaton. In [14] pre-nserton resstors are nstalled on the grd sde (prmary sde of converter transformers) to lmt transformer and capactor nrush currents. In the proposed test system, the pre-nserton resstors are nstalled on the converter sde (see RA1 and RB1 n Fg. 1). Ths soluton s effectve to lmt capactor nrush currents, but not transformer nrush currents. The Pont-On-Wave (POW) controllers s mplemented on the ac crcut breakers (M1A and M1B n Fg. 1). Ths soluton can provde several techncal and economc benefts, but may not be relable on the long term to lmt nrush currents (controller falure, varaton of the crcut breaker mechancal performances ). In the proposed test case (Fg. 1), converter transformers are composed of 3 sngle phase unts of 35 MVA each. Each sngle phase unt has 2 wound legs and 2 unwound legs. Ths type of core provdes a magnetc path for zero sequence flux, but can have remanent flux when the transformers are swtched off. The POW controllers mplemented on ste do not take nto account remanent flux n the calculaton of the swtchng tmes [17]. That s why the HVDC control and protecton systems must be tested by takng nto account hgh nrush currents. Therefore, magnetzaton branch of transformer, should be ncluded n the model to study such nrush current. D. Hgh mpedance groundng devces Hgh mpedance groundng devces (named star pont reactor n the present converter staton) are nstalled between transformer secondary sde and ac sde of converter arms to provde a reference to ground. Ths equpment does not provde a strong reference to ground, because ts mpedance s very hgh (several thousand of Henry) but t can be used to detect any voltage unbalance generated by a dc fault [12]. In some cases (hgh mpedance dc fault analyss) the saturaton of ths devce must be modeled. III. ITERATIVE SOLUTIONS FOR NONLINEAR FUNCTIONS IN REAL-TIME SIMULATIONS Ths secton brefly descrbes the numercal technques used to solve nonlneartes n real-tme smulaton tools. These technques have been recently mplemented n the emegasm [18]-[19] and Hypersm [2] real-tme smulators. Smulaton results have been compared and valdated aganst results gven by the offlne smulaton tool EMTP [22]. EMTP uses a fully teratve and smultaneous solver for all nonlneartes. Snce transmsson lnes ntroduce decouplng n the network soluton, the subnetworks separated by transmsson lnes can be dentfed and solved ndependently. Ths s the tradtonal method to perform parallel processng n real-tme. Hypersm and emegasm tools provde an teratve solver adapted to real-tme smulaton. They use an teratve setup wthn each subnetwork that ncludes nonlnear models. Surge arresters are modeled by pecewse lnear resstors. Each segment j s represented by a lnear equaton of current j as a functon of voltage v j: j K jv j IN j whch defnes a Norton equvalent wth admttance K j and Norton current source I Nj. Nonlnear devces are requred to return ther dscretzed Norton equvalent through lnearzaton at the gven operatng pont for each teraton. After each nodal soluton, the nonlnear models retreve back ther voltages to dentfy whch segment of the nonlnear characterstc s actve. If the current segment s dfferent than the prevous one, the nodal admttance matrx of the subnetwork s updated wth the new segment and re-factorzed wthn. The Norton current vector s updated as well. The teratve process ends when convergence s acheved. When the teraton process requres

5 5 too much tme for real-tme smulaton, mtgaton solutons must be used, such as reducng the convergence precson condton n order to decrease the number of teratons and meet the real-tme constrant. emegasm uses a combned State- Space Nodal Method proposed n [18] to account for nonlneartes. FPGA Arm model Sgnals to CPU: 6 Rth, 6Vth Sgnals from CPU: 6 nb of SM nserted, 6 Iarm t =1.25µs Balancng algorthm t =5µs Control system model t =2µs CPU CPU IV. TEST CASES ON A REAL MMC INSTALLATION The France Span HVDC nterconnecton s used here as an applcaton example. Converter, transformer and cable data s avalable n [15]. Surge arrester data s provded n [16]. As explaned n [2], real-tme smulaton of MMC models wth more than 161 levels can only be acheved wth FPGAbased models due to computaton effort. The arm model presented n secton II.A.2) has been mplemented on an FPGA and ntegrated nto the Hypersm platform. Real-tme smulaton requrements are fulflled here for a 41 level converter. To model converters wth such hgh number of levels, gatng sgnals cannot be generated on a CPU due to the number of I/Os and the latency between CPU and FPGA. The soluton s to mplement the balancng algorthm that generates the gatng sgnals on an FPGA. It can be mplemented on the same FPGA used for the valve models or on an addtonal FPGA (actual controller). Ths soluton has been ntally tested n [2] and mproved n [21]. It drastcally reduces the number of I/Os and makes the nterface much smpler on the CPU. Only 6 reference voltages are sent to the FPGA by the CPU at each tme step. Ths lmted number of I/Os enables the use of smaller tme steps on CPU and thus modelng of converters wth hgh numbers of levels. The smulaton setup for 1 converter staton s presented n Fg. 9. The complete setup s composed of 2 converter statons and 2 dc cables. The converter model s solved on CPU wth a 2µs tme step (trapezodal ntegraton method). The arm models are solved on FPGA wth a 1.25µs tme step and usng Norton equvalent (or Thevenn equvalent). The balancng algorthm s executed on FPGA at 5µs. The electrcal crcut solved on CPU s ndependent from the number of submodules n each arm. The conclusons drawn n ths paper regardng the modelng of the presented system wthnonlneartes, are applcable to converters wth varous numbers of levels. A total of 11 surge arresters are modeled wth nonlnear resstors. The nonlnear characterstcs are composed of 1 segments. The characterstcs of the surge arrester connected to the dc cables are provded n [16]. CPU AC Grd Data acquston synchronzed on CPU tme step CPU Tme step : 2 µs Executon tme for models and nodal soluton (2-15µs) PCI/E communcaton bus Data processng wth IOs Fg. 9 - Converter staton model mplemented n Hypersm (CPU and FPGA) A. Converter startng sequence Converter model The start-up process of the MMC conssts n chargng equally all the capactors before beng able to operate. Moreover, current and voltage stresses n the power swtches and on the ac grd have to be lmted durng start-up [23]. The frst step of the startng sequence s the passve energzaton of the converter staton and the dc cables. The sum of capactor voltages n upper arm phase-a s presented n Fg. 1 : 1. ac crcut breaker (M1A) closng at t=.1s 2. nserton of resstor RA1 bypass at t=.5s. 3. ac crcut breaker M1B closng at t=2s. 4. nserton of resstor RB1 bypass at t=4s. 5. converter de-blockng, send pulses to control dc voltage and start full power transmsson at t=3s. The start-up sequence s a relevant test case to valdate the arm model and especally the blocked state condton. The upper arm current n phase-a of converter Sde A s presented n Fg. 12. Smulaton results are smlar between the proposed model (wthout teratons) and the offlne model (wth teratons). The mpact of the proposed arm model smplfcaton durng current zero crossng s neglgble durng the start-up sequence. The dfferences between real-tme and offlne results are dentfed wth the letter (relatve error).

6 HYPERSIM Real-tme 1 <2% EMTP Offlne Fg. 1 Sum of capactor voltage n upper arm durng startng sequence <.1% HYPERSIM Real-tme <.1% EMTP Offlne Fg. 11 Sum of capactor voltage n upper arm durng startng sequence (Zoom) Current (ka) 5 <.2% <1% <4% HYPERSIM Real-tme EMTP Offlne Fg. 12 Lower arm phase-a current durng start-up sequence B. DC bus faults <.1% <.1% <3% <.2% <.2% The objectve of ths secton s to analyse DC pole to ground fault wth converter blockng and surge arresters. The pole to ground fault presented n Fg. 8 s smulated wth surge arresters ncluded and the converter s blocked when the dc fault s detected. The MMC Sde-A converter s blocked 6.18 ms after fault gnton (over-current protecton) and ac crcut breakers are opened 2 cycles later. The system presented n Fg. 9 s confgured n the STATCOM mode (.e. dc cable dsconnected only Sde A smulated) n order to get faster decrease n the non-faulty pole-to-ground voltage. Ths s the worst case n terms of rate of change for overvoltages. Ths confguraton n STATCOM mode has no mpact on smulaton performance because both sdes are smulated on separated hardware (CPU and FPGA). Ths test case s mplemented n real-tme and n offlne wth controls n the smulaton loop. The controls are dentcal n both smulaton tools. The followng results are compared: EMTP results wth arm and surge arrester models solved wth teratons Hypersm results wth only surge arrester solved wth teratons (Norton equvalent for each arm s kept constant for each teraton, only surge arrester segments are changed); Hypersm results wthout any teraton. The voltages on the healthy pole are presented n Fg. 13 and Fg. 14. The teratve soluton of nonlnear characterstcs necesstates ncreased computng efforts. For the test system presented n the paper (lnk or STATCOM confguraton) the teratve process requres 3 tmes more computng tme than a soluton wthout teratons. The executon tme of the test case wth the startng sequence followed by a pole-to ground fault s presented n Fg <1% -6 <.5% HYPERSIM Real-tme <.5% EMTP Offlne Fg. 13 DC voltage at converter termnals (healthy pole) durng pole-to-ground fault Comparson offlne vs real-tme wth teratons Fg. 14 DC voltage at converter termnals (healthy pole) durng pole-to-ground fault Comparson offlne vs real-tme wthout teratons <5% <3% <2% Fg. 15 Executon tme n Hypersm wth teratons Executon Tme (µs)1 It s shown that wthout teratons, the overvoltage s over estmated by 3%, but the teratve soluton requres more computng tme. In the proposed test case, t s ncreased by a factor of 3 wthout leadng to over-run n real-tme smulaton. There s a tradeoff between accuracy and computng tme. In the proposed case, even f the smulaton results are less accurate wthout teratons, they can be consdered acceptable for many HIL applcatons. The naccurate computaton of overvoltages may, however, mpact on the overvoltage protecton system and produce erroneous results. V. CONCLUSIONS 5 teratons <.5% 5 teratons 3 teratons <1% HYPERSIM Real-tme EMTP Offlne Study of MMC modelng ncludng the nonlnear characterstcs of components has been addressed n ths paper. Ths paper descrbes and nvestgate the nonlneartes that must be taken nto account n MMC staton modelng. The proposed benchmark wth ts generc data s based on a real HVDC-VSC project. Ths paper proposes and tests converter arm model smplfcatons (compromses) to accurately solve MMCs n real-tme smulaton tools. These compromses are mandatory to avod teratons on mxed CPU-FPGA platforms wthn the requred tme-step lmtatons. The provded practcal test cases

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