Full Bridge MMC Converter Optimal Design to HVDC Operational Requirements

Transcription

1 .9/TPWRD.5.475, IEEE Transactons on Power Delvery Full Brdge Converter Optmal Desgn to HDC Operatonal Requrements Wexng Ln, Member IEEE, Dragan Jovcc, Senor Member, IEEE, Samuel guefeu, Member, IEEE, and Han Saad, Member, IEEE Abstract Desgn and operaton of (full brdge) that meets HDC specfcatons are studed n ths paper. Three new desgn parameters: the over-modulaton ndex (), the DC modulaton ndex (Mdc), the mnmal DC voltage (mnpu) are ntroduced to specfy the operaton of a. Power ncrease and semconductor count ncrease wth the ncrease of s analyzed to understand benefts of over-modulaton. The requred number of submodules and the number of more-costly submodules for specfed rated dc voltage, mnpu and are calculated. The relatonshp of the submodule nsertng logc and dynamcs of an arm s analyzed. The submodule voltage balancng s studed and the constrants on the requred number of submodules are deduced. The capablty of over-modulaton and the operaton under low DC voltage wth optmal submodule count are verfed usng EMTP smulaton. Index Terms AC-DC power converson, DC power systems, DC power transmsson, HDC converters, HDC transmsson I. ITRODUCTIO The -level and -level PC technologes domnated the SC-HDC market snce untl the recent emergence of modular multlevel converter () []-[]. The modular structure enables seres connecton of submodules, rather than IGBTs whch elmnates ssues wth the swtchng losses and harmoncs caused by smultaneously trggerng of large number of IGBTs at khz frequency. Furthermore s able to theoretcally acheve any level of DC voltage ratng usng basc submodules bult wth standard IGBTs. The (half-brdge) converter has become the only commercally avalable SC-HDC technology []-[6]. All the exstng SC-HDC lnks, except Caprv lnk, operate wth DC cables. Wth the rapd development of technology, also becomes canddate for the over-head lne transmsson [6]-[8]. Because of very frequent DC faults on overhead lnes, whch are typcally transent n nature, common s not sutable. The possble mult-termnal connecton and prospect of DC grds s another mportant applcaton area whch calls for mprovements n technology. Several topologes of DC fault tolerant have been reported n the lterature [9] -[8], such as the usng the clamp double submodules [9], the hybrd cascaded multlevel converter (HCMC) [], the alternate arm converter[], a Ths project s funded by RTE, Pars, France. W. Ln and D. Jovcc are wth the School of Engneerng, Unversty of Aberdeen, AB4 UE, U.K. (wexngln@abdn.ac.uk, d.jovcc@abdn.ac.uk ). S. guefeu and H. Saad are wth the Réseau de Transport d Electrcté, Pars 99, France (samuel.nguefeu@rte-france.com, han.saad@rte-france.com ) seres connected double sub-module[], the cross-connected half-brdge submodules [], the hybrd wth submodules at the DC sde and submodules at the AC sde[4]-[5], the based on unpolar voltage full-brdge SM and three-level cross-connected SM [6], the based on (full brdge) submodules [9], [7]-[8] and the wth mxed submodules and submodules [9]-[]. Among all these DC fault tolerant s, the based on submodules (ncludng the mxed submodules ) s the only commercally avalable fault tolerant technology for HDC applcaton. Apart from the DC fault tolerant property, the - also has the advantages of operaton wth low DC voltage and the ablty to generate hgher AC voltage for a gven DC voltage lmt. Some recent researches have studed - [7]-[] but there s no analytcal desgn method for mportant parameters of, lke the number of submodules or the number of submodules. Also generc submodule balancng requrement has not been studed for the mpact on converter parameters. Ths study ams to derve optmal desgn prncples for assumng that HDC operatng condtons are specfed lke, operatng DC voltage range, and requred AC voltage magntude for a restrcted DC voltage level. Also the study explores submodule balancng methods and attempts to derve mnmal number of submodules consderng that costs and losses of submodules are much hgher than wth submodules. Ths study wll facltate development of electrcal and cost models, and understandng of operatng lmts. II. PERFORMACE SPECIFICATIO FOR A. Over-modulaton requrement Fg. shows crcut dagram of one phase of a -. Each arm s composed of a seres connecton of submodules and submodules. Such topology s named mxed cells n [9] or hybrd n []-[]. As t wll be demonstrated n the paper, such requres most of ts submodules to be of - type f t s desred to operate under low or negatve DC voltage. It wll also be shown that under practcal HDC demands, t s not expected that converter wll have % cells. The studed converter s therefore an optmzed verson of a whch wll be used n practcal HDC, and hence label s retaned through the artcle. submodules enable over-modulaton, whch produces hgher AC voltage for a gven DC voltage, compared wth. The over-modulaton s defned by parameter k, (c) 5 IEEE. Personal use s permtted, but republcaton/redstrbuton requres IEEE permsson. See

2 .9/TPWRD.5.475, IEEE Transactons on Power Delvery where the case k = corresponds to AC voltage generated by. The converter AC voltage s defned as: arm _ dc v M cos( t v ) () where arm_dc s the arm DC voltage whch s same as nomnal DC voltage ( arm_dc= d) under all steady-state condtons, consdered n ths study. Dynamcally however arm voltage s not dentcal to DC voltage because of DC-sde modulaton. The AC-sde modulaton ndex M and phase angle θ v of () (M d and M q n DQ frame) are the same as wth : M v From () the AC voltage v falls wthn the followng range: () arm _ dc arm _ dc v () The voltages of the upper and lower arm are respectvely denoted as v p and v n. eglectng the voltage drops on the arm nductors and resstances, from Fg. the crcut equatons can be derved followng the Krchhoff s oltage Law (KL): v pcc L k + - v + - v p v n R L L R p n dc vp vn (4) I dc F H dc / vn vp v (5) dc / Fg.. Crcut dagram of one-phase of - B. Low DC voltage requrement In practcal terms, the most sgnfcant beneft of s the possblty to operate normally under DC fault condtons, whch means that the converter DC voltage dc can take any value n the range dc mn dc d C c C c + - v c v c (6) The mnmal DC voltage dcmn, s a desgn requrement and can be specfed n the range: (7) d dc mn d The converter DC voltage s: M (8) dc dc arm _ dc Where M dc s the DC modulaton ndex, representng an addtonal control sgnal feasble only wth. The DC modulaton ndex control range depends on the physcal capablty of the,.e. the number of submodules. The mnmal possble DC voltage s also noted usng pu values dcmn= mnpu d. Therefore the M dc control range s: mnpu M (9) ote that M dc can be negatve. Lowerng dcmn requres more submodules and therefore has cost penaltes. C. Requred arm voltage ratngs In order to generate requred v, under gven dc, usng (4), and (5) the converter arm voltage should have the values: dc arm _ dc vp M dc v () arm _ dc vn M dc v () It s mportant to frstly determne requred maxmal and mnmal voltage of arms snce these ratngs wll determne the number of submodules n arms. The maxmum peak voltage ˆp and mnmum peak voltage ˆp of the upper arm under d can be obtaned from (), replacng dc= d assumng that M=, and consderng peak values for the requred grd sne voltage v of (): ˆ p ( dc d ) d () ˆ p ( dc d ) d () Under mnmal DC voltage dcmn, the converter s also requred to generate nomnal v, n order to exchange rated reactve power. Therefore replacng (8) n () and usng the lower lmt from (6) the maxmal and mnmal values for upper arm voltage under the lowest DC voltage are: ˆ mnpu p dc dc mn d (4) ˆ mnpu p dc dc mn d (5) Equaton () gves the absolute maxmal requred voltage for upper arm whle equaton (5) gves the requrement for mnmal arm voltage. For gven k and dcmn, these two equatons determne voltage ratng of the arm. It s evdent (c) 5 IEEE. Personal use s permtted, but republcaton/redstrbuton requres IEEE permsson. See

3 .9/TPWRD.5.475, IEEE Transactons on Power Delvery from (5) that mnmal arm voltage ˆp dc dc mn wll assume negatve value for dcmn<k d, and ths leads to the requred number of submodules. III. REQUIRED UMBER OF SUBMODULES A. Total number of arm submodules It s assumed that postve voltage s generated by both and submodules. sm p c sm ˆ v (6) Where s the nomnal submodule voltage whch s determned by the ratng of the employed IGBTs (typcally.k< <k) [4]. sm s the total number of submodules per arm. From () and (6), sm s calculated by, ˆ d sm p / / (7) Equaton () also enables accurate expresson for the arm DC voltage: v (8) sm ˆ arm _ dc p c B. Requred number of submodules The full brdge submodules are requred n order to generate negatve arm voltage. The negatve value of expresson n (5) gves the number of submodules: ˆ p dc mn mnpu d (9) If any submodules are present, they are also assumed to be able to generate postve voltage, contrbutng to the total arm voltage n (7). Therefore subtractng (9) from (7) the number of submodules: mnpu d () In the common case of dcmn=, the number of submodules s obtaned as: d ( dc mn ) () d ( dc mn ) () The specal case k = and dcmn= d wll gve the converter desgn specfcaton. Examnng (9) and () t s concluded that: The requred number of submodules ncreases as the mnmal DC voltage reduces and as the over-modulaton ndex ncreases. These two requrements are ndependent (each requres extra submodules). The number of submodules depends only on the mnmal DC voltage. Examnng (7), (9) and () t s concluded that the total number of submodules depends only on the over-modulaton ndex (not on the mnmal DC voltage). Ths mples that: Under a gven mnpu and d, ncreasng over-modulaton ndex requres addtonal submodules accordng to (9). Addng new submodules s costly. Under a gven k and d, lowerng mnmal DC voltage requres replacng submodules wth submodules Ths has modest cost mplcatons snce submodules are -5% more expensve than submodules. I. POWER CAPABILITY ICREASE WITH OER-MODULATIO Ths secton studes the benefts of over-modulaton (ncreasng k ). Hgher k requres hgher number of semconductors and therefore hgher costs. The goal s to analyze the cost mplcatons of the ncrease n the maxmal converter power resultng from over-modulaton. The converter AC current n Fg. s defned as: I cos( t ) () m Replacng the AC voltage from (), under extreme condtons M=, M dc= and θ - θ v = the maxmal AC power for -phase s defned as: P ac max m Whle the maxmal DC power s: d I k (4) P I (5) dc max d d where I d s the nomnal DC current and d s the rated DC voltage. Equatng (4) wth (5), the lnk between maxmal AC and DC current s derved as: I k 4 m d I (6) From (6) and () t s concluded that works as an deal transformer, where k determnes the steppng rato. The arm current (takng upper arm as an example) can be derved as: P ( Idc ) (7) Denote the peak of arm (submodule) current n (7) as I pm and substtute () and (6) nto (7), a relatonshp between peak AC current I m and peak submodule current I pm s obtaned: I m 4I pm (8) k Substtute (8) nto (4), the maxmal AC power as the functon of over-modulaton ndex s: (c) 5 IEEE. Personal use s permtted, but republcaton/redstrbuton requres IEEE permsson. See

4 .9/TPWRD.5.475, IEEE Transactons on Power Delvery 4 P ac max k I k d pm (9) In the above expresson the study s concerned wth the possble power ncrease as the ndex k s ncreasng. The DC voltage s kept unchanged and also the peak submodule current I pm (therefore the same IGBTs). Therefore the per unt AC power (dvng (9) by power when k =) s: P ac max_ pu () k Equaton () s llustrated n Fg.. For a gven fxed DC voltage d, and gven submodule current ratng (I pm), enables hgher power transfer usng over-modulaton. It s seen that the power ncrease wth k has modest slope, and may only be justfed where DC voltage cannot be further ncreased (DC cable nsulaton). ote that the converter power s normally ncreased drectly by ncreasng DC voltage, and the power s proportonal to the ncrease of dc, for a constant submodule current. Ths conventonal method gves hgher slope than n Fg., and t s evdently more cost effectve to ncrease power by ncreasng DC voltage, f DC voltage can be ncreased. However, snce DC cable voltage levels are typcally gven n dscrete steps and also IGBT current ratngs have fxed values, k may provde opportunty for fne tunng the desgn for maxmal component utlzaton. Each submodule employs 4 IGBTs. Each submodule employs IGBTs, bypass swtch and bypass thyrstors whch have lower costs and wll be neglected n ths study. Accordng to (9) and (), the relatonshp between the total number of IGBTs per arm and the k s: d IGBT 4 ( mnpu ) () Dvdng () by (9), the number of IGBTs per arm per actve power s obtaned: ( mnpu )( ) IGBT () P k I ac max pm In case of dcmn=, () becomes: k k () P k I IGBT 5 ( dcmn ) ac max pm Equatng frst dervatve of () wth zero, the k for mnmum IGBT number per power s. Denotng mnpu=, k = as the base case and dvdng () by the base number, the per unt number of IGBT per arm for each unt of actve power s obtaned as llustrated n Fg.. It s seen that the number of swtches ncreases wth the ncrease of k or decrease of dcmn. However each curve for mnpu< s a parabola whch has an optmal mnmal value. Pac(pu) Fg.. - power ncrease wth k (for constant dc and submodule peak current I pm). IGBT/Pac[pu] mnpu= - mnpu= -.8 mnpu= -.6 mnpu= -.4 mnpu= -. mnpu=. mnpu= +. mnpu= +.4 mnpu= +.6 mnpu= +.8 mnpu= Fg. umber of IGBTs per unt power for dfferent k and for dfferent dcmn requrements.. CAPACITOR OLTAGE BALACIG I A. Mnmal umber of submodules for successful voltage balancng Expandng (7), the upper arm current can be expressed as: Im P cos( t ) Idc (4) The above arm current has AC term and a DC term, and dependng on ther relatve magntude the arm current may have only one polarty. oltage balancng of submodules can be acheved ether wth negatve or postve current, consderng that submodule voltage can be reversed. However balancng of submodules s more restrctve. Successful submodule balancng demands that the arm current has postve and negatve segments n each cycle. Ths mples that the peak of AC component n (4) must be larger than DC component: I m Idc (5) In steady state, the nstantaneous dc power equals the AC power, and therefore usng (8), () and (5): (c) 5 IEEE. Personal use s permtted, but republcaton/redstrbuton requres IEEE permsson. See

5 .9/TPWRD.5.475, IEEE Transactons on Power Delvery 5 Marm _ dc M dcarm _ dcidc Im cos( v ) (6) Consderng the case that θ v -θ = (.e. the - transfer actve power from the ac sde to the dc sde), and worst case AC modulaton ndex M=, then (6) gves: M dcidc Im (7) 4 Replacng (7) n (5), the condton for successful balancng of submodules (arm current has postve and negatve values) s obtaned: M dc (8) Therefore, for a - wth desgn requrement mnpu.5k, the and can be dmensoned accordng to (9) and (). For the other desgn requrement -.5k < mnpu<.5k, to enable successful voltage balancng of the submodule voltages all the nserted submodules should be of type. Therefore and should be dmensoned as:.5 d d (9) 4 d ( ) (4) 4 In case of even lower requrement mnpu<(-.5k ), snce the absolute value mnpu >.5k under such condton, and can stll be dmensoned accordng to (9) and (). Combnng (9), (), (9) and (4), generc method of calcuatng the number of submodules and submodules n a - under any specfed desgn condton s: k k, mnpu k k, mnpu 4 mnpu d d k, mnpu k k ( ), mnpu 4 mnpu d d (4) (4) Fg. 4 shows the number of requred submodules (n pu relatve to the total number of submodules n an arm sm) as the functon of mnpu (n pu relatve to d) and k. These curves show the values of requred to acheve the border condton of zero AC current accordng to (5), whle n practce some negatve current s requred and therefore the number of submodules should be perhaps -% larger. In HDC applcatons wth overhead lnes, the requred mnmal DC voltage wll commonly be dcmn, and assumng also that commonly k, t s concluded that at least 8% of the arm submodules should be of type. ote that such converter wll also be able to operate wth DC voltage as low as dc=-.5pu accordng to Fg. 4. Alternatvely, as a lower cost soluton, can be desgned wth 5% cells whch enables DC voltage reducton to around.5pu (k ). Such HDC can be operated at reduced DC voltage as a preventatve measure to avod flashovers under unfordable atmospherc condtons. [pu] k =. k =.8 k =.6 k =.4 k =. k = mnpu Fg. 4 Mnmal number of submodules n an arm for gven k and dcmn. B. Instantaneous number of submodules n converter arm and phase leg The number of nserted submodules n postve arm s determned usng nearest level control accordng to n P=v P/. Consderng () and () for gven control sgnals M and M dc, the number of nserted submodules n postve and negatve arms s: d np M dc M cost v (4) d nn M dc M cost v (44) whle the number of submodules n a leg (pole-pole) s: n M k M cos t dc dc v M k M cos t dc v d (45) Therefore unlke wth, the number of nserted submodules n a leg of s not constant. Ths mples that total capactance between poles s also not constant and control dynamcs wll be dfferent compared wth. C. Capactor voltage balancng algorthm Fg. 5 takes the upper arm as an example to llustrate the basc voltage balancng algorthm of -, whch uses smlar prncples as wth tradtonal - [] (c) 5 IEEE. Personal use s permtted, but republcaton/redstrbuton requres IEEE permsson. See

6 .9/TPWRD.5.475, IEEE Transactons on Power Delvery 6 In Fg. 5, p_pre s the number of nserted submodules n the prevous control cycle. The CBA of Fg. 5 wll only be executed once p p_pre. In the case of p, the basc CBA wll not dscrmnate between the submodules and the submodules and the CBA s exactly the same as the CBA of a -. In the case of p<, only the submodules wll be nserted (wth negatve voltage) whle all the submodules wll be bypassed. D. Relatonshp of Insertng Logc wth dynamcs of an arm Consder an arm whch at a partcular nstant operates wth p submodules nserted wth negatve voltage. If a request comes to ncrease arm voltage there are two optons: ) Bypass one negatvely nserted submodule. In ths case the arm voltage wll be around ( p +), ( p<) and the arm current s passng through ( p -) submodules. Ths makes the arm capactance C c/( p -). Ths method wll be adopted snce t gves submodule capactance change consstent wth controls. ) Insert one submodule. In ths case the arm voltage wll stll be around ( p +), but the arm current s passng through ( p +) submodules. Ths makes the arm capactance C c/( p +). I. SIMULATIO ERIFICATIOS A. test system and detaled model Fg. 6 shows the crcut dagram of the test system. It s a sngle connected to a ±k DC battery through a 7km DC cable []. Smulatons on detaled swtchng model of a - [] are conducted on EMTP-R software [] to verfy the theoretcal dervatons. Power transmtted from AC to the DC sde s denoted as postve. Table lsts parameters of the test - converter where SCL and X/R are respectvely the short crcut level and the X/R rato of the AC system. X k s the leakage reactance of the AC transformer; T c s the equvalent energy dscharge tme of the submodule capactor. The detaled swtchng model s desgned to have =8 and =4 accordng to (4) and (4) (8% cells). Consderng curves n Fg. 4, ths converter should be able to operate wth mnmal DC voltage of -.6pu. k Table parameters of the test system d(k) dcmn(k) (k) P acmax(mw) SCL(MA) X/R C c(μf) T c(ms) L arm(h) X k(pu) B. controller The ntenton s to operate n open loop n order to valdate converter desgn equatons. However, has ndependent controls on AC sde (M d and M q) and on DC sde (M dc) whch may create energy unbalance on the arm capactors. Therefore t s necessary to use addtonal control loop to balance total arm voltage. Fg. 7 shows the very basc control of the - employed n ths study. The nner -axs, decoupled AC current controls are dentcal as wth common. The d-channel current I d s used to control average arm voltage of the 6 arms of the. The DC current s drectly controlled through a PI controller actng on M dc. START Intalze p_pre = dc / Determne the number( p ) of nserted cells For Both cells and cells O p p_pre YES Record and sort the capactor voltages Only for cells Postvely nsert p cells from all the sm cells wth the lowest capactor voltages, bypass the other sm - p cells YES O p? p p < YES O p? Postvely nsert p cells from all the sm cells wth the hghest capactor voltages, bypass the other sm - p cells egatvely nsert p cells from the SM wth the hghest capactor voltages, bypass the other sm - p cells egatvely nsert p cells from the SM wth the lowest capactor voltages, bypass the other sm - p cells p_pre= p Fg. 5 submodule voltage balancng algorthm (c) 5 IEEE. Personal use s permtted, but republcaton/redstrbuton requres IEEE permsson. See

7 .9/TPWRD.5.475, IEEE Transactons on Power Delvery 7 ~ 4k:4k Z s.h.h Fg. 6 Crcut dagram of the test system dc MW ±k dc(pu) Idcref, Idc(pu) dc Mdc (a) DC oltage.5 Idcref. Idc (b) DC Current.5 Fg. 7 Elementary control of - used for testng. C. Operatng wth over-modulaton and low DC voltage Fg. 8 shows the EMTP verfcaton of over-modulaton and low DC voltage operaton of the. The ntally operates at pu DC voltage and at.s voltage of the DC battery s stepped to -.6pu and fnally stepped to pu at.7s. The DC current reference s kept at pu durng the test. The reactve current reference s stepped from to.pu at.4s. Fg. 8(a) shows profle of dc. Control sgnal Mdc margnally dffers from dc because of lne resstance. Fg. 8(b) shows the DC current whch s regulated at pu. Fg. 8(c) shows that the actve current whch changes magntude and sgn n order to mantan power balance between AC and DC sdes. Fg. 8(c) also demonstrates that retans ndependent reactve current control capablty rrespectve of DC voltage magntude. Fg. 8(d) shows the pole to ground DC voltage and AC termnal voltage of. We can see that the - operates wth over-modulaton (peak phase-ground AC voltage s hgher than the pole-to-ground DC voltage). Also, durng low DC voltage ntervals acheves requred AC voltage magntudes. Fg. 8(e) shows the submodule voltages of the upper arm of phase A. We can see that voltages of the submodules are well balanced. Fg. 8(f) shows that the upper arm voltage and lower arm voltage of phase A generate negatve values. Ths s only possble wth submodules. Id,Iq(pu) v,dc/(k) Idref, Id Iqref, Iq (c) d and q-channel currents 4 - dc/ v (d) AC and DC voltage 6 c_ vc(k) oltages(k) 4 c_ (e) submodule voltages dc vpa vna (f) Arm voltages Fg. 8. erfcaton of over-modulaton and low DC voltage operaton (c) 5 IEEE. Personal use s permtted, but republcaton/redstrbuton requres IEEE permsson. See

8 .9/TPWRD.5.475, IEEE Transactons on Power Delvery 8 D. Response wth nsuffcent submodules Fg. 9 shows response of the - wth nsuffcent submodules. As n prevous test k =. but the number of submodules s =4, =8, ( s 6% of submodules) whch s calculated accordng to (9). Ths desgn volates the condton n (9), and therefore we expect voltage balancng ssues of cells. Accordng to Fg. 4 ths converter can operate wth DC voltage no lower than.6pu. The DC voltage s -.pu and t s ramped to.5pu at.5s as seen n Fg. 9a). Fg. 9(b) shows the upper arm current of phase A. We can see that the current of PA s always of postve whle dc=-.pu and always negatve value when dc=.5pu. dc(pu) pa(ka) pa vc(k) dc Mdc (a) DC oltage (b) upper arm current of phase A (c) number of nserted submodules of upper arm of phase A 8 c_ 6 4 c_ (d) submodule voltages of upper arm of phase A Fg. 9 Smulaton of operaton wth nsuffcent number of submodules. Fg. 9(c) shows the number of nserted submodules of the upper arm of phase A. It s seen that - pa 9 when the DC voltage s -.pu. As pa <, all the requred submodule voltages can be provded by the submodules ( submodules are bypassed). Even wth pa consstently greater than zero, the - s stll able to balance all submodule voltages. However, when dc=.5pu the maxmum value of pa reaches over 5. As the total number of submodules s only 4, some addtonal submodule need to be nserted, but submodule voltage balancng wll not be possble. Fg. 9(d) shows the submodule voltages of upper arm of phase A. The submodule voltages are well balanced before.5s. After.5s the submodules are constantly dschargng because of undrectonal current, as predcted. The submodule voltages can be balanced, but they tend to ncrease to compensate for lower voltages, snce the top-level control keeps total arm voltage at pu. The balancng method s also tested wth much hgher number of cells and smlar results are observed. II. COCLUSIO Ths paper presents the full brdge optmal desgn to HDC specfcatons. It s found that for gven rated DC voltage and rated submodule voltage, the total number of submodules s solely determned by the over-modulaton ndex k. The number of submodules ncreases as the mnmal DC voltage reduces and as the k ncreases. The number of submodules depends only on the mnmal DC voltage. Wth the ncrease of k, the rated power transfer capablty of a - can be ncreased, though at a cost penalty of more power electronc devces. The requred number of power electronc devces per unt transferred actve power does not sgnfcantly changes wth the change of k. To enable successful voltage balancng under low DC voltages, typcally at least 8% of submodules should be of type. Smulatons on EMTP-R verfed the desgn method proposed n ths paper. REFERECES [] D Jovcc and K Ahmed "Hgh-oltage Drect Current Transmsson: Converters Systems and DC Grds", Wley 5. [] A. Lesncar, R. Marquardt, An nnovatve modular multlevel converter topology sutable for a wde power range, n Proc. Power Tech Conf., Bologna, Italy,, pp. -6. [] P. Francos, S. erdugo, H. Alvarez, S. Guyomarch, J. Loncle, IELFE-Europe's frst ntegrated onshore HDC nterconnecton, IEEE PES Socety General Meetng, San Dego, July. [4] C. Oates, Modular multlevel converter desgn for SC HDC applcatons, IEEE Journal of Emergng and Selected Topcs n Power Electroncs, 5, DOI:.9/JESTPE [5] B. Jacobson, P. Karlsson, g. Asplund, L. Harnefors, T. Jonsson, SC-HDC transmsson wth cascaded two-level converters, CIGRE [6] D. Doerng, J. Dorn, G. Ebner, M. Schmdt, C. Segl, oltage sourced converters for HDC overhead lne applcaton, 4 CIGRE Canada Conference, CIGRE-6. [7] E. Kontos, R. T. Pnto, S. Rodrgues and P. Bauer, Impact of HDC transmsson system topology on mult-termnal DC network faults, IEEE Trans. Power Del., vol., no., pp , Apr. 5. [8] X. L, Q. Song, W. Lu, H. Rao, S. Xu, L. L, Protecton of nonpermanent faults on DC overhead lnes n -based HDC systems, IEEE Trans. Power Del., vol. 8, no., pp. 48-9, Jan (c) 5 IEEE. Personal use s permtted, but republcaton/redstrbuton requres IEEE permsson. See

9 .9/TPWRD.5.475, IEEE Transactons on Power Delvery 9 [9] R. Marquardt, Modular multlevel converter: an unversal concept for HDC-networks and extended DC-bus-applcatons, IPEC, pp [] M. Merln, T. Green, P. Mtcheson, D. Traner, D. Crtchley, R. Crookes, A new hybrd mult-level voltage-source converter wth dc fault blockng capablty, IET ACDC conference, pp. -5. [] M. Merln, T. Green, P. Mtcheson, D. Traner, R. Crtchley, et al, The alternate arm converter: a new hybrd multlevel converter wth dc-fault blockng capablty, IEEE Trans. Power Del., vol. 9, no., pp. -7, Feb. 4. [] J. Zhang, C. Zhao, The research of SM topology wth DC fault tolerance n -HDC, IEEE Trans. Power Del. 5, DOI:.9/TPWRD [] A. am, L. Wang, F. Djkhuzen, Fve level cross connected submodule for cascaded converters, EPE,, pp. -9. [4] R. L, G. P. Adam, D. Hollday, J. E. Fletcher and B. W. Wllams, Hybrd cascaded modular multlevel converter wth DC fault rde-through capablty for HDC transmsson system, IEEE Trans. Power Del., 5, DOI:.9/TPWRD [5] S. Debnath, M. Saeedfard, A new hybrd modular multlevel converter for grd connecton of large wnd turbnes, IEEE Trans. Sustan. Energy, vol. 4, no.4, pp. 5-64, Oct.. [6] J. Qn, M. Saeedfard, A. Rockhll, R. Zhou, Hybrd desgn of modular multlevel converters for HDC systems based on varous submodule crcuts, IEEE Trans. Power Del., vol., no., pp , Feb. 5. [7] G. Adam, B. Wllams, Half- and full-brdge modular multlevel converter models for smulatons of full-scale HDC lnks and multtermnal DC grds, IEEE Journal of Emergng and Selected Topcs n Power Electroncs, vol., no. 4, pp. 89-8, Dec. 4. [8] G. Adam, I. Davdson, Robust and generc control of full-brdge modular multlevel converter hgh-voltage DC transmsson systems, IEEE Trans. Power Del., 5, DOI:.9/TPWRD [9] G. Adam, K. Ahmed, B. Wllams, Mxed cells modular multlevel converter, 4 IEEE ISIE, pp [] R. Zeng, L. Xu, L. Yao, B. W. Wllams, Desgn and operaton of a hybrd modular multlevel converter, IEEE Trans. Power Electron., vol., no., pp. 7-46, Mar. 5. [] R. Zeng, L. Xu, L. Yao, D. Morrow, Prechargng and DC fault rde-through of hybrd -based HDC systems, IEEE Trans. Power Del., vol., no., pp. 98-6, Jun. 5. [] J. Peralta, H. Saad, S. Dennetere, J. Mahseredjan, S. guefeu, Detaled and average models for a 4-level -HDC system, IEEE Trans. Power Del., vol. 7, no., pp. 5-58, Jul.. [] J. Mahseredjan, S. Dennetère, L. Dubé, L., B.Khodabakhchan, L. Gérn-Lajoee, On a ew Approach for the Smulaton of Transents n Power Systems, Electrc Power Systems Research, vol. 77, no., pp. 54-5, Sep. 7. Samuel guefeu (M 4) graduated from École Supéreure d'electrcté (Supélec), Gf-sur-Yvette, France, n 99. He receved the M.A.Sc. and Ph.D. degrees n electrcal engneerng from Unversté Perre et Mare (Pars I), Pars, France, n 99 and 99, respectvely. He was a Consultant for two years before jonng THOMSO, France, n 996. From 999 to 5, he was wth EDF R&D, Clamart, France, n Power Systems and Power Electroncs. In 5, he joned the French Transmsson System Operator (Réseau de Transport d Electrcté), where he s currently nvolved n Flexble AC Transmsson Systems and HDC projects. system smulaton. Han Saad (S 7) receved hs B.Sc. and Ph.D. degrees n electrcal engneerng from the École Polytechnque de Montréal n 7 and 5, respectvely. From 8 to he worked at Techmp Spa.and n the Laboratory of Materals Engneerng and Hgh oltages (LIMAT) of the Unversty of Bologna on research and development actvtes related to partal-dscharge dagnostcs n power systems. In 4, he joned the French TSO (Réseau de Transport d Electrcté), where he s currently nvolved n power BIOGRAPHIES Wexng Ln (M, S ) obtaned hs Bachelor s degree and PhD degree n electrcal engneerng n 8 and 4 from Huazhong Unversty of Scence and Technology (HUST), Wuhan, Chna. He s currently a research fellow at the Unversty of Aberdeen. Hs research nterest s dfferent topologes of, smulatons on EMPT-R, dc grds, hgh power dc-dc converter, hgh power dc-dc autotransformer. Dragan Jovcc (SM 6, M, S 97) obtaned a Dploma Engneer degree n Control Engneerng from the Unversty of Belgrade, Yugoslava n 99 and a Ph.D. degree n Electrcal Engneerng from the Unversty of Auckland, ew Zealand n 999. He s currently a professor wth the Unversty of Aberdeen, Scotland where he has been snce 4. He also worked as a lecturer wth Unversty of Ulster, n the perod -4 and as a desgn Engneer n the ew Zealand power ndustry n the perod Hs research nterests le n the FACTS, HDC, DC grds and ntegraton of renewable sources (c) 5 IEEE. Personal use s permtted, but republcaton/redstrbuton requres IEEE permsson. See