SUPPRESSION OF ELECTROMAGNETIC INTERFERENCE BY SPREAD SPECTRUM CLOCK GENERATION

Transcription

1 SUPPRESSION OF ELECTROMAGNETIC INTERFERENCE BY SPREAD SPECTRUM CLOCK GENERATION Dr.Srigitha.S.Nath 1, Ms.S.Umamahesawri 2, Ms.S.Chithra 3, Ms.K.Anitha 4 1 Professor &Head, Department of ECE, Saveetha Engineering College, Chennai, India, hod.ece@saveetha.ac.in 2. Assistant Professor, Department of ECE, Saveetha Engineering College, Chennai, India, umamaheswari@saveetha ac.in 3 Assistant Professor, Department of ECE, Saveetha Engineering College, Chennai, India, chithra@saveetha ac.in 4 Assistant Professor, Department of ECE, Saveetha Engineering College, Chennai, India, anitha@saveetha ac.in Abstract A clock is a specific type of signal that can oscillate between a high and a low state. When the operating frequency and data rate is increased, the clock oscillation increases. When the clock signal operates at high speed, it makes the digital circuits to emit radiation that may interfere with nearby circuits that leads to electromagnetic interference. The electromagnetic interference appear as sharp spectral peaks with high intensities. The amount of radiation from synchronous digital circuits can be reduced by using spread spectrum clock generator. This paper presents digital spread spectrum clock generator methods, where the system clock is modulated using saw tooth modulation technique. The saw tooth modulation is more effective since most of the problems faced while designing digital circuit is related to the clock signals, which is a major contributor of electromagnetic interference. A comparison is made between triangular modulation and saw tooth modulation in terms of power consumption and efficiency. Keywords spread spectrum; electromagnetic interference; sawtooth modulation. I. INTRODUCTION Today all applications are digitally controlled. Implementation of digital systems is ruled by logic of the devices. Digital devices have become dense with respect to signal speed specifically with clock synchronization, setup and hold time and jitter. These inconveniences not only affect the system but also leads to electromagnetic interferences (EMI) when the device is operating at high frequency in close contact. Electromagnetic interference frequently known as radio-frequency interference is mainly the disturbance caused by radio frequency that affects an electrical circuit due to radiated electromagnetic waves emitted from any kind of external source. Such unwanted radiations disrupt and corrupt the actual performance of digital devices. The main issue that has to be addressed in the design of digital devices is to maintain the electromagnetic radiations within the permissible levels. Most of the problems faced while designing a digital system relates to the clock of the system. The clock signal is the highest frequency signal that acts as the primary source of EMI. Moreover, as requirements for speed increases, the radiations emitted from the digital devices will contain higher electromagnetic energy. The radiation levels of the devices are maintained by numerous regulatory agencies across the world that verify the various EMI standards. The agencies certify that any digital devices do not interfere with the functioning of other devices by emitting harmful radiations. These agencies set the limit on the maximum allowed radiation emission according to the countries requirements. Compliance test on the devices are performed to ensure that frequency violation does not occur. II. SPREAD SPECTRUM CLOCK GENERATION In this kind of clock generation, a particular bandwidth signal is varied and spread in frequency domain. The signal will be spread out over a wider bandwidth that causes a reduction in the peak radiated emission. In spread spectrum clock generation, the transform at logical levels occurs concurrently for synchronized digital devices. Such transitions at the logical level of transform of a particular signal is called as the clock. Prediction of circuit behaviour can be made exactly since the input of each of the storage elements will reach its terminal value before the occurrence of the next clock pulse. A digital system is opted for high speed and accuracy and for a synchronized digital system to operate at a very high speed there is a need for delay at each level of logical operation. Care is taken while designing the clock distribution networks in order for these circuits work correctly. Static timing analysis is often used to find the maximum safe operating speed. Fig. 1. Spread Spectrum Clock 815

2 III. PROPOSED SYSTEM The All-Digital Spread Spectrum Clock Generation (ADSSCG) is depicted in Fig.2. The ADSSCG comprises of a spreadspectrum clock (SSC) controller, phase and frequency detector (PFD), a spreading ratio detector, a digital loop filter, a Sawtooth Modulator, a Digital control oscillator, and a divide by 16 block. The modulation used in ADSSCG is sawtooth modulation. Fig.2. Concept of all digital spread spectrum clock generation A. Spread Spectrum Controller It is possible to spread the spectrum of a digital clock signal by various methods such as Clock Scrambling and Clock Modulation. In clock scrambling also known as suppressed carrier clocking, the clock signal is directly mixed with the modulation signal using XOR gate. One of the common methods to perform clock signal conditioning involves the modulation of the clock frequency with the waveform in order to spread its energy over a wider band of frequency. Such a method of suppressed carrier clocking does not introduce jitter and the attenuation of the fundamental frequency is slightly greater than 10dB. If the modulation is performed on the transition period of the clock, the transition of these suppressed clock will be lost. This leads to increase in computation time in synchronous digital devices. This problem can be reduced in clock distribution network, where demodulation of scrambled signal is performed but this results to additional design of the demodulation circuitry. In the clock distribution network, the signal has suppressed EMI whereas at the clock frequencies and its harmonics the signal in the rest of the chip emits radiation. It is possible to obtain a spread spectrum clock signal in clock modulation method in two different ways. The first method is modulating the clock s frequency completely. Conventionally, the input voltage of digitally controlled oscillator is guarded by a modulation waveform. The suppressed carrier clock in time domain is represented in fig. 3. Fig.3. Waveform of suppressed carrier clock in time domain This spread spectrum clock generation that supresses the EMI can be achieved using various modulation techniques namely, Delta sigma Modulation which is efficient but cost of implementation remains high, Triangular modulation, where the problem of jitter exists and Saw tooth modulation, which has lower cost of implementation and overcomes the problem of jitter. B. Spreading Ratio Detector 816

3 The reduction in EMI depends on spread amount of the clock, more the spread more interference is reduced. The amount of clock spreading is commonly done in terms of percentage. The spread amount is defined as the ratio of difference between the two boundary frequencies (Δf) to the clock target frequency. Fig.4. shows the EMI reduction with increasing spread amount. Fig.4. EMI reductions with increasing spread amount In synchronous digital devices, the harmonics of the fundamental frequency is a main concern as it is a main source of radiation. The reduction in electromagnetic interference is achieved by attenuating the radiations from the harmonic frequency. Due to fixed amount of spread, these harmonic frequencies will have their attenuation of peak energy more prominent at higher order and less attenuation at the fundamental frequency. This mainly occurs at higher frequencies where the narrow band becomes wider and also since the harmonics are an integer multiplication of the centre frequency. When implemented in such a way, there will be more reduction in the amount of radiated energy as depicted by Fig. 5. Fig.5. EMI reduction vs. Harmonics The amount of reduction in the shape of the spectral peak is decided by the spreading profile, which is the main factor in the frequency variations of modulated signal with respect to time, when spread spectrum technique is applied. C. Estimation of EMI Reduction Level using Spread Spectrum Clocking The parameters of a spread-spectrum clock are responsible for how much the interference is suppressed. To determine the amount of suppression, calculation of spread spectrum clock is necessary. The signal spectrum can be defined as the power density in terms of frequency. The clock and spreading clock are represented as, A sin 2πfct = A sin 2π(fc+w(t)) t (1) where w(t) is the waveform for modulation. The spectrum of the non-spreading clock is a line of spectra at frequency fc and has a magnitude value of 1/2A 2. In a spectrum the amplitude does not depend on the resolution bandwidth B since the spectrum is represented as a spectral line but on the resolution bandwidth B. Within the range of the frequency band the spreading clock spread in terms of Δf, which is the power measured in the spectrum analyzer at the resolution band B. The resolution band B is given by B = 12 A 2 B/Δf (2) Hence the EMI reduction rate S is represented as: S=10 log ( Δf /B ) (3) 817

4 The suppression reduction rate S is represented in terms of spreading rate δ, clock(clk) frequency fc, and modulation styles in the following ways: 1. Down or up spreading: 2. Centre spreading: S=10 log (( δ *fc)/b) (4) S=10 log ((2 δ *fc)/b) (5) This simple estimate provides the designer, the spreading rate of the EMI reduction. D. Phase and Frequency Detector Phase-locked loop (PLL) circuits are used when an output signal whose phase will relate to that of the input signal has to be generated. PLL is often used for the process of frequency multiplication, clock synchronization and recovery. Phase locked loop circuits can be classified into various types based on the application where it is used. The block diagram of PFD is shown in Fig.6. Fig.6. Basic representation of Phase and Frequency Detector The main components of a digital PLL circuit encompass of PFD. The difference of phase and frequency between the input reference signal and the signal given as feedback is measured by the Phase and frequency Detector. The Operation of PFD is shown in Fig.7. The operation of PFD is obtained by combining a latch circuit and a 4-state PFD. Fig.7.Operation of PFD There are four nodes, namely node U, node D, node UP and node DN. During the positive progression of REFCLK, the node U is high while the voltage level of node D remains low. Due to this transition, an UP signal is generated. The UP-control signal is maintained high until the transition of FBKCLK occurs. Similarly, when a positive transit occurs on FBKCLK the node D becomes high while the node UP is low. A down signal is set and is turned off only when transition of REFCLK occurs. While both REFCLK and FBKCLK transition happen simultaneously the nodes U and D is at a lower voltage level. In 818

5 such a state no output signal is generated from the PFD. Fig.8.shows the output of phase and frequency detector. The PFD used has a simple circuitry and has no glitch output. Fig.8.Outputs of Phase and Frequency Detector. E. Digitally Controlled Oscillator In a digitally controlled oscillator a periodic signal is generated whose frequency is digitally controlled by a control word. The digitally controlled oscillators are based on ring based topology having 3, 4 and 5 control bits. Based on the requirement of output frequency range an increase in the number of control bits is done. The advantages of the ADPLL systems are fast frequency locking, digital control and good stability. LC oscillators are the commonly used oscillators in transceiver designs. The most important feature of the LC oscillator is the low phase noise. In all digital PLLs, the discretization of frequency leads to quantization noise that affects the performance of the system in terms of out-of-band phase noise. The heart of the DCO is the capacitor bank. The capacitor bank consists of groups of varactors that have different specifications. Variation of frequency in DCO in coarse and fine frequency steps is provided by the capacitor bank. Therefore, the varactor decides the tuning range and frequency resolution of a DCO. Varactors are just variable capacitances that are controlled by control bits in case of DCOs and tuning voltage in case of VCOs. DCO s should be designed in such a way that it can provide enough control word to control the frequency and maintain only a considerable amount of jitter because jitter is a factor that is responsible in stimulating the system. The resolution is the factor that decides the jitter, if the resolution is kept small, the jitter of the PLL can be maintained. The optimized DCO has a lower power consumption, hence PLL will become more energy-efficient. F. Delta Modulation A much-simplified version of PCM is the Delta Modulation(DM). In some systems correlation occurs between neighbouring samples. Once the samples are known, instead of sending the real value of each sample every time, the estimate of the variances between successive samples are sent in Delta Modulation. In DM a two-level quantization scheme is used along with one-bit coding. The transmitted code pulses do not carry the message data but they carry only a differential message function. At the output of the demodulator the bit stream of samples appears at high rate. The value of each bit is determined based on whether the input message sample has increased or decreased in contrast to the pervious samples. The system implements a feedback loop where it acts as a continuous to discrete-time converter. It is nothing but a form of analog to digital converter. Once the clocking of the sampler occurs, the resultant signal is a delta modulated signal.fig 9,shows the generation of saw-tooth waveform. Fig.9. Generation of Saw-tooth waveform 819

6 The output of the sampler is a bi-polar signal (+V volts) which has a clocking rate similar to that of the modulator. On integrating the clock signal, a saw tooth-like waveform is generated. This is somewhat approximate to the original message. At message frequency, the saw tooth waveform contains information and certain unwanted frequency components (quantization noise). Such unwanted frequency components that lie beyond the bandwidth of the original baseband message are removed by designing a lowpass filter. Reconstruction of the original message using a delta modulator is less perfect when compared to ideal sampling of an analog signal, and then performing ideal reconstruction by a lowpass filter. IV.RESULTS AND DISCUSSION The results show the waveforms of the input signal with sharp spectral peaks where the intensity of interfering signal is high. The high intensity signal is reduced by spreading the signal from a narrow band to a wide band that thereby reduces the electromagnetic interference caused. Fig. 11, shows the signal with sharp spectral peak where the intensity of interfering signal will be high. Fig.10.Signal with a high intensity peak Fig.12, shows the spreading of the signal from narrow band to a wideband that causes a reduction in signal intensity. Figure 12. High Intensity spread spectrum signal 820

7 The spectrum analysers step response is shown in Fig. 13 Fig.13.Step Response V. CONCLUSION This paper summarizes the spread spectrum clock generation techniques. A brief discussion on sources and causes of Electromagnetic interference along with various control methods have been discussed. The block diagram of all digital spread spectrum clock generation using sawtooth modulation is analysed. The simulation results of spread spectrum clock generation are analysed with sawtooth modulation technique. The experimental results demonstrate the spreading of narrow band spectral peak to a wide band spectrum. The power consumption when sawtooth modulation is used was found to be around 111 mw which is a significantly lower value when compared to other modulation techniques. REFERENCES [1] Bo Shen, Unruh, G., Lugthart, M., Chang-Hyeon Lee, Chambers M. (2013) An 8.5 mw, 0.07 mm2 ADPLL in 28 nm CMOS with sub-ps resolution TDC and < 230 fs RMS jitter, IEEE Symposium on VLSI Circuits (VLSIC). [2] C.-C. Chung, C.Y. Ko, (2011) A Fast Phase Tracking ADPLL For Video Pixel Clock Generation In 65 Nm CMOS Technology IEEE Journal of Solid-State Circuits, Volume:46, Issue: 10. [3] Ching-Che Chung, Duo Sheng, Wei-Da Ho (2012) A Low-Power And Small-Area All-Digital Spread-Spectrum Clock Generator In 65 Nm CMOS Technology, IEEE International Symposium on VLSI Design, Automation, and Test (VLSI-DAT). [4] Chung, C.-C., Sheng, D.,Ho, W.D. (2014) A Low-Cost Low-Power All-Digital Spread-Spectrum Clock Generator, published in very large scale integration systems, IEEE transactions on Volume:PP, Issue: 99. [5] El Kholy, A. Mokhtar, A., El Ghitany, F., Badawy, A., Essawy, A., Naguib, A.,Ismail, A., Ahmed, A. (2009) A Wide Spreading Range Programmable Spread Spectrum Clock Generator Using A ΣΔ Fractional-N PLL,Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference,NEWCAS- TAISA. [6] M. Kokubo, T. Kawamoto, T. Oshima, T. Noto, M. Suzuki, S. Suzuki, T.Hayasaka, T. Takahashi, and J. Kasai, Spread-Spectrum Clock Generatorfor Serial ATA using Fractional SSCG controlled by Modulator withlevel Shifter, IEEE ISSCC, Digest of Tech. Papers, pp , Feb [7] J. Shin, at al., A Low-Jitter Added SSCG with Seamless Phase Selectionand Fast AFC for 3rd Generation Serial-ATA, IEEE 2006 CICC, pp , Sept [8] Seungjin Kim, In-Young Lee, Sang-Sung Lee, Min Su Kil, Jeongki Choi, Jinho Ko,Sang-Gug Lee (2014) A UHF-band RFID transmitter with spur reduction technique using a DLL-based spread-spectrum clock generator, published in IEEE Radio Frequency Integrated Circuits Symposium. [9] Wan-Rone Liou,Mei-Ling Yeh, Ping-Shin Chen, Chun-Chang Tseng, Tang-Yu Huang, Shu-Chia Lin, Cheng-Yu Lin, Chih- Hsiang Sun (2014) Monolithic Low-EMI CMOS DC DC Boost Converter for Portable Applications 53rd IEEE International Midwest Symposium on Circuits and Systems (MWSCAS). [10] W. Rhee, B. S. Song and A. Ali, A 1.1-GHz CMOS fractional frequency synthesizer with a 3-b third-order ΔΣ modulator IEEE J. Solid-State Circuits,vol. 35, pp , Oct [11] Zhen-Yu Li, Herming Chiueh, Juang, Y.-Z., Chin-Fong Chiu (2010) A Small Area Fully Integrated Spread-Spectrum Clock Generator With High EMI- Reduction For SATA-3.0 Applications, 53rd IEEE International Midwest Symposium on Circuits and Systems (MWSCAS). 821