Freescale Semiconductor, I

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1 Application Note Rev. 0, 5/ bit Quadrature Decoder TPU Function Set (16QD) By Milan Brejl, Ph.D. Functional Overview The 16-bit Quadrature Decoder (16QD) TPU Function Set is useful for decoding position, direction and velocity information from encoder signals in motion control systems. The function set consists of 4 TPU functions: 16-bit Quadrature Decoder (16QD) Index Channel for 16-bit Quadrature Decoder (16QD_index) Home Channel for 16-bit Quadrature Decoder (16QD_home) Velocity Support for 16-bit Quadrature Decoder (16QD_VS) The 16-bit Quadrature Decoder uses 2 input channels to decode a pair of out of phase encoder signals and produce a resulting 16-bit bidirectional position counter for the CPU. Additional input channels can also be processed. The Index channel receives a pulse on each revolution. Based on the actual direction, a Revolution Counter is incremented or decremented on the index pulse. A further additional input channel can indicate a home position. When the position is reached, appropriate actions are taken. For accurate velocity measurement, Velocity Support can be added. Figure 1 illustrates the functionality. Position Counter Index Revolution Counter -1 Home Change of direction Revolution HOME position reached Change of direction Figure 1. Signals processed by 16QD TPU function set and corresponding PC value Mo

2 Function Set Configuration The 16QD is the main function of the set. It can be used either alone, with one of the supporting functions, with two of them, or with all of them. There are no restrictions about the channel numbers any function can run on any channel. Table 1 shows the configuration options and restrictions. Table 1. 16QD TPU function set configuration options and restrictions TPU function Optional/ Mandatory How many channels Assignable channels 16QD mandatory 2 any 2 channels: and 16QD_index optional 1 or more any 16QD_home optional 1 or more any 16QD_VS optional 1 or more any The two out of phase encoder signals are called (primary channel) and (secondary channel). The Host Sequence (HSQ) bit 0 is used to determine to which channel is connected and to which is connected. The HSQ is also used for other configuration options see detailed function descriptions. Table 2 shows an example of configuration. The encoder signal is connected to channel 0 and to channel 1. TCR2 clock is selected for all timing operations. The Index channel, as well as the Home channel, reacts to low-high transition. The 16QD_index resets the Position Counter each revolution. Table 2. Example of configuration Channel TPU function HSQ Priority 0 16QD 10 high 1 16QD 11 high 2 16QD_index 10 middle 3 16QD_home 00 middle 15 16QD_VS 10 middle In this configuration, when no other functions run on the same TPU, the 16QD can receive and process input transitions at a rate of up to 606 kcounts per second at 40MHz IMB clock. When 16QD_index, 16QD_home and 16QD_VS are not used, the 16QD running standalone can count edges at a rate of up to 950 kcounts per second at 40MHz IMB clock. This is equivalent to a 1024-pulse encoder speed of more then 13,900 rpm.

3 Function Set Configuration Table 3 shows another example of configuration where the functions of the Standard Space Vector Modulation TPU function set (svmstd) run together with the 16QD functions on one TPU. This configuration enables the 16QD to receive and process input transitions at a rate of up to 392 kcounts per second at 40MHz IMB clock. This is equivalent to a 1024-pulse encoder speed of more than 5,700 rpm. The Space Vector Modulation PWM frequency can be set up to 14.2 khz to enable the maximum rpm. If the PWM frequency is set to 16 khz, the encoder pulses can be processed at a rate of 294 kcounts per second, which is equivalent to 4,300 rpm with a 1024-pulse encoder. If the PWM frequency is set to 20 khz, the encoder pulses can be processed at a rate of 196 kcounts per second, which is equivalent to 2,800 rpm with a 1024-pulse encoder. Table 3. Example of configuration Channel TPU function Priority 0 svmstd_top middle 1 svmstd_top middle 2 svmstd_top middle 3 svmstd_bottom middle 4 svmstd_bottom middle 5 svmstd_bottom middle 6 16QD high 7 16QD high 8 16QD_index low 9 16QD_home low 10 svmstd_sync low 12 16QD_VS low 15 svmstd_fault middle The Table 4 shows the TPU function code sizes. TPU function 16QD 16QD_index 16QD_home 16QD_VS Table 4. TPU function code sizes Code size 33 µ instructions + 8 entries = 41 long words 44 µ instructions + 8 entries = 52 long words 10 µ instructions + 8 entries = 18 long words 13 µ instructions + 8 entries = 21 long words

4 Configuration Order NOTE: Detailed Function Description 16-bit Quadrature Decoder (16QD) The CPU configures the TPU as follows. 1. Disables the channels by clearing the two channel priority bits on each channel used (not necessary after reset). 2. Selects the channel functions on all used channels by writing the function numbers to the channel function select bits. 3. Initializes function parameters. The parameters PC_init, RC_init, VS_period, CORR_PIN_PTR_A and CORR_PIN_PTR_B must be set before initialization, if applicable channels are used. 4. Set the HSQ (Host Sequence) bits to determine which channel is Phase A and which, and to select other function options. 5. Issues an HSR (Host Service Request) type %10 to both of the 16QD channels to initialize position counting. Issues an HSR type %10 to the 16QD_index, 16QD_home and 16QD_VS channels, if used. 6. Enables servicing by assigning high, middle or low priority to the channel priority bits. Both and channels should be assigned the same priority. A CPU routine that configures the TPU can be generated automatically using the MPC500_Quick_Start Graphical Configuration Tool. The 16QD operates on two channels and processes the incoming out-of-phase encoder signal. As a result of the processing, the bidirectional 16-bit Position Counter (PC) gets a value that reflects a position of a motion system. The PC value is incremented or decremented by 1 on each transition of or input channels see Figure 2. On initialization, the PC is set to a PC_init value entered by CPU.

5 Detailed Function Description Position Counter Position Counter Position Counter Two function modes are offered: TCR1 clock selected TCR2 clock selected Figure bit Quadrature Decoder The mode selection is done by HSQ bit 1. The HSQ bit 0 is used to determine which channel is and which is see Table 5. The user has to select on one channel and on the other, and the same mode on both channels. The function offers interpolation support for very slow quadrature signals. The parameters LastEdgeT and ActualT are updated on a Host Service Request HSR = 11. Then LastEdgeT has the value of the last incoming edge time in TCR clock and ActualT has the current value of the TCR clock. The CPU program should use 32-bit reads to ensure the coherency of the two parameters. This applies to coherent reads of LastEdgeT and ActualT as well as PC and TCR_VALUE, which is required for interpolation calculations.

6 Host Interface Written By CPU Written By TPU Written by both CPU and TPU Not Used Name Table 5. 16QD Control Bits Channel Function Select Channel Priority Host Service Bits (HSR) Host Sequence Bits (HSQ) Channel Interrupt Enable Channel Interrupt Status Options 16QD function number (Assigned during assembly the DPTRAM code from library TPU functions) 00 Channel Disabled 01 Low Priority 10 Middle Priority 11 High Priority 00 No Host Service Request 01 Not used 10 Initialization 11 Get LastEdgeT and ActualT x0 (primary channel) x1 (secondary channel) 0x TCR1 clock selected 1x TCR2 clock selected x Not used x Not used

7 Detailed Function Description Table 6. 16QD Parameter RAM Channel Parameter LastEdgeT 1 ActualT 2 TCR_VALUE 3 PC 4 RC 5 CORR_PIN_PTR_A 6 CHAN_PINSTATE_A 7 0 LastDir PC_init 4 RC_init 5 CORR_PIN_PTR_B 6 CHAN_PINSTATE_B 7 Table 7. 16QD parameter description Parameter Format Description Parameters written by CPU PC_init 16-bit signed integer Position Counter initialization value RC_init 16-bit signed integer Revolution Counter initialization value (if 16QD_index is used) CORR_PIN_PTR_A 16-bit unsigned integer $00XC, where X is a number of PhaseB channel CORR_PIN_PTR_B 16-bit unsigned integer $00XC, where X is a number of PhaseA channel Parameters written by both TPU and CPU PC 16-bit signed integer Position Counter value RC 16-bit signed integer Revolution Counter value (if 16QD_index is used) Parameters written by TPU LastEdgeT 16-bit unsigned integer TCR time of last transition * ActualT 16-bit unsigned integer Actual TCR time * TCR_VALUE 16-bit unsigned integer TCR time of last transition The actual state of the pin is CHAN_PINSTATE_A $8000 or $0000 $8000 high, CHAN_PINSTATE_B $0000 low

8 Table 7. 16QD parameter description Parameter Format Description LastDir $8000 or $0000 Direction $8000 incremental, $0000 decremental * The parameter values are entered by TPU on Host Service Request 11 (Get LastEdgeT and ActualT). Performance Table 8. 16QD State Statistics NOTE: EDGE EDGE State Max IMB Clock Cycles RAM Accesses by TPU INIT 24 4 GET_TIME 8 3 EDGE 30 9 Execution times do not include the time slot transition time (TST = 10 or 14 IMB clocks) EDGE EDGE EDGE EDGE GET EDGE EDGE EDGE EDGE TIME HSR 11 Figure 3. 16QD timing EDGE EDGE EDGE EDGE EDGE EDGE EDGE INIT GET_TIME EDGE HSR = 10 HSR = 11 Figure 4. 16QD state diagram

9 Detailed Function Description Noise Immunity The input signals can be disturbed by impulse noise. The TPU hardware rejects short input pulses of less then a configurable number of IMB clocks. Longer pulses are processed by the TPU. Furthermore, the function itself uses a pin history to reject any short error pulse that is long enough to get through the hardware filter, but not long enough to last from the actual transition time to the time that the TPU services the channel. Even longer error pulses are counted on both edges resulting a net error of zero on PC. See examples of error pulse processing on Figure 5. Position Counter Index Channel for 16-bit Quadrature Decoder (16QD_index) +1 X X X +1 Position Counter Figure 5. Noise immunity The 16QD_index function monitors an input signal that indicates each revolution of the motion system with a pulse. The function can be configured to react on either a low-high transition or a high-low transition. This way the user can select whether the INDEX signal is of positive or negative polarity. When the specified action happens, the 16QD_index function increments or decrements the Revolution Counter by 1, depending on the current direction, and generates a channel interrupt. Optionally it can also reset the Position Counter to its initialization value (PC_init). Four function modes are offered based on these options: positive INDEX pulse polarity, no reset positive INDEX pulse polarity, reset Position Counter negative INDEX pulse polarity, no reset negative INDEX pulse polarity, reset Position Counter The mode selection is determined by HSQ bits see Table 14.

10 The function is actually more complicated to ensure its robustness. The INDEX pulse is presumed to be positioned at one of the places where both and signals have the same state see Figure 6. Index OR Index Figure 6. INDEX pulse positioning The transition of the INDEX pulse does not come exactly at the same time as the or transitions. When the INDEX pulse transition comes earlier, the function postpones its action until both and signals have the same state and the or B transition is processed. As a result of this, the RC is always incremented or decremented after the PC is incremented or decremented. Index Figure 7. Change of direction during INDEX pulse Another difficult situation happens when the motion system stops when the INDEX pulse is on, changes its direction and then goes back. The signal

11 Detailed Function Description coming to the INDEX channel is the same as during normal rotation a lowhigh transition followed by a high-low transition (positive polarity). However, the Revolution Counter value, before the pulse and after the pulse, should be equal. The 16QD_index function checks the motion system direction on the high-low transition and compares it with a previous direction on the low-high transition. If they are not equal, the Revolution Counter is decremented or incremented back. Host Interface Written By CPU Written by both CPU and TPU 3 2 Written By TPU 0 0 Name Table 9. 16QD_index Control Bits Channel Function Select Channel Priority Host Service Bits (HSR) Host Sequence Bits (HSQ) Channel Interrupt Enable Channel Interrupt Status Not Used Options 16QD_index function number (Assigned during assembly the DPTRAM code from library TPU functions) 00 Channel Disabled 01 Low Priority 10 Middle Priority 11 High Priority 00 No Host Service Request 01 Not used 10 Initialization 11 Not used x0 Detection of low-high transition x1 Detection of high-low transition 0x Position Counter is NOT reset to PC_init on transition 1x Position Counter is reset to PC_init on transition 0 Channel Interrupt Disabled 1 Channel Interrupt Enabled 0 Interrupt Not Asserted 1 Interrupt Asserted

12 Performance Table QD_index Parameter RAM Channel Parameter PC_VS_ADDR 7 Index channel Table QD_Index parameter description Parameter Format Description Parameters written by CPU PC_VS_ADDR 16-bit unsigned integer $00XC, where X is a number of VS channel $00000 if no VS channel is used. Table QD_index State Statistics mode: Don t Reset PC (HSQ1 = 0) State Max IMB Clock Cycles RAM Accesses by TPU INIT 16 2 LH0, HL HL0, LH LINK_LH0, LINK_HL LINK_HL0, LINK_LH Table QD_index State Statistics mode: Reset PC (HSQ1 = 1) State Max IMB Clock Cycles RAM Accesses by TPU INIT 16 2 LH0, HL HL0, LH LINK_LH0, LINK_HL LINK_HL0, LINK_LH NOTE: Execution times do not include the time slot transition time (TST = 10 or 14 IMB clocks)

13 Detailed Function Description HSQ = x0 Index LH0 LINK_LH0 HL0 LINK_HL0 HSQ = x1 Index HL1 LINK_HL1 LH1 LINK_LH1 link Home Channel for 16-bit Quadrature Decoder (16QD_home) INIT HSR = 10 Figure 8. 16QD_index timing Figure 9. 16QD_index state diagram The 16QD_home function monitors an input signal, which indicates a HOMEposition of the motion system by a pulse. The function can be configured to react on either a low-high transition, a high-low transition or both transitions. This way the user can select whether the HOME-signal is of positive or negative polarity and the action to be taken when the HOME-position is either arrived at, left, or both. Three function modes are offered based on these options: Detection of low-high transition Detection of high-low transition Detection of any transition LINK_LH0 LINK_HL1 LH0 HL1 HL0 LH1 LINK_HL0 LINK_LH1

14 The mode selection is done by the HSQ bits see Table 14. When the specified action happens the 16QD_home function resets the Position Counter and the Revolution Counter to their initialization values (PC_init, RC_init) and generates a channel interrupt. Host Interface Written By CPU Written By TPU Written by both CPU and TPU Not Used Table QD_home Control Bits Name Channel Function Select Channel Priority Host Service Bits (HSR) Host Sequence Bits (HSQ) Channel Interrupt Enable Channel Interrupt Status Options 16QD_home function number (Assigned during assembly the DPTRAM code from library TPU functions) 00 Channel Disabled 01 Low Priority 10 Middle Priority 11 High Priority 00 No Host Service Request 01 Not used 10 Initialization 11 Not used 00 Detection of low-high transition 01 Detection of high-low transition 1x Detection of any transition 0 Channel Interrupt Disabled 1 Channel Interrupt Enabled 0 Interrupt Not Asserted 1 Interrupt Asserted

15 Detailed Function Description Table QD_home Parameter RAM Channel Parameter PC_VS_ADDR 7 Home channel Table QD_home parameter description Performance NOTE: Parameter Format Description Parameters written by CPU PC_VS_ADDR 16-bit unsigned integer $00XC, where X is a number of VS channel $00000 if no VS channel is used. Table QD_home State Statistics State Max IMB Clock Cycles RAM Accesses by TPU INIT 8 0 HOME 10 4 Execution times do not include the time slot transition time (TST = 10 or 14 IMB clocks)

16 HSQ = 00 Position Counter PC_init Revolution Counter -1 RC_init Home HOME HSQ = 01 Position Counter PC_init Revolution Counter -1 RC_init Home HOME HSQ = 1x Position Counter Revolution Counter Home PC_init PC_init -1 RC_init HOME Figure QD_home timing INIT HSR = 10 HOME Figure QD_home state diagram RC_init HOME

17 Detailed Function Description Velocity Support for 16-bit Quadrature Decoder (16QD_VS) The 16QD_VS runs on an unconnected TPU channel. The function periodically measures the difference of the 16QD Position Counter (PD Position Difference) and the exact time corresponding to it (TD Time Difference). The Time Difference varies slightly from the period of measurement (VS_period). The Time Difference is calculated as a difference between the time of the last counted transition and the time of the transition prior to the first one counted. It is illustrated on Figure 12. VS_period Position Counter Figure 12. Velocity Support The Time Difference and Position Difference values can be used by the CPU program to calculate the exact velocity of the motion system. The function can use the TCR1 or TCR2 clock for VS_period measurement. Two function modes are offered based on these options: TCR1 clock selected TCR2 clock selected Time Difference Position Difference = 9 The mode selection is done by HSQ bits see Table 18. The selected clock must be the same as the main function 16QD uses.

18 Host Interface Written By CPU Written By TPU Written by both CPU and TPU Not Used 3 2 Name Table QD_VS Control Bits Channel Function Select Channel Priority Host Service Bits (HSR) Host Sequence Bits (HSQ) Channel Interrupt Enable Channel Interrupt Status Options 16QD_VS function number (Assigned during assembly the DPTRAM code from library TPU functions) 00 Channel Disabled 01 Low Priority 10 Middle Priority 11 High Priority 00 No Host Service Request 01 Not used 10 Initialization 11 Not used 0x TCR1 clock selected 1x TCR2 clock selected 0 Channel Interrupt Disabled 1 Channel Interrupt Enabled 0 Interrupt Not Asserted 1 Interrupt Asserted TPU function 16QD_VS generates an interrupt after each VS_period. Table QD_VS Parameter RAM Channel Parameter VS_period VS_PD 5 VS_TD 6 PC_VS 7 EDGE_TIME Velocity Support 0 0

19 Detailed Function Description Table QD_VS parameter description Parameter Format Description Parameters written by CPU VS_period 16-bit positive integer Period of VS calculations in TCR clocks Parameters written by TPU VS_PD 16-bit signed integer Position difference VS_TD 16-bit unsigned integer Time difference Other parameters are just for TPU function inner use. Performance NOTE: Table QD_VS State Statistics State Max IMB Clock Cycles RAM Accesses by TPU INIT 8 1 VS 18 9 Execution times do not include the time slot transition time (TST = 10 or 14 IMB clocks) VS VS VS VS VS Figure QD_VS timing INIT HSR = 10 VS Figure QD_VS state diagram

20 Rev. 0 5/2003