AMBA Generic Infra Red Interface

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2 AMBA Generic Infra Red Interface Datasheet Copyright 1998 ARM Limited. All rights reserved. Release Information The following changes have been made to this document. Change History Date Issue Confidentiality Change Jan 1998 A Non-Confidential First release Proprietary Notice Words and logos marked with or are registered trademarks or trademarks owned by ARM Limited, except as otherwise stated below in this proprietary notice. Other brands and names mentioned herein may be the trademarks of their respective owners. Neither the whole nor any part of the information contained in, or the product described in, this document may be adapted or reproduced in any material form except with the prior written permission of the copyright holder. The product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given by ARM in good faith. However, all warranties implied or expressed, including but not limited to implied warranties or merchantability, or fitness for purpose, are excluded. This document is intended only to assist the reader in the use of the product. ARM Ltd shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product. Confidentiality Status This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to. Product Status The information in this document is final, that is for a developed product. Web Address ii Copyright 1998 ARM Limited. All rights reserved. ARM DDI 0097A

3 Contents AMBA Generic Infra Red Interface Datasheet Chapter 1 Chapter 2 Chapter 3 Chapter 4 Chapter 5 Introduction 1.1 Overview and Features Signal Descriptions 2.1 APB Signals Internal Signals Functional Description 3.1 Block Diagram Overview Programmer s Model 4.1 Introduction Summary of Generic Infra Red Registers Register Descriptions Interrupts Generic Infra Red Interface Test Harness 5.1 Test Registers ARM DDI 0097A Copyright 1998 ARM Limited. All rights reserved. iii

6 Introduction 1.1 Overview and Features Overview Features Overview The Generic Infra Red Interface is an AMBA slave module that connects to the Advanced Peripheral Bus (APB). For more information about AMBA, please refer to the AMBA Specification (ARM IHI 0001). The Generic Infra Red Interface provides the interface between the remote control and the system. It supports a fully flexible mechanism based on programmable pulse widths. The peripheral is capable of transmitting or receiving a modulated carrier or direct digital signal. The encoding and decoding of the information transferred in the bitstream is performed in software allowing further flexibility Features The Generic Infra Red Interface supports: modulated or digital TX and RX 16 deep buffered TX and RX FIFOs direct interrupts for TX and RX FIFO level monitoring TX and RX FIFO level and function status register load and store multiple instructions. The following key features are programmable: modulation and demodulation enable independent TX and RX function enables independent TX and RX FIFO enables, flushed when disabled modulated signal detection tolerance signal synchronization on either or both edges of the received signal RX and TX FIFO interrupts TX clock frequency RX clock frequency TX clock duty cycle. Additional test registers and modes are implemented to provide efficient testing. 1-2 Copyright 1998 ARM Limited. All rights reserved. ARM DDI 0097A

8 Signal Descriptions 2.1 APB Signals The Generic Infra Red Interface peripheral is connected to the APB bus as a slave. Table 2-1 describes the APB signals used. Name Type Source/Destination Description BnRES In Reset Controller ASB Reset signal Initiates a reset. Table 2-1 APB signal descriptions BCLK In ASB Bus ASB Clock input signal Times all ASB bus transfers. PA[6:2] In APB Bus Provides the peripherals internal register map address source. PD[17:0] BiDir APB Bus Driven by APB bridge writes, by the peripheral during reads. PSEL In APB Bus APB Slave Select When HIGH, the peripheral is selected. PSTB In APB Bus Times all APB bus transfers. PWRITE In APB Bus Defines APB access type. Write when HIGH, read when LOW. 2-2 Copyright 1998 ARM Limited. All rights reserved. ARM DDI 0097A

9 Signal Descriptions 2.2 Internal Signals Table 2-2 Internal signal descriptions Symbol Type Source/Destination Name and Function GIRIN in PAD Generic Infra Red Receive Input Input signal from an IR photodetector or receiver. If the signal is from a simple detector, demodulation is required to recover the baseband signal. GIROUT Out PAD Generic Infra Red Transmit Signal output to IR device. If the IR device is a simple detector, the signal will be modulated onto a carrier. Otherwise, the signal is a serial stream of data at baseband, and modulation is performed off-chip. GIRRXINT Out INT CTRL Generic Infra Red Receive Interrupt Receive FIFO interrupt (FIFO half-full). GIRTXINT Out INT CTRL Generic Infra Red Transmit Interrupt Transmit FIFO interrupt FIFO half-full. REFCLK In Clock Generation External Reference Clock Free running clock. It must be synchronous to, and an integer multiple of, BCLK. ARM DDI 0097A Copyright 1998 ARM Limited. All rights reserved. 2-3

12 Functional Description 3.1 Block Diagram The major functional blocks of the Generic Infra Red Interface are shown in Figure 3-1. Figure 3-1 Generic Infra Red Interface block diagram 3-2 Copyright 1998 ARM Limited. All rights reserved. ARM DDI 0097A

13 Functional Description 3.2 Overview Receive processing The received signal from the pad is a stream of digital symbols (HIGH and LOW values) which may or may not be modulated onto a relatively high-frequency carrier signal (in the range khz). The overall purpose of the receive functions is to measure the duration of these digital symbols, and present this information to the system for full decoding in software. For situations where the received signal is modulated onto a carrier signal, a programmable demodulator function is provided that recovers the digital data stream from the carrier. When the input signal does not contain a carrier, or has already been demodulated by external hardware, this function can be disabled. In either case, the input signal is first synchronized and squared up with respect to the local clock source, to improve the signal edge quality and reduce noise. This cleaned signal is then passed through an edge detection function, which detects edges in the data signal. The entire receiver processor core runs at a frequency which is a user-programmable division of REFCLK, the externally supplied clock. The frequency of the generated receive clock, RxClock, must be set dependent on the expected symbol rate of the input. If the input is modulated by a carrier, RxClock must be programmed to 16 times the carrier frequency to allow successful demodulation. The demodulated data (either direct from the input synchronization stage or from the demodulator) is then applied to a timer/counter that measures the duration of symbols in units of RxClock. This timer can be configured to measure the duration between either or both edges in the data stream Receive demodulation When enabled, the demodulator is used to recover the baseband serial data from the carrier signal. The function works by aligning to rising edges in the modulated signal and predicting when the next similar edge will arrive, within predefined limits (as defined the windowctrl bits within the GIRFCR control register). Because the receiver clock must be 16 times the carrier frequency, the counter expects rising edges once every 16 ticks. In addition, some persistence checking is performed by checking for four consecutive occurrences of a valid input edge (where valid means that the edge arrives within the predefined limits specified above). If these conditions are met, the input is considered ARM DDI 0097A Copyright 1998 ARM Limited. All rights reserved. 3-3

14 Functional Description valid and the demodulated output is produced. A similar persistence check is applied to detect the end of a carrier burst. The demodulator is therefore insensitive to a certain degree of noise and frequency inaccuracy. The output of the demodulator is shifted by approaching four carrier periods from the input. This should not affect the final decoding because the delay will be symmetrical between the start and end of the HIGH (modulated) symbols Receive FIFO information The demodulated signal (either via the demodulator or directly from the input filter function) is then applied to a timer circuit which measures the duration of the symbols in the decoded signal.the actual circuit is formed from an 18-bit timer/counter, clocked by RxClock. When an edge is detected (marking the end of the current symbol), the 16 MSBs (most significant bits) of this count are stored in the receive FIFO as a measure of symbol duration. Therefore, the duration of the symbol is derived from the value stored in the FIFO as follows: where: Duration of Symbol = N x (1/F rx ) x 4 F rx = Programmed receive clock rate N = FIFO count value (bits [15:0] of GIRDATAR when read). The maximum symbol duration which can be output is calculated as follows: Tmax = (2 16-1) x (1/F tx ) x 4 For example, with an expected carrier rate of 36kHz, the programmed receive clock would be set to (nominally) 576kHz, and the maximum measurable time is approximately 455 ms. If there is no carrier to demodulate, the frequency of the receive clock can be set with more freedom. A single bit representing the logic level of the most recently measured symbol, is stored in the FIFO at the same time as the counter value. On reading GIRDATAR, the 17 bits from the FIFO are appended with a further bit, RxDataAvail. This bit indicates whether there is further data in the FIFO after the current read. When HIGH, RxDataAvail indicates that there is more data to be read from the FIFO. If RxDataAvail is LOW, it does not guarantee that the FIFO is empty. Thus a software routine wishing to empty the FIFO reads GIRDATAR until bit 17 is LOW, then reads from GIRSTAT to confirm that the FIFO is empty. The end of the data transmission is detected when, following a data burst, the input becomes idle for so long that the duration timer reaches its 18-bit limit. This is reported via the FIFO as all 1 s. This condition is used to report a timeout condition in the status register. 3-4 Copyright 1998 ARM Limited. All rights reserved. ARM DDI 0097A

15 Functional Description An interrupt output, GIRRXINT, is defined, which can be set to indicate either that the receive. FIFO is half full or more, or that the FIFO is not empty. The receive FIFO is 17 bits wide and 16 bits deep. The Data Available bit is generated on the fly as a read occurs from GIRDATAR and is not stored in the FIFO itself Transmit processing In the transmit direction, output pulses are generated in a similarly generic fashion. Count values are loaded into a FIFO by the software and the output is controlled HIGH and LOW, according to these counts. An additional bit indicates the logic level is represented. The TX FIFO is 17 bits wide by 16 bits deep. A transmit clock frequency is programmed using a 16-bit clock divider identical to that used in the receive portion. The frequency chosen will be determined by the resolution and length of the output symbols required in unmodulated mode. When modulation is selected the frequency must be 16 times the carrier frequency required. When transmission is enabled and the FIFO contains entries, the 16-bit value representing the required duration will be loaded into the MSB positions of an 18-bit timer similar to that used in the receive direction. The timer is then allowed to decrement at the programmed transmit clock rate until it reaches zero. The next value is then loaded from the FIFO and the timer process restarts. End of transmission will be assumed when the present timer value reaches zero, and the TX FIFO is empty. The output level will always return to a stable LOW level when transmission is completed. An interrupt output, GIRTXINT, is available. This can be programmed to indicate either that the TX FIFO is half full or less, or that the transmitter is not busy (disabled or completed). The duration of each symbol is: where, Transmit modulation Duration = N x (1/F tx ) x 4 F tx = Programmed transmit clock rate N = FIFO count (bits [15:0] of GIRDATAR when written). If carrier generation is enabled, the data stream is modulated by the carrier such that marks or HIGH periods will be replaced by carrier bursts of equivalent duration. Spaces in the output stream are represented by the absence of the carrier. ARM DDI 0097A Copyright 1998 ARM Limited. All rights reserved. 3-5

16 Functional Description The GIRTXDUTYCR register is used in the generation of the carrier signal, when the signal is enabled. The register controls the duty cycle of the generated carrier signal. The relationship between the register setting and the resulting carrier duty cycle is: Register = 1111 Register = 0000 Register = 0001 Register = 0010 Reserved Carrier is 1/16 HIGH, 15/16 LOW Carrier is 2/16 HIGH, 14/16 LOW Carrier is 3/16 HIGH, 13/16 LOW; and so on Note The minimum HIGH phase duration supported is limited to 2/16 of the carrier period Clock dividers The reference clock is used to drive programmable dividers within the block, which generate the internal clock frequencies used by the transmit and receive blocks. The internal frequency must be 16 times the carrier frequency when modulation or demodulation is in use. If a carrier is not required, the clock rate selected does not have to be 16 times the symbol rate (though often it will be). A separate divider is provided for transmit and receive paths. The GIRRXGENCR and GIRTXGENCR registers provide the divisor values to the dividers. When a carrier is to be demodulated on the receive or generated on the transmit, the required divisor to create the correct internal clock is given by: Divisor = (Fsc / (16 x carrier rate)) 1 where Fsc is the input system clock frequency. When no demodulation or modulation is required, the internal frequency can be set by the incoming symbol rate (the repetition rate of the HIGHs and LOWs on the data). Assuming the use of 16 times the symbol rate, the required divisor to create the correct internal clock is given by: Divisor = (Fsc / (16 x symbol rate)) 1 where Fsc is the input system clock frequency. 3-6 Copyright 1998 ARM Limited. All rights reserved. ARM DDI 0097A

17 Chapter 4 Programmer s Model Introduction on page 4-2 Summary of Generic Infra Red Registers on page 4-3 Register Descriptions on page 4-4 Interrupts on page 4-9. ARM DDI 0097A Copyright 1998 ARM Limited. All rights reserved. 4-1

18 Programmer s Model 4.1 Introduction The base address of the Generic Infra Red Interface is not fixed and is dependant on the system implementation. However, the offset of any register from the base address is always fixed. Note The locations at offsets +0x20 through +0x28 are reserved for test purposes and should not be used during normal operation. 4-2 Copyright 1998 ARM Limited. All rights reserved. ARM DDI 0097A

19 Programmer s Model 4.2 Summary of Generic Infra Red Registers The following registers are provided: Table 4-1 Generic Infra Red Interface registers Offset Type Width Reset Value Name Description 0x00 R/W 12 0x000 GIRFCR Function Control Register 0x04 R/W 16 0x0000 GIRTXGENCR TX Clock Generator Control Register 0x08 R/W 16 0x0000 GIRRXGENCR RX Clock Generator Control Register 0x0C R/W 4 0x0 GIRTXDUTYCR TX Carrier Duty Cycle Register 0x10 R 6 0x10 GIRSTAT Status Register 0x40 0x7C R/W 18 Undefined GIRDATAR TX/RX Data Register, 16 locations to provide load/store multiple instructions ARM DDI 0097A Copyright 1998 ARM Limited. All rights reserved. 4-3

20 Programmer s Model 4.3 Register Descriptions GIRFCR - IR Function Control Register [12] (+0x00) This register acts as the main source of control for the IR interface. Separate enables are provided for transmit and receive paths. In addition, the FIFOs can be separately enabled. Bit Name Function Table 4-2 GIRFCR bit functions 11 TXIntCtrl TX interrupt control bit: 1 = When Transmit function enabled, GIRTXINT raised when transmitter is not busy, ie. transmission completed. 0 = GIRTXINT raised when TX FIFO half full or below, independent of whether Transmit function is enabled or disabled. 10 RXIntCtrl RX interrupt control bit: 1 = When Receive function enabled, GIRRXINT raised when RX FIFO is not empty. 0 = When Receive function enabled, GIRRXINT raised when RX FIFO is half full or greater. 9 TXEnable Enable transmitter function: 1 = enable transmission. 0 = disable transmission. 8 RXEnable Enable receiver function: 1 = enable receiver. 0 = disable receiver. 7 txfifoen Enable TX FIFO: 1 = FIFO enabled to accept data. 0 = FIFO disabled and flushed. 6 rxfifoen Enable RX FIFO: 1 = FIFO enabled to accept data. 0 = FIFO disabled and flushed. 4-4 Copyright 1998 ARM Limited. All rights reserved. ARM DDI 0097A

21 Programmer s Model Table 4-2 GIRFCR bit functions (continued) Bit Name Function 5 moden Enable modulation: 1 = Output level is modulated with a carrier signal as described below. 0 = Output level is set by bit 16 of the TX FIFO. 4 demoden Enable demodulation: 1 = Demodulation enabled. 0 = Demodulation disabled. 3:2 edgectrl[1:0] Edge detector control bits for pulse timer in RX direction: 00 : Edge detection disabled. 01 : Enable falling edges to restart timer. 10 : Enable rising edge to restart timer. 11 : Either edge will restart timer (used in demodulation mode). 1:0 windowctrl[1:0] Limit control bits for window comparator: 00 : Limits = +3 / : Limits = +3 / : Limits = +4 / : Limits = +4 / GIRTXGENCR - Transmit Clock Generator Control Register [16] (+0x04) This register holds the value of the divisor to be applied to the internal programmable divider for the Transmit functions. Bit Name Function Table 4-3 GIRTXGENCR bit functions 15:0 ckdiv Divisor value for the programmable divider/clock generator. Value of 0 is reserved. Value of 1 will result in divide by 2. Value of 2 will result in divide by 3, and so on. When the TX function is disabled, the value written to this register is applied directly to the internal programmable TX clock divider. When the TX function is enabled, changes to this register value only take effect when the associated internal counter reaches zero. ARM DDI 0097A Copyright 1998 ARM Limited. All rights reserved. 4-5

22 Programmer s Model GIRRXGENCR - Receive Clock Generator Control Register [16] (+0x08) This register holds the value of the divisor to be applied to the internal programmable divider for the Receive functions. Bit Name Function Table 4-4 GIRRXGENCR bit functions 15:0 ckdiv Divisor value for the programmable divider/clock generator: Value of 0 is reserved. Value of 1 will result in divide by 2. Value of 2 will result in divide by 3, and so on. When the RX function is disabled, the value written to this register is applied directly to the internal programmable RX clock divider. When the RX function is enabled, changes to this register value only take effect when the associated internal counter reaches zero GIRTXDUTYCR - TX Carrier Duty Cycle Control Register [4] (+0x0C) This register is used to control the duration of the HIGH phase of the transmitted carrier signal. Bit Name Function Table 4-5 GIRTXDUTYCR bit functions 3:0 high phase Duration of the high phase time of the carrier signal, as a multiple of x16 clock ticks: 1111 : Reserved : Carrier HIGH time = 1/16 of period (see note below) : Carrier HIGH time = 2/16 of period : Carrier HIGH time = 3/16 of period, and so on. Note The minimum HIGH phase duration supported is limited to 2/16 of the carrier period. 4-6 Copyright 1998 ARM Limited. All rights reserved. ARM DDI 0097A

23 Programmer s Model GIRDATAR - Generic IR Data Register [18] (+0x40 0x7C) This register is used to transfer data to and from the module. A write operation to this location results in a write to the TX FIFO. A read causes data to be read from the RX FIFO. The register spans 16 words of address so that the multiple load and store ARM instructions LDM and STM can be used. Bit Name Function Table 4-6 GIRDATAR bit functions 17 RXDataAvail This bit is undefined in write mode.in read mode, this bit reports whether the RX FIFO contains any more data after the current read: 1: more data to be read. 0: FIFO may be empty after the current read operation. 16 txval/rxval In write mode, this bit gives the polarity of the bit to be transmitted. In read mode, this bit shows the level of the received bit. 15:0 data In write mode, these bits give the required duration of the transmitted bit. If modulation is enabled, a 1 will be represented by a burst of carrier for the specified time. Otherwise, the output will be a logic level for the specified time. ARM DDI 0097A Copyright 1998 ARM Limited. All rights reserved. 4-7

24 Programmer s Model GIRSTAT - Generic IR Status Register [6] (+0x10) This read-only register contains flags describing the current state of the module. Bit Name Function 5 TXFull TX FIFO full. 4 RXEmpty RX FIFO empty. Table 4-7 GENIRSTAT bit functions 3 TXBusy Transmitter busy: Transmit function enabled and symbol being transmitted. 2 RXBusy Receiver busy: Receive function enabled and not timed out. 1 RXOverrun RX overrun (Attempt made to write to RX FIFO, but FIFO full). Active HIGH. 0 RXTimeout This bit is set HIGH to indicate that, while the receiver is enabled, the input has been stable so long that the duration timer has advanced to its limit. 4-8 Copyright 1998 ARM Limited. All rights reserved. ARM DDI 0097A

25 Programmer s Model 4.4 Interrupts Two interrupt signals, GIRRXINT and GIRTXINT, are available as internal output signals from the peripheral. Both these interrupts are programmable such that they happen when certain conditions occur within the peripheral. In the case of the GIRTXINT interrupt signal, this is controlled by the TXIntCtrl bit (GIRFCR bit [11]). When the TXIntCtrl bit is written with a logic one, the GIRTXINT interrupt is asserted HIGH when the transmitter is not busy, in other words the transmission of the last value in the TX FIFO has completed. When the TXIntCtrl bit is written with a logic zero, the GIRTXINT interrupt is asserted HIGH when the TX FIFO is half full or below.this action occurs irrespective of whether the transmit function is enabled or disabled. In the case of the GIRRXINT interrupt signal, this is controlled by the RXIntCtrl bit (GIRFCR bit [10]). When the RXIntCtrl bit is written with a logic one and the RX function is enabled, the GIRRXINT interrupt is asserted HIGH when the RX FIFO contains one or more entries. When the RXIntCtrl bit is written with a logic zero and the RX function is enabled, the GIRRXINT interrupt is asserted HIGH when the RX FIFO is half full or greater. ARM DDI 0097A Copyright 1998 ARM Limited. All rights reserved. 4-9

28 Generic Infra Red Interface Test Harness 5.1 Test Registers Extra registers are provided inside the Generic Infra Red Interface for test purposes only and should not be accessed during normal mode of operation. They are memory mapped as follows: Table 5-1 Test registers Address Offset Type Width Reset Value Name Description 0x20 R/W 16 0x0000 GIRTCR Generic IR Test Control Register 0x24 R 16 0x0000 GIRTTXCD Generic IR Test Transmit Current Clock Divider Value 0x28 R 16 0x0000 GIRTRXCD Generic IR Test Receive Current Clock Divider Value GIRTCR - Test Control Register [16] (+0x20) This register controls the clock and input signals to the block for test purposes. All bits of the GIRTCR register are readable, but only bit 15 and bits [6:0] have write access. Bit Name Function Table 5-2 GIRTCR bit functions 15 TicBres When HIGH, the peripheral s internal logic (with the exception of the test registers) is reset as per the action of the external BnRES signal. When LOW, the reset action is removed. 14 TXTestCount When set HIGH, this bit enables the 18-bit TX Duration counter to be partitioned for efficient testing. 13 TXTDecUpper When TXTestCount and this bit are HIGH, decrementing of the upper 16 bits of the TX Duration counter is allowed. 12 TXTDecLower When TXTestCount and this bit are HIGH, decrementing of the lower two bits of the TX Duration counter is allowed. 11 RXClock Returns the current clock value from the receive clock divider. 10 TXClock Returns current clock value from the transmit clock divider. 9 GIROUT Returns current serial output value. 5-2 Copyright 1998 ARM Limited. All rights reserved. ARM DDI 0097A

29 Generic Infra Red Interface Test Harness Table 5-2 GIRTCR bit functions (continued) Bit Name Function 8 GIRRXINT Returns current value of RX interrupt. 7 GIRTXINT Returns current value of TX interrupt. 6 QuickCount This bit controls the operation of the 18-bit timer/counter in the Receive direction and the two 16-bit dividers which generate TXClock and RXClock. When set to 1, the counters are partitioned into four 4-bit chunks and one 2-bit chunk for efficient testing. 5 RegRXSerial Registered data bit to drive the receive data path in test mode. 4 TestBypass When set, this bit causes both programmable dividers to be bypassed to shorten test times. In other words, IntGirClk is connected to RXClock and TXClock directly. 3 RegGirClk Registered clock bit. This may be used as a clock source in test modes by toggling the value on successive writes. 2:1 teststatus Clock Control bits X0: Normal operation. The REFCLK input is used as the clock source for the dividers, IntGirClk. 01: PSEL ANDed with PSTRB is driven as the internal clock, IntGirClk. When this clock source is selected, every access to the block generates a positive clock pulse internally. 11: RegGirClk is used as the clock, using toggle writes as described above. 0 UseTestSigs Test mux control 1: the RegRXSerial bit is used to drive the input data paths. 0: the input signal (GirinIn) is used as normal GIRTTXCD - Test Transmit Clock Divider Value [16] (+0x24) This read-only register returns the current value of the 16-bit clock divider value used to generate the Transmit side clock, TXClock GIRTRXCD - Test Receive Clock Divider Value [16] (+0x28) This read-only register returns the current value of the 16-bit clock divider value used to generate the Receive side clock, RXClock. ARM DDI 0097A Copyright 1998 ARM Limited. All rights reserved. 5-3

CDR in Mercury Devices

CDR in Mercury Devices February 2001, ver. 1.0 Application Note 130 Introduction Preliminary Information High-speed serial data transmission allows designers to transmit highbandwidth data using differential,