ES51998(60000counts) DMM Analog front end/insulation/peak

Transcription

1 Features counts dual-slope SDC (2 cnvs/s.) Input signal full scale: 630mV (Max count) Built-in 600 counts fast speed (x0) FDC Fast DC conversion rate: 20 times/s 00L LQFP package 3V DC regulated power supply Support digital multi-meter function *Voltage measurement (C/DC) *Current measurement (C/DC) *Support CDC RMS mode *Dual mode for frequency with voltage or current *Resistance measurement (600.00Ω MΩ) *Conductance measurement (60.00nS) *Capacitance measurement (6.000nF 60.00mF) (Taiwan patent no.: , ) (China patent no.: ) *Diode or continuity mode measurement *Frequency counter with duty cycle display: Hz MHz 5.0% 95.0% DP mode (C or DC mode is available) 3dB BW selectable for low pass filter at C mode (Taiwan patent no.: ) (China patent no.: X) Band-gap reference voltage output Peak-hold measurement (Taiwan patent no.:47648) 3-wire serial bus for MPU I/O port MPU I/O power level selectable by external pins On-chip buzzer driver and frequency selectable by MPU command High-crest-factor signal detection (Taiwan patent no.: 23466) Multi-level battery voltage detection Support sleep mode by external chip select pin pplication Clamp-on meter Digital multi-meter Description ES5998 is an analog frond end chip of DMM built-in 60000(SDC)/600(FDC) counts dual DCs. The SDC is operated at slower speed for higher resolution. The FDC is operated at higher speed for lower resolution. ES5998 provides voltage & current (C/DC) measurement, resistance measurement, capacitance measurement, diode/continuity measurement, frequency measurement, duty cycle measurement and voltage peak-hold function. n analog switches network is built-in for insulation resistance application. The ES5998 also supports multi-level battery detection, low-pass-filter feature for C mode and dual mode measurement for VF & F. 3-wire serial bus for MPU I/O port will be used easily for firmware design. Flexible function design is supported for different kinds of DMM or Clamp-on meter application.. ver 2.6

2 ver ES5998(60000counts) Pin ssignment IRVH 7 BUFH CZH 2 BUFOUT 3 CL 4 CL- 5 CIL 6 CZL 7 BUFL 8 RZ 9 OHMC3 0 OHMC2 OHMC 2 VRH 3 V 4 V- 5 EXTSRC 6 IRVH0 8 OR 9 VR5 20 VR4 2 VR3 22 VR2 23 OVSG 24 VR 25 IVSH 37 IVSL 38 DP 39 CVL 43 CVH 44 DI 45 DO 46 TEST5 47 SGND 36 IRVL 35 IRVG 34 C- 48 C 49 R9K 55 RK 56 OVX 26 OVH 27 LPC 57 LPC2 58 LPC3 59 LPFOUT 60 PMIN 6 PMX 62 CPKIN IRR5 29 IRR4 30 IRR3 3 IRR2 32 IRR 33 STBEEP 64 FREQ CIH 00 OSC2 78 OSC 79 CS 80 IO_CTRL 8 BZOUT DT_new 84 SCLK 85 SDT 86 C 87 C- 88 LBT 89 V- 90 V- 9 upvcc 92 V 93 V 94 DGND 95 GND 96 GND 97 CH 98 CH- 99 OVH 28 OPIN- 40 OPIN 4 OPOUT 42 OHMC ES5998

3 Pin Description Pin No Symbol Type Description BUFH O High-speed buffer output pin. Connect to integral resistor. 2 CZH O High-speed auto-zero capacitor connection. 3 BUFOUT O Filter capacitor connection for CDC RMS mode. 4 CL IO Positive connection for reference capacitor of high-resolution /D. 5 CL- IO Negative connection for reference capacitor of high- resolution /D. 6 CIL O High-resolution integrator output. Connect to integral capacitor. 7 CZL O High-resolution auto-zero capacitor connection. 8 BUFL O High-resolution Buffer output pin. Connect to integral resistor 9 RZ O Buffer output pin in Z and ZI phase. 0 OHMC3 O Filter capacitor connection for resistance mode. OHMC2 O Filter capacitor connection for resistance mode. 2 OHMC O Filter capacitor connection for resistance mode. 3 VRH O Output of band-gap voltage reference. Typically.23V 4 V I De-integrating voltage positive input. The input should be higher than V-. 5 V- I De-integrating voltage negative input. The input should be lower than V. 6 EXTSRC I External source input available for Res/Diode/DP mode 7 IRVH O High voltage measurement range for insulation R mode 8 IRVH0 O High voltage measurement range0 for insulation R mode 9 OR O Reference resistor connection for Ω range 20 VR5 O Voltage measurement 0000 attenuator(000.0v) 2 VR4 O Voltage measurement 000 attenuator(600.00v) 22 VR3 O Voltage measurement 00 attenuator(60.000v) 23 VR2 O Voltage measurement 0 attenuator(6.0000v) 24 OVSG O Sense low voltage for resistance/voltage measurement 25 VR I Measurement Input. Connect to a precise 0MΩ resistor. 26 OVX I Sense input for resistance/capacitance measurement 27 OVH O Output connection for resistance measurement 28 OVH O Output connection for resistance measurement (optional) 29 IRR5 I Test mode used (optional) 30 IRR4 I Current shunt resistor4 connection for insulation R mode 3 IRR3 I Current shunt resistor3 connection for insulation R mode 32 IRR2 I Current shunt resistor2 connection for insulation R mode 33 IRR I Current shunt resistor connection for insulation R mode 34 IRVG I Voltage measurement terminal low-side of shunt resistor 35 IRVL I Voltage measurement terminal high-side of shunt resistor 36 SGND G Signal Ground. 37 IVSH I Current measurement input for μ, m and modes. 38 IVSL I Current measurement input for μ, m. 39 DP I Measurement input in DP mode. 40 OPIN- I Independent operational amplifier negative input 4 OPIN I Independent operational amplifier positive input 42 OPOUT O Independent operational amplifier output 43 CVL O DC signal low input in CV/C mode. Connect to negative output of external C to DC converter. 44 CVH O DC signal high input in CV/C mode. Connect to positive output of external C to DC converter. 45 DI I Negative input of internal C-to-DC OPMP. 46 DO O Output of internal C-to-DC OPMP. 47 TEST5 O Buffer output of OVSG 48 C- IO Negative auto-zero capacitor connection for capacitor measurement ver

4 49 C IO Positive auto-zero capacitor connection for capacitor measurement 50 OHMC4 O Filter capacitor connection for resistance mode. 5 - Not connected 52 - Not connected 53 - Not connected 54 - Not connected 55 R9K O Connect to a precise 9KΩ resister for capacitor measurement. 56 RK O Connect to a precise KΩ resister for capacitor measurement. 57 LPC O Capacitor C connection for internal low-pass filter 58 LPC2 O Capacitor C2 connection for internal low-pass filter 59 LPC3 O Capacitor C3 connection for internal low-pass filter 60 LPFOUT O Capacitor C connection for internal low-pass filter 6 PMIN O Minimum peak hold output 62 PMX O Maximum peak hold output. 63 CPKIN I Bypass capacitor for peak mode 64 STBEEP O Fast low-impedance sensed output for CONT./Diode mode Build-in a internal comparator for OVX pin. 65 FREQ I Frequency counter input, offset V-/2 internally by the chip Not connected 78 OSC2 O Crystal oscillator output connection 79 OSC I Crystal oscillator input connection 80 CS I Set to high to enable ES5998. Set to low to enter sleep mode 8 IO_CTRL I MPU I/O level LOW setting. Connect to DGND or V-. 82 BZOUT I Buzzer frequency output. Normal low state Not connected 84 DT_NEW O New DC data ready 85 SCLK I Serial clock input 86 SDT IO Serial data input/output 87 C O Positive capacitor connection for on-chip DC-DC converter. 88 C- O Negative capacitor connection for on-chip DC-DC converter. 89 LBT I Low battery configuration input. 90 V- P Negative supply voltage. 9 V- P Negative supply voltage. 92 upvcc P MCU I/O power level connection. 93 V O Output of on-chip DC-DC converter. 94 V O Output of on-chip DC-DC converter. 95 DGND G Digital ground. 96 GND G nalog ground. 97 GND G nalog ground. 98 CH IO Positive connection for reference capacitor of high-speed /D. 99 CH- IO Negative connection for reference capacitor of high-speed /D. 00 CIH O High-speed integrator output. Connect to integral capacitor. ver

5 bsolute Maximum Ratings Characteristic Rating Supply Voltage (V- to GND) -4V nalog Input Voltage & EXTSRC pin V to V 0.6 V V (GND/DGND0.5V) GND/DGND GND/DGND (V- -0.5V) Digital Input (IO_CTRL=V-) V to upvcc0.6 Power Dissipation. Flat Package 500mW Operating Temperature -20 to 70 Storage Temperature -55 to 25 Electrical Characteristics T=25, V- = -3.0V Parameter Symbol Test Condition Min. Typ. Max Units Power supply V V Operating supply current I DD Normal operation m In DCV mode I SS In sleep mode 3 µ SDC 2 Voltage roll-over error 0MΩ input resistor ±0.0 %F.S FDC 3 Voltage roll-over error 0MΩ input resistor ±0.5 %F.S SDC 2 Best case straight voltage nonlinearity NLV line ±0.0 %F.S FDC 3 Best case straight voltage nonlinearity NLV2 line ±.0 %F.S Voltage full scale range of SDC 2 V-V- = 200mV mv Voltage full scale range of FDC 3 V-V- = 200mV 600 mv Input Leakage for VR input -0 0 p Zero input reading 0MΩ input resistor Count Band-gap reference voltage 00KΩ resistor V RH between VRH and GND V Open circuit voltage for 600Ω range measurement V- V Open circuit voltage for other Ω V RH V measurement Open circuit voltage for 60.00nS range measurement Internal pull-high to 0V current Between V- pin and CS V.2 µ C frequency response at 6.000V ±% range ±5% HZ OP unity gain bandwidth GB C L =0pF 200 khz OP slew rate at unity gain SR R L =0MΩ 3.5 V/us OP input offset voltage V IO 0. mv OP input bias current I B 0 p OP input common mode voltage range V ICR 2 V ver

6 3dB frequency for LPF 4 active Multi-level low battery detector ES5998(60000counts) 3dB=Full (DP) 00 khz f 3dB 3dB=0k (DP) 0 khz 3dB=k (DP) khz V t 2.5 V V t2 LBT vs. V V V t3.83 V Peak-hold mode pulse width CIN =40 ~ 400Hz us STBEEP comparator in Diode mode OVX to SGND 9 mv STBEEP comparator in Cont. mode OVX to SGND -7 mv HCF detection voltage VR2-VR5 00 mv Frequency input sensitivity (FREQ) Fin Square wave with Duty cycle 40-60% 500 mvp Frequency input sensitivity (FREQ) Fin Sine wave 400 mvrms Reference voltage temperature coefficient TC RF 00KΩ resister Between VRH -20 <T<70 Capacitance measurement ccuracy 5 6nF 60mF Note:. Full Scale (60000 counts for SDC and 600 counts for FDC) 2. SDC = High resolution DC (slow speed) 3. FDC = High speed DC (lower resolution) 4. ES5998 built-in 3 rd order low pass filter available for C mode 5. Gain calibration is necessary for higher accuracy 6. vailable for DP input terminal. 50 ppm/ %F.S counts ver

7 C electrical characteristics Parameter Symbol Min. Typ. Max. Unit SCLK clock frequency f SCLK khz SCLK clock time L t LOW SLCK clock time H t HIGH us SDT output delay time t SDT output hold time t DH ns Start condition hold time t HD.ST Start condition setup time t SU.ST us Data input setup time t SU.DT Data input hold time t HD.DT ns Stop condition setup time t SU.STO SCLK/SDT rising time t R SCLK/SDT falling time t F us Bus release time t BUF MPU I/O timing diagram SCLK SDT IN SDT OUT ver

8 Function Description. MPU serial I/O function overview. Introduction ES5998 configures a 3-wire serial I/O interface to external microprocessor unit (MPU). The SDT pin is bi-directional and SCLK & DT_NEW are unilateral. The SDT pin is configured by open-drain circuit design. The DT_NEW is used to check the data buffer of DC ready or not. When the DC conversion cycle is finished, the DT_NEW pin will be pulled high until MPU send a valid read command to ES5998. fter the first ID byte is confirmed, the DT_NEW will be driven to low until the next DC conversion finished again. The data communication protocol is shown below. The write protocol is configured by an ID byte with four command bytes. The read protocol is configured by an ID byte with ten data bytes. Write command: ID byte, Write control byte, Write control byte2, Write control byte3, Write control byte4 STRT BIT B U C Z 0 K C K C K C K C K WRITE STOP BIT Read command: ID byte, Read data byte, Read data byte2 ~ Read data byte9, Read data byte0 STRT BIT B U Z C K RED C C C K K K C K N K STOP BIT DT_NEW DC data ready ID code confirmed Next DC data ready SDT ID code Read command SCLK Start bit Stop bit ver

9 The ID byte of ES5998 is header of 000 followed by a buzzer on/off control bit and R/W bit. The start/stop bit definition is shown on the diagram below..2 Read/Write command description The write command includes one ID byte with four command bytes. If the valid write ID code is received by ES5998 at any time, the write command operation will be enabled. The next table shows the content of write command. Byte Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit Bit0 ID BUZ R/W=0 W SHBP/DCSEL F3 F2 F F0 Q2 Q Q0 W2 B0 B B2 0 0 FQ2 FQ FQ0 W3 C BUFCL BUF_CDC EXT FD LPF LPF0 RP W4 PEK PCL IRQ IRV IRR OP0 OP EXT_DP uxiliary low-resistance detection control bit for Continuity and Diode modes: SHBP CDC mode selection control bit for CDC mode: DCSEL Measurement function control bit: F3/F2/F/F0 Range control bit for V//R/C modes: Q2/Q/Q0 Range control bit for Freq mode: FQ2/FQ/FQ0 Buzzer frequency selection: B2/B/B0 Buzzer driver ON/OFF control bit: BUZ C mode control enable bit: C PEK/Calibration mode enable bit: PEK/PCL 3dB BW for low-pass-filter selection: LPF/LPF0 External source for Diode mode control bit: EXT OP configuration control bit: OP/OP0 Frequency mode input resistance control bit or conductance mode control bit or output resistance control bit for CDC mode: RP Buffer control bits for CDC mode: BUFCL/BUF_CDC DP mode control bit: EXT_DP Insulation mode control bit: IRQ/IRV/IRR Fduty mode at 60kHz range auxiliary control bit: FD ver

10 The read command includes one ID byte with ten data bytes. When DT_NEW is ready, MPU could send the read data command to get the result of DC conversion (D0/D/D2/D3) 2 or status flag from ES5998. The next table shows the content of read command. Byte Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit Bit0 ID BUZ R/W= R SIGN BSIGN PMX PMIN BTS0 BTS ST0 LRM R2 HF LF LDUTY ST F_FIN D0:0 D0: D0:2 R3 D0:3 D0:4 D0:5 D0:6 D0:7 D0:8 D0:9 D0:0 R4 D0: D0:2 D0:3 D0:4 D0:5 D0:6 D0:7 D0:8 R5 D:0 D: D:2 D:3 D:4 D:5 D:6 D:7 R6 D:8 D:9 D2:0 D2: D2:2 D2:3 D2:4 D2:5 R7 D2:6 D2:7 D2:8 D2:9 D2:0 D2: D2:2 D2:3 R8 D2:4 D2:5 D2:6 D2:7 D2:8 D3:0 D3: D3:2 R9 D3:3 D3:4 D3:5 D3:6 D3:7 D3:8 D3:9 D3:0 R0 D3: D3:2 D3:3 D3:4 D3:5 D3:6 D3:7 D3:8 Note: DT_NEW will be active with D data updated when one fast DC (FDC) conversion finished. If MCU access slow DC output only, ten FDC conversion cycle delay is necessary. DT_NEW for frequency or capacitance mode will be active when D0 or D3 data ready. 2 Note: D0/D/D2/D3 all are binary code format. D0 is SDC output and D is FDC output. The maximum data is counts for SDC and 604 counts for FDC. The maximum counts for PEK mode is 03000, so D0 bit 7-8 could be ignored.. The DC data output for measurement mode: F3/F2/F/F0 F3 F2 F F0 Measurement mode Read data bytes V mode D0(0:8), D(0:9) CV Hz(%) mode D0(0:8), D(0:9), D3(0:8) mode D0(0:8), D(0:9) 0 0 C Hz(%) mode D0(0:8), D(0:9), D2(0:8), D3(0:8) Resistance mode D0(0:8), D(0:9) 0 0 Continuity mode D0(0:8), D(0:9) 0 0 Diode mode D0(0:8), D(0:9) 0 F duty mode D0(0:8), D2(0:8), D2(0:8), D3(0:8) Capacitance Mode D0(0:8) 0 0 DP mode D0(0:8), D(0:9) 0 0 DP Hz(%) mode D0(0:8), D(0:9), D2(0:8), D3(0:8) Insulation mode D0(0:8) ver

11 Buzzer frequency selection: B2/B/B0 B2 B B0 Buzzer frequency kHz kHz kHz kHz kHz kHz kHz 4.00kHz Set B2-B0 properly to get the target frequency. Use BUZ control bit to enable/disable the BUZOUT (pin82) driver output. If MPU control BUZ only, it is available to set ID byte with ending of stop bit. STRT BIT R C /W K STOP BIT Buzzer OFF STRT BIT R /W STOP BIT Buzzer ON ver. 2.6

12 Status flags for measurement mode: = function available Measurement mode SIGN BSIGN PMX PMIN BTS0 BTS LRM V mode CV Hz mode mode C Hz mode Res. mode Cont. mode Diode mode F duty mode Cap. Mode DP mode DP Hz mode Insulation mode Measurement mode HF LF LDUTY ST0 ST F_FIN V mode V Hz mode mode Hz mode Res. mode Cont. mode Diode mode F duty mode Cap. Mode DP mode DP Hz mode Insulation mode Description of status flags: SIGN: Sign bit of SDC output (- * D0 if SIGN=) BSIGN: Sign bit of FDC output (- * D if BSIGN=) PMX: Indicates D0 output is the voltage of the peak maximum capacitor (pin62) PMIN: Indicates D0 output is the voltage of the peak minimum capacitor (pin6) BTS0/BTS: Multi-level battery voltage indication LRM: Large capacitor indication/high crest factor signal detection in CV mode HF: Higher frequency indication for Hz mode LF: Lower frequency indication for Hz mode LDUTY: Low duty indication for Hz duty mode ST0/ST: divider indication for Hz mode ST0: Status flag for capacitor discharging mode ST: Status flag for Insulation R mode/resistance mode F_FIN: Measurement cycle finished for Hz mode ver

13 .3 Power & I/O level selection The ES5998 provide a flexible I/O level setting for different MPU system configuration. The up_vcc should be connected to the same potential of external Vcc of MCU. The up_vcc is allowed to be set between DGND ~ V. The IO_CTRL pin selects the Vss level of MCU. If IO_CTRL is set to DGND, the Vss level of MCU is the same as DGND. If IO_CTRL is set to V-, the Vss level of MCU is the same as V-. ver

14 2. Operating Modes 2.. Voltage Measurement MPU send write command to select the voltage measurement function. The Hz mode measurement is available to be enabled with the CV function (set C bit to ) simultaneously. The measured signal is applied to VR terminal (pin25) through 0MΩ. See the next table of function command: F3 F2 F F0 C Measurement mode Read data bytes DCV mode D0(0:8), D(0:9) CV mode D0(0:8), D(0:9) CV Hz(%) mode D0(0:8), D(0:9), D2(0:8), D3(0:8) Note: D0/D/D3 all are binary format. SIGN/BSIGN are the sign bit of D0/D, respectively. Note2: See PEK mode (section 2.0) also. Range control for voltage mode (CV/DCV) Q2 Q Q0 Full Scale Range Divider Ratio Resister Connection mV VR (0MΩ) V /0 VR2 (.MΩ) V /00 VR3 (0kΩ) V /000 VR4 (0.0kΩ) V /0000 VR5 (kω) Frequency range control for CVHz(%) mode FQ2 FQ FQ0 Full Scale Range Hz Hz kHz kHz Duty Cycle 20% ~ 80% Note: See frequency mode (section 2.9) also LRM bit at voltage mode is used for high crest factor (HCF) signal detection. If MPU check the LRM status flag active when data and range are stable, it should consider the making the existing range up to avoid the signal clamping saturation caused by HCF signal. There is higher peak voltage with lower RMS value for HCF signal. So if the range is up according to the LRM bit, MCU should set the lower under-limit counts temporarily to avoid the ranging unstable for this case. ver

15 2.2 Current measurement MPU send write command to select the current measurement function. The Hz mode measurement is available to be enabled with the C function (set C bit to ) simultaneously. The measured signal is applied to IVSL/IVSH terminals (pin37-38). See the next table of function command: F3 F2 F F0 C Measurement mode Read data bytes DC mode D0(0:8), D(0:9) C mode D0(0:8), D(0:9) 0 0 C Hz(%) mode D0(0:8), D(0:9), D2(0:8), D3(0:8) Note: D0/D/D3 all are binary format. SIGN/BSIGN are the sign bit of D0/D, respectively. Note2: See PEK mode (section 2.0) also. Range control for current mode (C/DC) Q2 Q Q0 Full Scale Range Input terminal mV 60000counts IVSL mV 60000counts IVSH Current measurement mode configuration examples: (max. voltage drop 300mV) u / m FUSE / u / m K K V - V TL K IVSL V - V COM 5 V - FUSE 6 / 20 0.uF 0.uF 00K Zero Offset.5K 00K IVSH m u m m u u 00K 00K GND SGND IVSH IVSL (max voltage drop = ~ V) ver

16 Frequency range control for CHz(%) mode FQ2 FQ FQ0 Full Scale Range Hz Hz kHz kHz Duty Cycle 20% ~ 80% Note: See frequency mode (section 2.9) also. ES5998(60000counts) 2.3 Low pass filter (LPF) mode for C/CV mode 3 rd order low pass filter with is built in ES5998. The 3dB bandwidth of the low pass filter could be selectable by MPU. The LPF mode is active when the LPF control bit is set to be active. When PEK mode is active, the LPF mode will be disabled temporarily until the PEK mode is cancelled. The LPF mode is allowed to be enabled in F duty mode to reject high-frequency noise for sine wave input, but the 3dB will be fixed at 0kHz only. LPF LPF0 Low pass filter effect 0 0 Disable 0 3dB = khz 0 3dB = 0kHz 3dB > 00kHz 2.4 CDC mode measurement Set control bit BUF_CDC= to enter CDC RMS measurement mode. The additional DC low-pass filter buffer will be enabled. The DC phase output of CDC mode will be sent to DC when DCSEL=. The C phase output of CDC mode will be sent to DC when DCSEL=0. The zero offset of DC low pass filter buffer should be calibrated by setting BUFCL=. The CDC RMS mode is supported as follow: F3 F2 F F0 C BUF_CDC Measurement mode Read data bytes DCVCV mode D0(0:8), D(0:9) DCC mode D0(0:8), D(0:9) 0 0 DP DCC mode D0(0:8) ver

17 The auto range scheme for CDC RMS mode is recommended as below: Note: When data is not overflow (larger than counts), always keep to set RP=0. Note2: Set BUF_CL = to enter CL mode to read D0_offset & D_offset Note3: If Range is increasing, set RP= to reduce settling time for BUFOUT (D0_dc) when range is modified. If RP=, wait 20ms then set RP=0 again. The D0_dc & D0_ac is the original data from SDC of ES5998. The D_dc & D_ac is the original data from FDC of ES5998. D0x & Dx is real dc value deducted by dc buffer offset. The final CDC RMS result is square root of sum of D0x 2 and D0_ac 2. ver

18 2.5 Resistance/Conductance Measurement ES5998(60000counts) MPU send write command to select the resistance measurement function. When RP=, the command to select the conductance mode. F3 F2 F F0 Measurement mode Read data bytes Resistance mode D0(0:8), D(0:9) Note: D0/D both are binary format. SIGN/BSIGN bits are ignored. When RP=, the D data should be ignored. Range control for resistance mode (RP=0) Q2 Q Q0 Full Scale Range Relative Resistor Equivalent value Ω OR 00Ω KΩ VR5 KΩ KΩ VR4 VR 0KΩ KΩ VR3 VR 00KΩ MΩ VR2 VR MΩ MΩ VR 0MΩ Note: Change OR resistor to 200Ω when MCU set FQ2/FQ/FQ0 = [,,] to provide more stability for Ω range if necessary. Set RP= when range control is 0MΩ range, the conductance mode is available. The status ST bit is used for converted data indication of reference voltage or input voltage. Q2 Q Q0 Full Scale Range Relative Resistor Equivalent value nS VR 0MΩ The maximum displayed count is 6000 and the resolution should be 0.0nS. The MCU should check the status bit ST and D0 simultaneously. When ST= the D0 data should be V D. If ST=0, then the D0 data should be V D2. The DUT conductance value could be calculated by simple formula. ver

19 2.6 Capacitance Measurement MPU send write command to select the capacitance measurement function. F3 F2 F F0 Measurement mode Read data bytes Capacitance mode D0(0:8) Note: D0 is binary format. SIGN bit is ignored. Range control for capacitance mode Q2 Q Q0 Full Scale Range Relative Resistor Measurement Period nF* sec nF* OVX pin VR 0.5 sec nF* -.25 sec uF* R9K / RK 0.4 sec max uF* R9K / RK 0.5 sec max uF* R9K / RK.0 sec max mF* R9K / RK.35 sec max mF* R9K / RK 6.75 sec max. The displayed counts in ES5998 capacitance mode is recommended to be divided by 0. (6000 counts displayed is recommended) LRM bit at capacitance mode is used for increasing the ranging speed. If MPU check the LRM= at lower range, it could set the next range to 6.000uF directly and the DC output should be ignored. ST0 status bit is used for detection of DUT capacitor voltage. If ST0=, the internal capacitor discharging mode is active and the capacitance measurement is inhibited. It is recommended to discharge the DUT capacitor externally. 2.7 Continuity Check measurement MPU send write command to select the continuity measurement function. F3 F2 F F0 Measurement mode Read data bytes 0 0 Continuity mode D0(0:8), D(0:9) Note: D0/D both are binary format. SIGN/BSIGN bits both are ignored. Continuity mode shares the same configuration with Ω resistance measurement circuit and support the low-resistance detection. If the STBEEP output (pin64) is low, it means the low-resistance status is detected (It means the OVX terminal voltage less than -7mV). It could be faster than the FDC result, so MPU could monitor the STBEEP output and FDC (D) data output make the high speed detection for short circuit detection. Set SHBP= to enable the built-in buzzer driving automatically when STBEEP is active. ver

20 2.8 Diode Measurement MPU send write command to select the diode measurement function. F3 F2 F F0 Measurement mode Read data bytes 0 0 Diode mode D0(0:8), D(0:9) Note: D0/D both are binary format. SIGN/BSIGN are the sign bit of D0/D, respectively. Diode measurement mode shares the same configuration with V voltage measurement circuit and support the low-resistance detection. If the STBEEP output (pin64) is low, it means the low-resistance status is detected (It means the OVX terminal voltage less than 9mV). It could be faster than the FDC result, so MPU could monitor the STBEEP output and FDC (D) data output make the high speed detection for short circuit detection. Set SHBP= to enable the built-in buzzer driving automatically when STBEEP is active. The default source voltage at diode mode is the same as V potential. MPU could set the control bit EXT= to change the source voltage to external source. The external voltage source (positive or negative) input applied from EXTSRC (pin6). The available external source range should be from V to V-. ver

21 2.9 Frequency/duty cycle mode measurement The default typical input impedance of frequency with duty cycle mode is MΩ. The MPU could set control bit RP= to change the input impedance down to 00kΩ. MPU send write command to select the frequency/duty cycle measurement function. F3 F2 F F0 Measurement mode Read data bytes 0 Hz Duty mode D0(0:8), D2(0:8), D3(0:8) Note: D0/D2/D3 all are binary format. SIGN bit is ignored. Note2: Set LPF = to enable the smooth function for sine wave input automatically Range control for frequency mode FQ2 FQ FQ0 Full Scale Conversion period Hz 700ms (fixed) Hz 700ms (fixed) KHz 700ms (fixed) KHz 700ms (fixed) KHz 700ms (fixed) MHz 700ms (fixed) MHz 700ms (fixed) vailable minimum frequency input F MIN = 4.000Hz Frequency & duty cycle mode computed by D0/D2/D3 (if F_FIN=) Flag ST0=0 ST0= Range* ST= ST= Hz FREQ= /D3 FREQ= /D3 FREQ= /D Hz FREQ= /D3 FREQ= /D3 FREQ= /D3** KHz FREQ= /D3 FREQ= /D3 FREQ= /D3*** KHz FREQ= /D3 FREQ= /D3 FREQ= /D KHz MHz MHz FREQ = D0- *Note: The Hz measurement of CHz mode is recommended to support 6000 counts displayed **Note: If D3 < 40000, simple arithmetic mean is necessary to get the 0.0Hz resolution ***Note: If D3 < 50000, simple arithmetic mean is necessary to get the KHz resolution Note: Set FD= to change the frequency calculation at 60kHz range to FREQ = D0. ver

22 Status Flag LDUTY= LDUTY=0 Duty cycle (<60kHz) 0000-D2*0000/D3 D2*0000/D3 The status flag F_FIN indicate the frequency input signal available (> F MIN ) or not. If the computed result less than F MIN, the frequency/duty cycle readings should be set to zero. The status flags HF & LF are used for fast judgment of proper range. If frequency input is larger than 7 khz, HF will be active. If frequency input is floating or frequency detected too low, LF will be active. uto range consideration for MPU by using Status Flags of frequency mode Flag F_FIN=0 F_FIN= F_FIN= Range LF=0 LF=* HF=LF=0 HF=** Hz Hz KHz KHz KHz MHz MHz Data and Range is not necessary to be updated Hz/Duty=0 Set range to Hz range Change range depends on data computed Set range to kHz range Change range depends on data computed *Note: 60Hz range implies the frequency is not available to be measured. The Hz/Duty readings should be set to zero. **Note: When CVHz/CHz/DPHz mode is selected, the HF status should be ignored. Change range depends on data calculation result. Duty cycle mode range (Input sensitivity > duty cycle = 5.0% & 95.0%) Freq. range Duty range* Hz Hz 5.0% % KHz 0.0 % % **60.000KHz 20.0% 80.0% *Note: Duty range for CHz(%) is 20% ~ 80%. **Note: Set FD= to improve the duty cycle resolution at 60kHz range. ver

23 2.0 DP mode MPU send write command to select the DP mode measurement function. The Hz mode measurement is available to be enabled with the DP C function (set C bit to ) simultaneously. The measured signal is applied to DP terminal (pin39). The signal full scale is 600mV for DC mode and 600mVrms for C mode. See the next table of function command: F3 F2 F F0 C Measurement mode Read data bytes DP DC mode D0(0:8), D(0:9) 0 0 DP C mode D0(0:8), D(0:9) 0 0 DP Hz(%) mode D0(0:8), D(0:9), D2(0:8), D3(0:8) Note: D0/D/D3 all are binary format. SIGN/BSIGN are the sign bit of D0/D, respectively. Note2: See PEK mode (section 2.0) also. Frequency range control for DPHz(%) mode FQ2 FQ FQ0 Full Scale Range Hz Hz kHz kHz Duty Cycle 20% ~ 80% Note: See frequency mode (section 2.9) also If MPU set the control bit EXT_DP=, the voltage on EXTSRC pin could be switched to DP terminal internally. It is helpful for a voltage pulled application of DP mode. External source pull high or low EXT_DP DC IN DP_IN SGND DC IN- ver

24 2. Peak-hold measurement mode ES5998 provides a peak hold function to capture the real peak value for voltage or current measurement mode. In a case of a V sine wave input voltage, the peak hold function gets a maximum peak value of.44v and minimum peak value of.44v ideally. Set the control bit PEK= to force the ES5998 entering PEK measurement mode. Peak Hold function is divided into two parts of peak maximum and peak minimum conversion. High resolution SDC performs peak maximum and peak minimum conversion in turn, not at the same time. The status flag PMX or PMIN shows which type the peak value is. If PMX=(PMIN=), the SDC output D0 is the conversion data on PMX (PMIN) terminals (pin 6/62). The MPU should make the comparison procedure to get the maximum value of PMX data and minimum value of PMIN data. The max counts for D0 is Peak calibration mode t PEK-Hold measurement mode, the offset voltage of internal operation amplifier will cause an error. To obtain a more accurate value, the offset error must be canceled. ES5998 provides the peak calibration feature to remove the influence on accuracy by internal offset voltage. Set the control bit PCL= to enter peak calibration mode. When PCL mode is active, the SDC of ES5998 will output the calibration value of peak maximum and minimum conversion in turn. The offset values should be memorized respectively and deducted from the data of PMX/PMIN at the normal peak measurement mode. Set PCL= or PEK= Status indication PMX=, PMIN=0 PMX=0, PMIN= DC data V PMX.C V PMIN.C V PMX.C and V PMIN.C are not the real-time value of peak-hold voltage. They are the voltage stored on terminal capacitor (pin6-62). Because the capacitor will be self-discharging, so MCU need to compare the V PMX.C & V PMIN.C respectively and memorize the maximum and minimum peak values in turn. ver

25 2.2 Insulation resistance measurement mode ES5998(60000counts) The ES5998 is built-in analog switches network to support the insulation resistance measurement mode. By implementation of external high voltage source, the insulation resistance could be obtained from SDC output of ES5998 and calculated by microprocessor easily. The insulation mode is separated into two modes which are insulation V mode and insulation R mode which are described below. Insulation V mode configuration F3 F2 F F0 IRV C Measurement mode Read data bytes 0/ Insulation (DC/C) V mode D0(0:8) Note: D0 is binary format. SIGN is the sign bit D0. Insulation V mode HV OFF (Discharging mode) MCU control PTC 0MΩ V V DC VR2 VR3 VR4 VR5 MCU control V DUT = V - V B = k * V DC.MΩ 0KΩ 0.0KΩ KΩ V B Q IRVG ctive in insulation V mode Note: The on-resistance of internal analog switches could be omitted. ver

26 Before measure insulation resistance, it is necessary to measure V DUT. If V DUT is too high, the resistance measurement should be forbidden. The insulation V mode is implemented by the same configuration with Voltage mode. The k factor of diagram is depended on the voltage range. During insulation V mode, an external fast discharging path should be applied on the HV sourcing part to release the high voltage charge on the DUT if it is capacitive load. Range control for insulation V mode Q2 Q Q0 Full Scale Range V V V Note: 600mV 6V ranges are omitted. Insulation R mode configuration F3 F2 F F0 IRV IRR Measurement mode Read data bytes 0 Insulation R mode D0(0:8) Insulation R mode HV(25V ~ 000V) MCU control PTC V 0MΩ V D DC IRVH0 IRVH V = V D / R * (0MR ) MCU control I RX = V D2 / R B = V B / R B Rx I RX 5.6KΩ 56KΩ R X = (V -V B ) / I RX R V B 00kΩ V D2 DC Q Test mode 360kΩ R B 36kΩ 3.6kΩ 360Ω IRR5 IRR4 IRR3 IRR2 IRR MCU control Note: DC full scale is 600mV typically. ver

27 During insulation R mode is setting, the SDC of ES5998 will convert the DUT terminal voltage V (higher voltage side V D ) & V B (lower voltage side V D2 ) sequentially. Use ohm s law calculation {R X = (V -V B )/I RX } to get the target DUT insulation resistance easily. The microprocessor gets the DC data by checking status bit ST: Status indication ST= ST=0 DC data V D V D2 The proper range control (R / R B selection) depends on the HV source. The R selection is controlled by IRQ control bit. The R B is selected by Q2/Q/Q0 control bits. The next range table is an example of HV sourcing from 25V to 000V. R Set IRQ= (IRVH) Set IRQ=0 (IRVH0) R B HV=25V HV=50V HV=00V HV=250V HV=500V HV=000V 5.0kΩ ~ 30.0kΩ ~ 60.0kΩ ~ 0.50MΩ ~ 0.300MΩ ~ 0.600MΩ ~ IRR 50.0kΩ 300.0kΩ 600.0kΩ.500MΩ 3.000MΩ 6.000MΩ 0.50MΩ ~ 0.300MΩ ~ 0.600MΩ ~.50MΩ ~ 3.00MΩ ~ 6.00MΩ ~ IRR2.500MΩ 3.000MΩ 6.000MΩ 5.00MΩ 30.00MΩ 60.00MΩ.50MΩ ~ 3.00MΩ ~ 6.00MΩ ~ 5.0MΩ ~ 30.0MΩ ~ 60.0MΩ ~ IRR3 5.00MΩ 30.00MΩ 60.00MΩ 50.0MΩ 300.0MΩ 600.0MΩ 5.0MΩ ~ 30.0MΩ ~ 60.0MΩ ~ 0.50GΩ ~ 0.300GΩ ~ 0.600GΩ ~ IRR4 50.0MΩ 300.0MΩ 600.0MΩ.500GΩ 3.000GΩ 6.000GΩ Q2 Q Q0 R B range Best resolution* 0 0 IRR 0.kΩ 0 0 IRR2 kω 0 IRR3 0.0MΩ 0 0 IRR4 0.MΩ 0 Test mode (IRR5) N/ *Note: The best resolution depends on the external high voltage and SDC readings. 2.3 Sleep Set CS pin (pin 80) to logic low to make the ES5998 entering the sleep mode. The current consumption will be less than 3u typically. Set CS pin to logic high or kept floating, the ES5998 will return to normal operation. ver

28 2.4 Multi-level battery voltage indication The ES5998 is built-in a comparator for batter voltage indication. The voltage is applied to LBT pin (pin 89) vs. V- terminal. MPU could check the status bit BTS/BTS0 and monitor the LBT voltage status. Battery voltage BTS BST0 V LBT > V t V t2 < V LBT < V t 0 V t3 < V LBT < V t2 0 V LBT < V t3 0 0 Low battery configuration for 9V/.5V*4/.5V*3 battery Low battery test circuit (a) Low battery test circuit (b) 6V 9V B 360K LBT B 470K LBT TT 270K 0.u GND V- TT 80K 0.u GND V- 0V 0V Low battery test circuit (c) 4.5V B 360K LBT TT 470K 0.u GND V- 0V ver

29 2.5 Independent OPMP ES5998 is built-in an independent OPMP with low drift offset using for general purpose. MPU could control the OP/OP0 to change the OPMP configuration: OP OP0 OPMP configuration 0 0 Normal 0 OP disable 0 Unity gain buffer Zero calibration Note: If C=, it is recommended to set FD= simultaneously. ver

30 3. pplication Circuit 3. VG circuit D C B Date: 3-Jun-203 Sheet of File: F:\Protel file\k029\k029_spec.ddb Drawn By: 4 Demo Board schematic Ver : 9 Size Number Revision JP4 Insulation R- 2 Title ES5998 Schematic Circuit (VG) Q6 Q8 Q9 Q5 Q7 R6 2.2K PTC R25 K OVH R4 2.2K PTC R24 K OVH R7 80K OVX Close to IC C2 680pF R37 56K C3 22nF K CVL R26 N448 N448 C24 0.uF R36 56K C22 uf D D2 CVH VR2 50K DO SW SW_RC 9K JP3 R32 R33 5K uf C25 C26 uf R34 5K VIN Insulation R 2 2 R5 2.2K PTC Insulation High V CIH CH- CH GND GND DGND V V upvcc V- V- LBT C- C SDT SCLK DT_new BZOUT IO_CTRL CS OSC OSC2 OVX OVH OVH IRR5 IRR4 IRR3 IRR2 IRR IRVG IRVL SGND IVSH IVSL DP OPIN- OPIN OPOUT CVL CVH DI DO TEST5 C- C OHMC4 DI R35 0K JP2 VR3 0K C23 4.7uF TEST5 RK R9K 220pF R2 K C2 4.7uF C9 3.3nF /- 0% C5 00pF /- 0% Close to IC C27 C4 470pF /- 0% VR 200 C6 0nF C7 0nF C8 22pF FIN STBEEP R2 200 C20 2.2uF R3 2.2K PTC 2 C6 470nF R5 220K 8 R9 0 9 JP C0 220nF C3 00nF C9 47nF C7 220nF C 220nF Q Q2 Q3 Q4 C7 0uF Close to IC C uF 0 2 R 5.6K 3 V 4 V- 5 EXTSRC 6 R3 56K 7 R4 5.6K 8 R R9 K 20 R20 0.0K 2 R2 0K 22 R22.M 23 OVSG 24 R23 0M R K R K R K R R K R IVSH 00K R6 37 IVSL 00K R7 38 DP 00K R8 39 OPIN- 40 OPIN 4 OPout 42 CVL 43 CVH 44 DI 45 DO 46 TEST5 47 C8 470nF /- 0% BUFH CZH BUFOUT CL CL- CIL CZL BUFL RZ OHMC3 OHMC2 OHMC VRH V V- EXTSRC IRVH IRVH0 OR VR5 VR4 VR3 VR2 OVSG VR ES V FREQ STBEEP CPKIN PMX PMIN LPFOUT LPC3 LPC2 LPC RK R9K Close to IC C2 22nF C28 0.uF V ZR2 R 470K CS VSS V- or DGND C8 0.uF U R39 0 STBEEP C6 0uF V C 22nF C4 VCC LBT C5 SD SCL DT_new BUZOUT VSS CS DT_new MPU ZR 5.6V SCLK C29 5pF 0nF V V - 470nF Y 4MHz SDT VDD upvcc (DGND or 3V) Regulator DC 3.0V V - 47K Metallized Polypropylene Film Capacitor : C7 Metallized Polyester Capacitor : C, C3, C, C6, C7 Option VDD D C B ver

31 3.2 RMS circuit (ES636) D C B Date: 3-Jun-203 Sheet of File: F:\Protel file\k029\k029_spec.ddb Drawn By: 4 Demo Board schematic Ver : 9 Size Number Revision JP4 Insulation R- 2 Title ES5998 Schematic Circuit (TRMS) Q6 Q8 Q9 Q5 Q7 R6 2.2K PTC R25 K OVH R4 2.2K PTC R24 K OVH R7 80K OVX Close to IC C2 680pF K C24 0uF 0uF C3 22nF R26 VR4 500K 200 DI R33 C26 C27 2.2uF C22 uf VS - VS VR VS VS R34 0K VR2 50K ES636 Close to IC SW SW_RC 9K CVH JP3 R32 VIN Insulation R C25 22uF R35 200K 2 2 R5 2.2K PTC Insulation High V CIH CH- CH GND GND DGND V V upvcc V- V- LBT C- C SDT SCLK DT_new BZOUT IO_CTRL CS OSC OSC2 OVX OVH OVH IRR5 IRR4 IRR3 IRR2 IRR IRVG IRVL SGND IVSH IVSL DP OPIN- OPIN OPOUT CVL CVH DI DO TEST5 C- C OHMC4 VS Vin VS En - VS CV db COMMON BUF out RL BUF in Iout JP2 CV RMS C23 4.7uF U2 RK R9K - VS VS R2 K C2 4.7uF SW2 220pF C9 3.3nF /- 0% C5 00pF /- 0% Close to IC C29 C4 470pF /- 0% VR 200 C6 0nF C7 0nF C8 22pF FIN STBEEP R2 200 C20 2.2uF R3 2.2K PTC 2 C6 470nF R5 220K 8 R9 0 9 JP C0 220nF C3 00nF C9 47nF Close to IC C7 220nF C 220nF Q Q2 Q3 Q4 C7 0uF Close to IC C3 0.47uF 56K % % 0 2 R 5.6K 3 V 4 V- 5 EXTSRC 6 R3 7 R4 8 R8 5.6K 00 9 R9 K 20 R20 0.0K 2 R2 0K 22 R22.M 23 OVSG 24 R23 0M R K % R K % R K % R % R K R IVSH 00K R6 37 IVSL 00K R7 38 DP 00K R8 39 OPIN- 40 OPIN 4 OPout CVH 44 DI C8 470nF /- 0% BUFH CZH BUFOUT CL CL- CIL CZL BUFL RZ OHMC3 OHMC2 OHMC VRH V V- EXTSRC IRVH IRVH0 OR VR5 VR4 VR3 VR2 OVSG VR ES V FREQ STBEEP CPKIN PMX PMIN LPFOUT LPC3 LPC2 LPC RK R9K Close to IC C2 22nF C28 0.uF V ZR2 R 470K CS VSS V- or DGND C8 0.uF U? R37 0 C6 0uF C 22nF C4 0nF VCC LBT 88 C5 470nF SD 85 SCL 84 DT_new STBEEP V - BUZOUT VSS CS DT_new MPU ZR 5.6V SCLK C30 5pF V V - Y 4MHz SDT VDD upvcc (DGND or 3V) Regulator DC 3.0V V - 47K Metallized Polypropylene Film Capacitor : C7 Metallized Polyester Capacitor : C, C3, C, C6, C7 Option VDD D C B ver

32 4. Package Information 4. 00L LQFP Outline drawing 4.2 Dimension parameters ver