Nanoelectronic Circuit Design

Transcription

1 Nanoelectronic Circuit Design

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3 Niraj K. Jha l Editors Deming Chen Nanoelectronic Circuit Design

4 Editors Niraj K. Jha Department of Electrical Engineering Princeton University NJ, USA Deming Chen Department of Electrical and Computer Engineering University of Illinois at Urbana-Champaign IL, USA ISBN e-isbn DOI / Springer New York Dordrecht Heidelberg London # Springer Science+Business Media, LLC 2011 All rights reserved. This work may not be translated or copied in whole or in part without the written permission of the publisher (Springer Science+Business Media, LLC, 233 Spring Street, New York, NY 10013, USA), except for brief excerpts in connection with reviews or scholarly analysis. Use in connection with any form of information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed is forbidden. The use in this publication of trade names, trademarks, service marks, and similar terms, even if they are not identified as such, is not to be taken as an expression of opinion as to whether or not they are subject to proprietary rights. Printed on acid-free paper Springer is part of Springer ScienceþBusiness Media (

5 Preface After enjoying a three-decade ride as the top semiconductor technology for implementing integrated circuits (ICs), the era of single-gate complementary metal-oxide semiconductors (CMOS) is coming to an end. Waiting in the wings as replacements are various interesting new nanotechnologies. In the past decade, a contender for replacing bulk CMOS technology has been double-gate field-effect transistor technology, most manufacturable of which are FinFETs. There are also other contenders, such as nanowires, carbon nanotubes, graphene nanoribbons, resonant tunneling diodes, quantum cellular automata, etc. We may also soon see hybrid nano/cmos designs in which the memory has been implemented in a new technology, while the processing elements have been implemented in CMOS. Although these nanotechnologies have attracted significant attention over the last decade, the emphasis of interest, as expected, has been more on their physics, chemistry, and fabrication aspects. However, interesting new nanoelectronic circuit designs are beginning to emerge that herald an exciting new era of IC design. These designs deal with both logic as well as interconnect. Our aim in this book is to introduce readers to the emerging design paradigms in various nanotechnologies, and to bridge the existing gap between nanodevice research and nanosystems design. The book focuses on state-of-the-art research activities, yet, at the same time, covers the fundamental principles behind the nanotechnology developments. The ultimate goal is to expose the great potential of nanoelectronic technology and the unique challenges it poses along the deviceto-system spectrum. A rich set of references is included at the end of each chapter to give pointers to readers who want to dig deeper. In addition, some exercises are also included in each chapter to allow the use of the book for a first-year graduate-level course on nanoelectronic circuit design. The book is organized by grouping together chapters on each nanotechnology. Chapter 1 introduces various nanotechnologies. Chapters 2 and 3 deal with FinFET logic and memory design. Chapter 4 describes a nano/cmos dynamically reconfigurable architecture. Chapters 5 7 discuss nanowire-based ICs and architectures. Chapters 8 and 9 describe how reliable logic circuits and field-programmable gate v

6 vi Preface arrays can be built using nanotubes. Chapter 10 deals with circuit design based on graphene nanoribbon transistors. Chapter 11 compares copper, nanotube, graphene, and optics for implementing interconnects on chips. Chapters 12 and 13 discuss circuit design with resonant tunneling diodes and quantum cellular automata, respectively. The chapters are fairly independent of each other. Thus, any subset can be chosen for a one-semester course. Last, but not the least, Niraj would like to thank his father, Dr. Chintamani Jha, his wife, Shubha, and his son, Ravi, for their encouragement and understanding. Deming would like to thank his wife, Li, and his sons, Jeffrey and Austin, for their love and understanding. Niraj K. Jha Deming Chen

7 Contents 1 Introduction to Nanotechnology... 1 Deming Chen and Niraj K. Jha 2 FinFET Circuit Design Prateek Mishra, Anish Muttreja, and Niraj K. Jha 3 FinFET SRAM Design Rajiv Joshi, Keunwoo Kim, and Rouwaida Kanj 4 A Hybrid Nano/CMOS Dynamically Reconfigurable System Wei Zhang, Niraj K. Jha, and Li Shang 5 Reliable Circuits Design with Nanowire Arrays M. Haykel Ben Jamaa and Giovanni De Micheli 6 Leveraging Emerging Technology Through Architectural Exploration for the Routing Fabric of Future FPGAs Soumya Eachempati, Aman Gayasen, N. Vijaykrishnan, and Mary Jane Irwin 7 Nanoscale Application-Specific Integrated Circuits Csaba Andras Moritz, Pritish Narayanan, and Chi On Chui 8 Imperfection-Immune Carbon Nanotube VLSI Circuits Nishant Patil, Albert Lin, Jie Zhang, Hai Wei, H.-S. Philip Wong, and Subhasish Mitra 9 FPCNA: A Carbon Nanotube-Based Programmable Architecture Chen Dong, Scott Chilstedt, and Deming Chen vii

8 viii Contents 10 Graphene Transistors and Circuits Kartik Mohanram and Xuebei Yang 11 Study of Performances of Low-k Cu, CNTs, and Optical Interconnects Kyung-Hoae Koo and Krishna C. Saraswat 12 Circuit Design with Resonant Tunneling Diodes Pallav Gupta 13 Circuit Design with Quantum Cellular Automata Pallav Gupta Index

9 Contributors Csaba Andras Moritz Department of Electrical and Computer Engineering, University of Massachusetts, Amherst, MA, USA Deming Chen Department of Electrical and Computer Engineering, University of Illinois at Urbana Champaign, IL, USA Scott Chilstedt Department of Electrical Engineering, University of Illinois at Urbana Champaign, Urbana, IL, USA Chi On Chui Department of Electrical Engineering, The University of California, Los Angeles, CA, USA Giovanni De Micheli Institute of Electrical Engineering, EPFL, Lausanne, Switzerland Chen Dong Department of Electrical and Computer Engineering, University of Illinois, at Urbana Champaign, IL, USA Soumya Eachempati Department of Computer Science and Engineering, The Pennsylvania State University, University Park, PA, USA Aman Gayasen Department of Computer Science and Engineering, The Pennsylvania State University, University Park, PA, USA ix

10 x Contributors Pallav Gupta Core CAD Technologies, Intel Corporation, Folsom, CA 95630, USA M. Haykel Ben Jamaa Commissariat à l Energie Atomique, DRT-LETI-DACLE-LISAN, Grenoble Cedex, France Niraj K. Jha Department of Electrical Engineering, Princeton University, NJ, USA jha@princeton.edu Rajiv Joshi IBM, Thomas J. Watson Research Center, Yorktown Heights, NY, USA rvjoshi@us.ibm.com Rouwaida Kanj IBM Austin Research Laboratory, Austin, TX, USA Keunwoo Kim IBM, Thomas J. Watson Research Center, Yorktown Heights, NY, USA Kyung-Hoae Koo Albert Lin Prateek Mishra Department of Electrical Engineering, Princeton University, Princeton, NJ, USA Subhasish Mitra subh@stanford.edu Kartik Mohanram Electrical and Computer Engineering, Rice University, Houston, TX, USA kmram@rice.edu Anish Muttreja nvidia, Santa Clara, CA, USA Pritish Narayanan Department of Electrical and Computer Engineering, University of Massachusetts, Amherst, MA, USA Nishant Patil nppatil@stanford.edu

11 Contributors xi H. S. Philip Wong Krishna C. Saraswat Li Shang Department of Electrical, Computer, and Energy Engineering, University of Colorado, Boulder, CO, USA N. Vijaykrishnan Department of Computer Science and Engineering, The Pennsylvania State University, University Park, PA, USA Hai Wei Xuebei Yang Department of Electrical and Computer Engineering, Rice University, Houston, TX, USA Jie Zhang Wei Zhang School of Computer Engineering, Nanyang Technological University, Singapore

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