Faster than Nyquist Signaling

Transcription

1 Faster than Nyquist Signaling

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3 Deepak Dasalukunte Viktor Öwall Fredrik Rusek John B. Anderson Faster than Nyquist Signaling Algorithms to Silicon 123

4 Deepak Dasalukunte Lantiq Bangalore, India Fredrik Rusek Electrical and Information Technology Lund University Viktor Öwall Electrical and Information Technology Lund University John B. Anderson Electrical and Information Technology Lund University ISBN ISBN (ebook) DOI / Springer Cham Heidelberg New York Dordrecht London Library of Congress Control Number: Springer International Publishing Switzerland 2014 This work is subject to copyright. All rights are reserved by the Publisher, whether the whole or part of the material is concerned, specifically the rights of translation, reprinting, reuse of illustrations, recitation, broadcasting, reproduction on microfilms or in any other physical way, and transmission or information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed. Exempted from this legal reservation are brief excerpts in connection with reviews or scholarly analysis or material supplied specifically for the purpose of being entered and executed on a computer system, for exclusive use by the purchaser of the work. Duplication of this publication or parts thereof is permitted only under the provisions of the Copyright Law of the Publisher s location, in its current version, and permission for use must always be obtained from Springer. Permissions for use may be obtained through RightsLink at the Copyright Clearance Center. Violations are liable to prosecution under the respective Copyright Law. The use of general descriptive names, registered names, trademarks, service marks, etc. in this publication does not imply, even in the absence of a specific statement, that such names are exempt from the relevant protective laws and regulations and therefore free for general use. While the advice and information in this book are believed to be true and accurate at the date of publication, neither the authors nor the editors nor the publisher can accept any legal responsibility for any errors or omissions that may be made. The publisher makes no warranty, express or implied, with respect to the material contained herein. Printed on acid-free paper Springer is part of Springer Science+Business Media (

5 to dearest anu, my parents:::and a journey called life::: Deepak Dasalukunte

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7 Preface This is a book about a new chip. Actually, a first hardware implementation of a new digital transmission method, with all the uncertainties that apply. We expect that few readers actually design and construct chips, but chips play a dominant role in electronic and communication technology today, and we hope that this book will be of interest not only to designers but also to users and those interested in the new transmission method. The new method is called faster than Nyquist signaling, or simply FtN, a term coined by James Mazo of Bell Telephone Laboratories in the 1970s. Harry Nyquist was a brilliant communication engineer who was active in the first half of the twentieth century. Among his many contributions was discovery of a law, now called the Nyquist rate, which states how fast pulses with certain properties can be transmitted and still have a given bandwidth in Hertz. Pulses carry data bits in a transmission system. Mazo showed that pulses could be sent faster without damage to the bit error rate. Although some other properties had to be given up, the most important pulse property, the bandwidth, remained the same. These matters will be explained more fully in Chaps. 1 and 2. In the 1970s there was more confusion about these pulse properties than there is today, and it sounded faintly illegal to go faster than Nyquist. Mazo himself told one of us (JBA) that he thought the work was just a curiosity. But there is no conflict with Nyquist, and the work turned out to be much more fundamental than it appeared at first. The property given up is pulse orthogonality (see Chap. 1), and in return one can send more bits per second in the same bandwidth and at the same energy per bit. The price paid for this is more complex processing this is why the chip is needed. The need to reduce physical, radio bandwidth per bit transmitted is arguably the most crucial problem today in the wireless communication physical layer. It is the main motivation for this book. Another motivation is more scientific. The phenomenon that Mazo observed with just one type of pulse more bits per second in the same bandwidth and energy turns out to apply to a great many transmission methods. This was discovered by one of us (JBA) and coworkers during the 1980s. Faster than Nyquist signaling also addresses a fundamental problem in error-correction coding, which is a good vii

8 viii Preface method when a high density of bits are sent per Hertz and second. In the 2000s, two of us (FR and JBA) showed that faster than Nyquist signals can have a higher Shannon capacity. At that time all implementation of real FtN systems by us and others was by software algorithms. The time was ripe for hardware, and in 2007 the theorists and software mongers joined with two chip experts (DD and VÖ) to see what could be done in hardware. The outcome was a fascinating journey for all of us, which is depicted in these pages. The early stages were what is called algorithm-hardware codesign, finding out what could be given up to simplify the chip and what was the best practical first application. This theme runs through Chaps. 1, 2, 4, and 5. Then the chip was built and measured in 2011, in Chaps. 5 and 6. Chapter 3 on fading channels and Chap. 7 on IOTA pulses are added as side topics for those who are interested. One of us (DD) received a Ph.D. for the chip design, and this led to the invitation from Springer to place the book in their series of leading Ph.D. theses. The book, except for Chap. 7 and parts of Chap. 1, is based on that thesis. The book is thus the product of a long technical development that ended in the biggest challenge of all, development of a chip. It was perhaps not a journey for the faint-hearted, and we had our share of good luck. Be that as it may, it has been a rewarding journey for the four of us. We hope that it will be of interest to those who want to learn about FtN, but also those who are curious how new technology methods find implementation, how a chip is made, what are the risks along the way, and what cooperations are needed. We would like to express our thanks to Springer and to our New York editors, Jessica Lauffer and Charles Glaser. We are grateful to the Swedish Science Foundation (VR), to the Swedish Foundation for Strategic Research (SSF), and to the Swedish industrial development agency VINNOVA, who had the foresight to support this work over the last 8 years, both as separate grants and through the Lund University Center for High Speed Wireless Communication and the System on Silicon Center. The chip fabrication reported here took place at ST Electronics. Discussions with colleagues at EUTELSAT/Paris and Ericsson Company in Lund, Kista and Gothenburg were a great help in fixing ideas and priorities. Finally, we would like to acknowledge our many colleagues at the Electrical and Information Engineering Department, Lund University, and particularly Adnan Prlja and Shahid Mehmood, who made particular contributions to the project. Shahid joins us as a coauthor in Chap. 7. Bangalore, India April 2014 Deepak Dasalukunte Fredrik Rusek Viktor Öwall John B. Anderson

9 Contents 1 Introduction FTN Signaling Technical Introduction Prior Work and State-of-the-Art Hardware Implementation Algorithm-Hardware Tradeoffs Contribution Theory: FTN Signaling in AWGN and Fading Channels FTN Transmitter, Receiver: Hardware Architecture, Implementation, and Chip Measurements FTN Theory Transmission Scheme Choice of Orthogonal Basis Alternate Transmission Methods Method Method Decoding FTN Modulated Symbols Matched Filtering for FTN Symbol Reconstruction Inner Decoder Choice of Time Frequency Spacing in FTN Signaling System Setup Receiver Performance Finite Wordlength Considerations Fixing the Block Size for Interleaver/De-Interleaver Design Gains from the FTN System Summary FTN Signaling in Fading Channels System Model Receiver Processing in the Presence of Fading ix

10 x Contents Channel Coefficients at Orthogonal and FTN Subcarrier Positions Matched Filtering with Equalization LLR Calculation Results Adaptive FTN Signaling Maximizing Data Rate with FTN Signaling Results Summary FTN Transmitter: Hardware Architecture and Implementation Look-Up Table Based Architecture Operating at Suboptimal Points Implementation Register Based Implementation RAM Based Implementation Results FPGA Implementation ASIC Synthesis Summary FTN Receiver: Hardware Architecture and Implementation Matched Filter Architecture Inner Decoder Architecture Soft Output Calculation SIC Using Mapper-Matched Filter Cascade LLR Calculation Outer Decoder Controller for the FTN Decoder Implementation Results Area Speed and Throughput Power Consumption Hardware Overhead with FTN Signaling Architectural Optimizations to Reduce Area and Power Memory Optimization Intermediate Buffer Optimization Interference Canceled Symbol Buffer Optimization by Fixing Values of Noise Variance Post-optimization Results Power Consumption Memory Requirement and Chip Area RTL Verification Using MATLAB System Model Summary... 89

11 Contents xi 6 FTN Decoder: Implementation Results and Silicon Measurements Silicon Measurements Test Setup Operating the FTN Decoder Decoder Performance Power Supply and Frequency Benchmark Architectural Enhancements Utilizing the Configurable Iteration Count A Register-Based FTN Mapper Architecture Complexity Comparison Summary IOTA Pulse-Shaping Filters in FTN Multi-Carrier Systems Introduction IOTA Pulses in FTN Systems Functional Description of the Transmit/Receive IOTA Filter Hardware Architecture Hardware Mapped Architecture Time-Multiplexed Architectures Complexity Analysis Balancing IOTA Filter and IFFT Architectures A Unified Transmit/Receive Architecture Implementation and Results Resource Utilization Comparison Between the Architectures Utilizing Single-Port RAMs The IOTA Filter in the FTN System Summary Conclusion and Future Directions Conclusion Future Directions Theoretic/Algorithmic Extensions Architectural Extensions Extensions in Other Parts of the System References