Grand Challenges in Silicon Technology

Transcription

1 Grand Challenges in Silicon Technology Contents: Outcome of Consultation Exercise Page 2 Grand Challenges for Silicon Technology Roadmap Page 5 1

2 Outcome of Consultation Exercise Executive summary The GCs in Silicon Technology roadmap was produced as the main outcome of an EPSRC-funded network of researchers. A parallel activity was also undertaken in the area of microelectronic design. It aimed to develop a vision for silicon technology research and identify where the major research challenges lie in the field, thereby encouraging greater coherence, communication and collaboration across the research community. EPSRC carried out a formal consultation exercise via a call for feedback on its website. The GCs generated a lot of interest and overall support from both academic and industry researchers. Following the consultation, the authors of the document are in discussion with the National Microelectronics Institute (NMI) to determine how to take the GCs forward in partnership with industry. EPSRC is also considering signposting one or more of the GCs to encourage the research community to submit applications in the area, via responsive mode. Background The GCs in Silicon Technology roadmap document was produced as one of the main outputs from the EPSRC-funded network of researchers 'Silicon for the Nanotechnology era', a collaborative effort to which the following institutions contributed: Birmingham, Cambridge, Edinburgh, Glasgow, Imperial College, Liverpool, Manchester, Newcastle, Queen s Belfast, Sheffield, Southampton, Surrey and Warwick. The network ended in The GCs are divided into two sets; the first four grand challenges were identified specific areas of strength in the UK whilst GC5-8 have been selected as flagship projects aligned with EPSRC delivery plan themes: GC1 Novel devices and Processes Using Silicon Based Technologies GC2 Modelling and Simulation for Silicon Based Technologies GC3 Characterisation for Silicon Based Technologies GC4 New Materials for Silicon Based Technologies GC5 Smart Nano: nanoscience to nanoengineering GC6 Silicon for Life: towards next generation healthcare GC7 Eco-silicon: energy In order to consider the views of both academic and user research community on the content and the format of the GCs, a consultation exercise was launched in October 2007 and closed in January Over 500 academic and industry researchers, registered on the Research Councils Je-S system, and with relevant expertise, were contacted and asked to provide their views on the Grand Challenges document. A summary of the outputs of the consultation are presented below. 2

3 Outcomes of consultation (summary of) Over 100 replies were received (20% hit rate); 60% of which came from academic researchers and 40% from industry. The majority of replies were supportive. The roadmap received very strong endorsement for the UK industrial base, specifically from SMEs. There was however quite a significant proportion of less supportive feedback, principally centred on the lack of novelty / incremental nature of some the grand challenges proposed. All responses provided a significant source of constructive detailed comments to help improve on the current documents. The overlap with the Grand Challenges in Microelectronic Design document was highlighted numerous times in the consultation process. In order to summarise generic points made by all those consulted on the GCs document, an analysis of strengths, weakness, opportunities and threats (SWOT) was carried out and is presented in Table 1: Strengths Useful framework document Outlines a vision Logical analysis of strengths and opportunities for UK research Realistic (UK should play to its strengths) Comprehensive Significant industry support Opportunities Overlap with GCs in microelectronic design (joined-up approach needed) Silicon Photonics Spintronics Major Strategic Alliances (e.g. IMEC) G5-G8 Link to EU Weaknesses Not GCs but incremental / too conservative Absence of paths to solutions / endpoints Lacks focus Repeats what exists already in other (e.g. EU) silicon roadmaps Themes targeted at aware audience (not general public) Unclear vision Too targeted at EPSRC Exploitation / route to market is unclear for some of the GCs Threats Absence of UK industry International competition Limitations of CMOS technology Table 1 - SWOT analysis: outputs of consultation on GCs 3

4 Conclusion / Next steps The GCs documents generated a lot of interest from both academic and industry communities whom, on the whole, are supportive of the ideas presented in the roadmap. The two main conclusions are (1) the overlap design/device should be considered in key areas (e.g. health) and (2) the route to market remains an issue for some of the GCs, although the endorsement of the GCs by UK industry can be seen as a real strength. A number of actions are being taken forward following the consultation: The authors of the document are in discussion with the National Microelectronics Institute (NMI) to determine how to take the GCs forward in partnership with industry. EPSRC is considering the signposting of one or more of the GCs via responsive mode. This would aim to encourage the research community to submit high-quality applications directly in alignment with the GCs. Acknowledgements EPSRC wishes to thank again all the researchers who took the time to provide feedback in response to the consultation. 4

5 Grand Challenges for Silicon Technology Roadmap 1. Vision for UK Silicon Nanoelectronics Research: We believe that a creative and intelligent use of silicon will benefit our society in the areas of health, wealth creation, education, well-being and the environment. 2. The EPSRC Delivery Plan for the 2007 HM Government Comprehensive Spending Review includes: nanoscience to nanoengineering; towards next generation healthcare; energy; digital economy; towards better exploitation; essential platform to the knowledge economy; securing the future. 3. Silicon Futures is a network of UK universities undertaking research in silicon technology. The founding members are the universities of Birmingham, Cambridge (Engineering and Physics), Edinburgh, Glasgow, Imperial College, Liverpool, UMIST, Newcastle, Queen s Belfast, Sheffield, Southampton, Surrey and Warwick 4. A key objective identified at an early stage in the life of the network was to develop flagship projects which made use of the strengths of the community whilst at the same time were of major strategic value to the UK economy. The network was also encouraged by EPSRC to identify specific areas where future research might focus. The Grand Challenges set out to meet these objectives in alignment with the EPSRC Delivery Plan. 5. For the UK to play a world leading role in silicon based nanoelectronics research it must focus on unique capabilities and key strengths. These include materials, metrology, modelling and the integration of silicon with other technologies. It is not realistic to develop mainstream CMOS technology miniaturization (more Moore) in competition with the likes of Intel, ST Microelectronics or research centres such as IMEC, where high volumes of chips are produced. Instead, strategic partnerships with such organisations will be sought where this is appropriate and necessary. 6. The first 4 grand challenges (G1-G4) are specific technical areas of strength in the UK, while the last 3 (G5-G7) are flagship projects aligned to the CSR. 5

6 G1: Novel Devices and Processes Using Silicon Based Technologies Proof of concept research for novel devices and processes is needed in heterogeneous integration for systems-in-package, for the integration of nanoelectronics with nanotechnology and in advanced CMOS nodes. Strategic partnerships with global players will exploit the resulting IP and lead to inward investment for the UK and participation in world leading research. The grand challenges are imposed by nm scale resolution features, high speed electrical performance, 3D structures, manufacturing quality and a need to introduce new materials or extend properties through strain. G1.1: Advanced Si devices Innovations are needed to maintain Moore s law; new devices are needed for increased functionality of system-in-packages. New device concepts (e.g. switch, memory, sensor, 3D, interconnect) New physics (e.g. strain, temperature, low dimensions, variability) Extreme functionality (e.g. high power, high frequency, low power) New / extended functionality (e.g. photonic, sensing) G1.2: Device elements / processes Continual improvements in Si devices throw up new challenges in specific regions of devices (e.g. parasitics, channel mobility, reliability); bottom up versus top down fabrication. New MOS gate stacks Nanowires and nano-crystals Alternatives to metal interconnect Alternatives to patterning Combining top-down and bottom-up G1.3: Integration Issue: How to integrate biological, mechanical and electronic functions; how to mix technologies on a single Si platform. Integration of electronic devices on novel substrates New materials (functional, isolation, barriers, ) Material interfaces Packaging Interference between functional blocks G1.4: Technology / Design Issue: Future design solutions must take account of high leakage, variability, power dissipation; new device concepts require new design solutions. Design strategies for emerging devices Design/technology co-design Design for More than Moore Compact models for nanoelectronic devices 6

7 G2: Modelling and Simulation for Silicon Based Technologies Future generations of devices will soon have dimensions so small that their behaviour is governed by quantum effects or they will be grown from the bottom up and be founded on atomic or molecular structures. In either case, there will be a requirement for the development of new modelling and simulation strategies to support emerging nanoelectronics industries. Modelling and simulation will be required to ecompass fabrication, characterisation and reliability of devices, circuits and systems in order to enable industry to reduce the cost of design and development and to shorten time to market. This spans across both More Moore, More than Moore and Beyond Moore domains of future research. Modelling research undertaken in the UK has the potential to bridge the gap between the technology, device, circuits and systems communities. It can benefit enormously from the provision of research oriented supercomputing facilities in the UK including HECToR and the UK escience and the Grid initiative. The UK research community and industry have the skills and the expertise and is well placed to play a leading role by setting the agenda and by developing the necessary theory, models and tools required to underpin developments in nanoscale silicon. G2.1: Atomic and molecular scale devices, circuits and systems; bottom up fabrication New models required for growth, self-asssembly, charge transport and circuits. Revolutionary rather than evolutionary development of models Atomic level description of devices Development of electronic structure Molecular description device interactions G2.2: Quantum description of charge transport; scaled devices Definition of the real physical system. Wide range of devices including CMOS, nanowire, CNT Process simulators; range of materials /interfaces Efficient simulators Variability G2.3: New Circuit/System level models Flexible models required to deal with a range of devices and large variability. Links with similar sensors and actuators Interfaces with other materials/organic systems Communications with on-chip optics/memory G2.4: Power management High density circuit performance limited by heating. Modelling dynamic heat flow. Trade-offs within chip/package/system design 7

8 G3: Characterisation for Silicon Based Technologies New and evolving characterisation techniques will enable future silicon technology to advance in the domains of More Moore, More than Moore and Beyond CMOS. The grand challenges are imposed by nm scale resolution features, high speed electrical performance, 3D structures, manufacturing quality and a need to introduce new materials or extend properties through strain. G3.1: Demonstrating nm scale characterisation techniques in Si how to improve characterisation resolution to keep pace with advancing nanoelectronics scaling (e.g. 22 nm node MOSFET and beyond); integration of nanoelectronics with nanotechnology. Develop new techniques for electrical/material using TEM, AFM Sample preparation (without altering property to be measured) Modelling (to extract more data) Calibration (to validate technique, models, designs) G3.2: Understanding interfaces CMOS gate stack requires high electrical quality interfaces using deposited dielectrics; heterogeneous integration requires novel solutions; bio/mems/electronics interfaces without impeding functionality. New techniques for spatially resolved characterisation Interface mapping at the atomic level (e.g. defects) High resolution electrical characterisation G3.3: 3D characterization Issue: Many existing techniques are 1D (e.g. SIMS) or 2D (e.g. TEM) but novel devices (including advanced CMOS) are increasingly 3D. Tomography Quasi 3D characterisation Profiling below the surface without de-layering Modelling G3.4: Non destructive characterisation and test structures destroying a device to measure is costly and it can only be measured after completion; measuring several properties concurrently yields more information; In-line monitoring for manufacturing must be fast and non-destructive. New techniques New test structures Modelling G3.5: Characterising new materials, device concepts More Moore raises new issues (materials, temperature, strain) for future generation CMOS technology which must be characterised; Beyond CMOS devices (e.g. based on spin) will require new 8

9 characterisation techniques. Characterisation for 22nm CMOS New characterisation techniques (e.g. for spin) 9

10 G4: New Material Systems for Silicon Based Technologies New materials using silicon as a platform are key to continuing advances in nanoelectronics as we approach the end of the scalability of CMOS, and the search is on for radical new non-fet-based technologies and new applications of silicon base material in arenas such as photonics. Huge potentials exist by augmenting silicon platforms with new material system/configurations to realise future devices/systems utilising quantum mechanical and other effects (e.g. molecular, polymer, ferromagnetic, ferroelectric). The strong expertise base and tradition in silicon and other semiconductor thin film growth in the UK provides an excellent environment in meeting these challenges, including traditional epitaxy techniques as well as further developing new process such as ALD. It is clear that semiconductors in some guise will likely continue to play a major role - acting as the host material for charge transport and then possibly spin transport and in photonic devices. Silicon platform and silicon processing know-how are certain to remain central to these developments. Full exploitation of futuristic semiconductors will demand much of the insulating and metallic materials that are essential for access to the active regions. High-k gate dielectric and metal contacts fall into this category. Although digital, analogue and memory devices are the major nanoelectronic components there is also considerable opportunity to advance photovoltaic and thermoelectric devices by incorporating new semiconductor materials. G4.1: New material systems: Deposition of new materials, such as graphene, high-k dielectrics, metals, piezo, silicide, silicate and oxide, GeSi/GeC/Ge heterostructres, on different silicon surfaces; Bottom up approach to quantum wires or dots through self assembled growth Identifying potential of electronic properties of new material systems, self-assembly, growth on different surface orientations, Managing and retaining strain at low temperatures, control of interfacial properties. G4.2: Growth route through new chemistry: materials Identify new precursors and chemistry to enable growth of new Manufacture/procurement of new precursors for delivery of metal, silicon, carbon, and germanium; Purification and delivery of precursors, Understanding the surface chemistry/physics related to the new precursors in the relevant deposition techniques G4.3: Understanding growth mechanism and develop new processes/precursors obtain Surface chemistry of growth reactions on different material system and surface orientations; Application and development of surface sensitive diagnostic tools to information on growth reactions. Atomistic modelling of growth reaction, 10

11 Development of new precursor/processes and optimisation of existing growth processes. 11

12 G5: Smart Nano: Nanoscience to Nanoengineering Nanotechnology is being actively pursued around the world and is beginning to reach the stage where it is being seriously considered for application in a number of mainstream silicon electronics technologies. A likely first application for nanotechnology is in non-volatile memories, where the use of a nanocrystal floating gate offers the prospect of lower programming voltages and higher speed operation. A second possible application is as inter-metal vias, where the high current-carrying capability of carbon nanotubes offers the prospect of lower series resistance. While promising progress is being made, a number of challenging problems remain to be solved before nanotechnology can find wider application in mainstream electronics. Many of these problems relate to the manufacturability of nanotechnology, but other problems are associated with achieving, in practice, the predicted benefits of device operation at the nanometer scale. To stimulate discussion and research on silicon-based nanotechnology, we propose a number of grand nanotechnology challenges for electronics and associated technologies G5.1: Robust methods for producing nanocrystals with a uniform size and position Issue: variability of nanocrystal size and position in an oxide layer causes problems in manufacturing G5.2: Silicon-compatible nanotube and wire growth methods Issue: metal catalysts required for nanotube & wire growth are lifetime-killers in silicon G5.3: Robust methods for directed self-assembly of nanotubes and wires Issue: for circuit applications, nanotubes and wires need to be in defined locations G5.4: Light emission from silicon using nanotechnology approaches Issue: light sources for optical interconnects and silicon-based integrated optics G5.5: Design approaches for coping with device variability Issue: variability in MOSFET characteristics a major problem in the design of nanocmos systems G5.6: Integration of nanotechnologies with silicon IC technology and MEMS Issue: New material developments and integration issues G5.7: Design approaches for nanotechnology circuits and systems 12

13 Issue: compact models and design strategies for nanowire and quantum dot technologies 13

14 G6: Silicon for Life: Towards Next Generation Healthcare Silicon already plays a major role in almost every sector of our life. For example, in medical technology microprocessors are widely used for medical image processing and numerous detectors in imaging systems which use both visible and X-ray wavelengths (e.g. CT) are silicon-based. In addition most patient monitoring systems, both portable and in hospitals, use silicon microprocessors to analyse information from their detectors and sensors. There are still many areas, however, where silicon has the potential to bring significant breakthroughs and to improve medical detection, treatment and patient care, It is enivisaged that the integration of silicon with novel materials and technologies will provide enormous opportunities. Integrating new materials with CMOS to achieve greater functionality is one field where the U.K. has led the world. UK Universities have already successfully spun off a number of companies (e.g. Vision (now part of ST Microelectronics), MED, and CRL Opto Ltd., É.). Post-processing/material integration technology is set to become a major focus and represent a major R&D challenge across the whole application field. It will be a key component in meeting the Silicon for Life Challenges as well as those associated with Smartnano and Eco-silicon. G6.1: Components Creation of lab-on-a-chip technology Array based structures/smart implants Miniaturised chip based on FRET/FLIM system Smart fluid manipulation Development of new sources, detectors and sensors Wireless power delivery and data transfer for implants New materials for sensors G6.2: Diagnostics medicine Cost effective medicine; GP-wide screening, self-test and home Silicon technology for oncological screening of skin, oral breast and prostate cancers at GP level Exploitation of mid- and far-infrared (or terahertz) part of the electromagnetic spectrum Robust and rapid DNA screening at point of care G6.3: Imaging Portable and inexpensive medical and security screening Large imaging arrays for use in medical applications and imaging of explosives and weapons Exploitation of non-ionising terahertz technology Silicon platforms for excitation and detection for FRET/FLIM based analysis G6.4: Datacomms imaging Enormous bandwidth required for data produced by medical 14

15 Development of cheap silicon photonics systems for communications between detector arrays and microprocessors 15

16 G7: Eco-silicon: Energy The issues of sustainability of the environment and the efficient utilisation of energy resources are currently amongst the most important facing Mankind. There are many ways in which silicon technology can contribute to meeting this challenge, yet relatively little is being done in a proactive sense. Silicon is currently the most important material used in photovoltaic applications, and silicon solar cells will constitute an ever more significant renewable energy source as organic fossil fuel supplies dwindle. In addition the huge number of silicon devices consume large amount of energy and there are significant opportunities to reduce this by both design and process enhancements. Thermoelectric (Seebeck) generators based on Si/SiGe offer exciting eco-friendly alternative power generation systems, utilizing body heat, geothermal, solar and combustion engine waste heat. They have potential applications in medical electronics, bio- MEMs, space science and IR detectors requiring no power supply. Culture in many societies is dominated by portable, battery powered, electronic devices and there is a growing need to find alternative power supplies. G7.1: Energy Supply: crystalline solar cells, whilst suitably efficient, are too expensive. Amorphous devices, although cheaper, are relatively inefficient and suffer from degradation problems, whilst poly-crystalline thin-film devices need either a modest increase in efficiency or a modest decrease in cost to be attractive for true mass production. Incorporation of nanocrystals in photovoltaic cells Improve efficiency / cost trade-off for both solar and fuel cells Development of thermoelectric generators for nanoscale systems G7.2: Energy Consumption: explore ways in which electrical energy consumption (dominated by silicon microelectronic circuits) can be reduced, accepting that improvements in battery technology is limited. Low power design, both from the perspective of circuit design and also at the fundamental transistor level. Low power IC technologies Novel device/circuit innovations to reduce power consumption Integrate permalloy cored inductors with silicon IC control circuitry. G7.3: Energy Management: Efficient utilisation of energy resources by better monitoring (and hence regulating) of consumption; Micro-fuel cell systems could use silicon based MEMS technology Develop cheap systems for energy monitoring (domestic, urban) Deployment of monitoring system Communication with monitoring system Integration of novel material/nanotechnology for fuel cell membranes 16