LT GHz 2.4GHz High Linearity Direct Quadrature Modulator DESCRIPTIO FEATURES APPLICATIO S TYPICAL APPLICATIO

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1 FEATURES High Input Impedance Version of the LT5528 Direct Conversion to.5ghz 2.4GHz High OIP3: 22.8dBm at 2GHz Low Output Noise Floor at 2MHz Offset: No : 58.2dBm/Hz P OUT = 4dBm: 52.5dBm/Hz 4-Ch W-CDMA ACPR: 64dBc at 2.4GHz Integrated LO Buffer and LO Quadrature Phase Generator 5Ω AC-Coupled Single-Ended LO and Ports Low Carrier Leakage: 49dBm at 2GHz High Image Rejection: 4dB at 2GHz 6-Lead QFN 4mm 4mm Package APPLIC S U Infrastructure Tx for DCS, PCS and UMTS Bands Image Reject Up-Converters for DCS, PCS and UMTS Bands Low Noise Variable Phase-Shifter for.5ghz to 2.4GHz Local Oscillator Signals.5GHz 2.4GHz High Linearity Direct Quadrature Modulator DESCRIPTIO U The LT 558 is a direct I/Q modulator designed for high performance wireless applications, including wireless infrastructure. It allows direct modulation of an signal using differential baseband I and Q signals. It supports PHS, GSM, EDGE, TD-SCDMA, CDMA, CDMA2, W-CDMA and other systems. It may also be configured as an image reject up-converting mixer, by applying 9 phase-shifted signals to the I and Q inputs. The high impedance I/Q baseband inputs consist of voltage-to-current converters that in turn drive double-balanced mixers. The outputs of these mixers are summed and applied to an on-chip transformer, which converts the differential mixer signals to a 5Ω single-ended output. The balanced I and Q baseband input ports are intended for DC coupling from a source with a common mode voltage level of about 2.V. The LO path consists of an LO buffer with single-ended input, and precision quadrature generators that produce the LO drive for the mixers. The supply voltage range is 4.5V to 5.25V., LTC and LT are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. TYPICAL APPLIC U.5GHz to 2.4GHz Direct Conversion Transmitter Application with LO Feedthrough and Image Calibration Loop W-CDMA ACPR, AltCPR and Noise vs Output Power at 24MHz for and 4 Channels BASEBAND GENERATOR ADC I-DAC Q-DAC EN 4 6 V-I 7 I-CHANNEL Q-CHANNEL 5 V-I 2, 4, 6, 9,, 2, 5, 7 8, 3 9 BALUN 3 VCO/SYNTHESIZER 5V nf 2 PA =.5GHz TO 2.4GHz LO FEEDTHROUGH CAL OUT IMAGE CAL OUT CAL ACPR, ALTCPR (dbc) 4-CH ACPR 4-CH ALTCPR 65 -CH ACPR CH ALTCPR -CH NOISE 8 4-CH NOISE 85 DOWNLINK TEST MODEL 64 DPCH OUTPUT POWER PER CARRIER (dbm) NOISE FLOOR AT 3MHz OFFSET (dbm/hz) 558 TAa 558 TAb

2 ABSOLUTE AXI U RATI GS W W W (Note ) Supply Voltage...5.5V Common Mode Level of BBPI, BBMI and BBPQ, BBMQ...2.5V Operating Ambient Temperature (Note 2)... C to 85 C Storage Temperature Range C to 25 C Voltage on Any Pin Not to Exceed... mv to + 5mV U U U W PACKAGE/ORDER I FOR EN LO TOP VIEW BBMI BBPI VCC BBMQ BBPQ VCC 2 9 ORDER PART NUMBER EUF UF PART MARKING 558 T JMAX = 25 C, θ JA = 37 C/W EXPOSED PAD (PIN 7) IS MUST BE SOLDERED TO THE PCB Consult LTC Marketing for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS = 5V, EN = High, T A = 25 C, f LO = 2GHz, f = 2.2GHz, P LO = dbm. BBPI, BBMI, BBPQ, BBMQ inputs 2.6V DC, Baseband Input Frequency = 2MHz, I and Q 9 shifted (upper sideband selection). P, OUT = dbm, unless otherwise noted. (Note 3) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Output () f Frequency Range 3dB Bandwidth.5 to 2.4 GHz Frequency Range db Bandwidth.7 to 2.2 GHz S 22, ON Output Return Loss EN = High (Note 6) 4 db S 22, OFF Output Return Loss EN = Low (Note 6) 2 db NFloor Output Noise Floor No Input Signal (Note 8) 58.2 dbm/hz P OUT = 4dBm (Note 9) 52.5 dbm/hz P OUT = 4dBm (Note ) 5. dbm/hz G P Conversion Power Gain P OUT /P IN, I&Q.6 db G V Conversion Voltage Gain 2 log(v OUT, 5Ω /V IN, DIFF, I or Q ) 4 db P OUT Absolute Output Power V P-P, DIFF CW Signal, I and Q dbm G 3LO vs LO 3 LO Conversion Gain Difference (Note 7) 28 db OPdB Output db Compression (Note 7) 8.5 dbm OIP2 Output 2nd Order Intercept (Notes 3, 4) 49 dbm OIP3 Output 3rd Order Intercept (Notes 3, 5) 22.8 dbm IR Image Rejection (Note 6) dbc LOFT Carrier Leakage EN = High, P LO = dbm (Note 6) 49 dbm (LO Feedthrough) EN = Low, P LO = dbm (Note 6) 58 dbm LO Input (LO) f LO LO Frequency Range.5 to 2.4 GHz P LO LO Input Power 5 dbm S, ON LO Input Return Loss EN = High (Note 6) 8 db S, OFF LO Input Return Loss EN = Low (Note 6) 5 db NF LO LO Input Referred Noise Figure (Note 5) at 2GHz 4 db G LO LO to Small Signal Gain (Note 5) at 2GHz 23.8 db IIP3 LO LO Input Linearity (Note 5) at 2GHz 9 dbm 2

3 ELECTRICAL CHARACTERISTICS Note : Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: Specifications over the C to 85 C temperature range are assured by design, characterization and correlation with statistical process controls. Note 3: Tests are performed as shown in the confi guration of Figure 8. Note 4: On each of the four baseband inputs BBPI, BBMI, BBPQ and BBMQ. Note 5: V(BBPI) V(BBMI) = V DC, V(BBPQ) V(BBMQ) = V DC. Note 6: Maximum value within db bandwidth. Note 7: An external coupling capacitor is used in the output line. Note 8: At 2MHz offset from the LO signal frequency. Note 9: At 2MHz offset from the CW signal frequency. Note : At 5MHz offset from the CW signal frequency. Note : power is within % of fi nal value. Note 2: power is at least 3dB lower than in the ON state. = 5V, EN = High, T A = 25 C, f LO = 2GHz, f = 2.2GHz, P LO = dbm. BBPI, BBMI, BBPQ, BBMQ inputs 2.6V DC, Baseband Input Frequency = 2MHz, I and Q 9 shifted (upper sideband selection). P, OUT = dbm, unless otherwise noted. (Note 3) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Baseband Inputs (BBPI, BBMI, BBPQ, BBMQ) BW BB Baseband Bandwidth 3dB Bandwidth 4 MHz V CMBB DC Common Mode Voltage (Note 4) 2.6 V R IN, DIFF Differential Input Resistance Between BBPI and BBMI (or BBPQ and BBMQ) 2.9 kω R IN, CM Common Mode Input Resistance BBPX and BBMX Shorted Together 5 Ω I CM, COMP Common Mode Compliance Current Range BBPX and BBMX Shorted Together (Note 8) 73 to 48 µa P LO2BB Carrier Feedthrough on BB P OUT = (Note 4) dbm IPdB Input db Compression Point Differential Peak-to-Peak (Note 7) 2.7 V P-P, DIFF ΔG I/Q I/Q Absolute Gain Imbalance.6 db Δφ I/Q I/Q Absolute Phase Imbalance deg Power Supply ( ) Supply Voltage V I CC, ON Supply Current EN = High ma I CC, OFF Supply Current, Sleep Mode EN = V.5 5 µa t ON Turn-On Time EN = Low to High (Note ).2 µs t OFF Turn-Off Time EN = High to Low (Note 2).3 µs Enable (EN), Low = Off, High = On Enable Input High Voltage EN = High. V Input High Current EN = 5V 24 µa Sleep Input Low Voltage EN = Low.5 V Note 3: Baseband is driven by 2MHz and 2.MHz tones. Drive level is set in such a way that the two resulting output tones are dbm each. Note 4: IM2 measured at LO frequency + 4.MHz. Note 5: IM3 measured at LO frequency +.9MHz and LO frequency + 2.2MHz. Note 6: Amplitude average of the characterization data set without image or LO feedthrough nulling (unadjusted). Note 7: The difference in conversion gain between the spurious signal at f = 3 LO BB versus the conversion gain at the desired signal at f = LO + BB for BB = 2MHz and LO = 2GHz. Note 8: Common mode current range where the common mode (CM) feedback loop biases the part properly. The common mode current is the sum of the current fl owing into the BBPI (or BBPQ) pin and the current fl owing into the BBMI (or BBMQ) pin. 3

4 TYPICAL PEOR A CE CHARACTERISTICS SUPPLY CURRENT (ma) T A = 85 C T A = 25 C 5. SUPPLY VOLTAGE (V) U W = 5V, EN = High, T A = 25 C, f LO = 2.4GHz, P LO = dbm. BBPI, BBMI, BBPQ, BBMQ inputs 2.6V DC, Baseband Input Frequency f BB = 2MHz, I and Q 9 shifted without image or LO feedthrough nulling. f = f BB + f LO (upper sideband selection). P, OUT = dbm ( dbm/tone for 2-tone measurements), unless otherwise noted. (Note 3) Supply Current vs Supply Voltage T A = C 5.5 OUTPUT POWER (dbm) Output Power vs LO Frequency at V P-P Differential Baseband Drive 5V, T A = C LO FREQUENCY (GHz) VOLTAGE GAIN (db), OPdB (dbm) Voltage Gain and Output db Compression vs LO Frequency and Temperature OPdB GAIN LO FREQUENCY (GHz) 4.5V 5.5V 5V 558 G 558 G2 558 G3 VOLTAGE GAIN (db), OPdB (dbm) Voltage Gain and Output db Compression vs LO Frequency and Supply Voltage OPdB GAIN 4.5V 5.5V 5V LO FREQUENCY (GHz) OIP3 (dbm) Output IP3 and Noise Floor vs LO Frequency and Temperature 26 OIP NOISE FLOOR 2 f BB, = 2MHz f BB, 2 = 2.MHz 8 NO BASEBAND SIGNAL 64 6 f LO = 2.4GHz (FIXED) FOR NOISE LO/NOISE FREQUENCY (GHz) T A = C T A = 85 C T A = 25 C NOISE FLOOR (dbm/hz) OIP3 (dbm) Output IP3 and Noise Floor vs LO Frequency and Supply Voltage OIP3 4.5V V V 5 2 f BB, = 2MHz f BB, 2 = 2.MHz NOISE FLOOR NO BASEBAND SIGNAL 64 6 f LO = 2.4GHz (FIXED) FOR NOISE LO/NOISE FREQUENCY (GHz) NOISE FLOOR (dbm/hz) 558 G4 558 G5 558 G6 LO FT (dbm) 45 4 LO Feedthrough to Output vs LO Frequency 5V, T A = C LO FREQUENCY (GHz) 558 G7 P(2 LO) (dbm) LO Leakage to Output vs 2 LO Frequency 5V, T A = C LO FREQUENCY (GHz) 558 G8 P(3 LO) (dbm) LO Leakage to Output vs 3 LO Frequency 5V, T A = C LO FREQUENCY (GHz) 558 G9

5 TYPICAL PEOR A CE CHARACTERISTICS U W = 5V, EN = High, T A = 25 C, f LO = 2.4GHz, P LO = dbm. BBPI, BBMI, BBPQ, BBMQ inputs 2.6V DC, Baseband Input Frequency f BB = 2MHz, I and Q 9 shifted without image or LO feedthrough nulling. f = f BB + f LO (upper sideband selection). P, OUT = dbm ( dbm/tone for 2-tone measurements), unless otherwise noted. (Note 3) IMAGE REJECTION (dbc) Image Rejection vs LO Frequency 45 5V, T A = C LO FREQUENCY (GHz) 558 G ABSOLUTE I/Q GAIN IMBALANCE (db) 2. Absolute I/Q Gain Imbalance vs LO Frequency 5V, T A = C LO FREQUENCY (GHz) 558 G ABSOLUTE I/Q PHASE IMBALANCE (DEG) Absolute I/Q Phase Imbalance vs LO Frequency 5V, T A = C LO FREQUENCY (GHz) 558 G2 2 Voltage Gain vs LO Power 24 Output IP3 vs LO Power CW Output Power, HD2 and HD3 vs Baseband Voltage and Temperature VOLTAGE GAIN (db) LO INPUT POWER (dbm) 5V, T A = C G3 OIP3 (dbm) V, T A = C LO INPUT POWER (dbm) 558 G4 HD2, HD3 (dbc) 2 7 HD3 T A = C T A = 85 C T A = 25 C 2 HD2 HD2 = MAX POWER AT f LO + 2 f BB OR f LO 2 f BB HD3 = MAX POWER AT f LO + 3 f BB OR f LO 3 f BB I AND Q BASEBAND VOLTAGE (V P-P, DIFF ) 558 G5 CW OUTPUT POWER (dbm) HD2, HD3 (dbc) 2 CW Output Power, HD2 and HD3 vs Baseband Voltage and Supply Voltage HD3 4.5V 5.5V 5V 2 HD2 HD2 = MAX POWER AT f LO + 2 f BB OR f LO 2 f BB HD3 = MAX POWER AT f LO + 3 f BB OR f LO 3 f BB I AND Q BASEBAND VOLTAGE (V P-P, DIFF ) CW OUTPUT POWER (dbm) LO FT (dbm), IR (dbc) LO Feedthrough to Output and Image Rejection vs Baseband Voltage and Temperature T A = C T A = 85 C T A = 25 C LO FT I AND Q BASEBAND VOLTAGE (V P-P, DIFF ) 558 G6 558 G7 IR LO FT (dbm), IR (dbc) LO Feedthrough to Output and Image Rejection vs Baseband Voltage and Supply Voltage 4.5V 5.5V 5V LO FT I AND Q BASEBAND VOLTAGE (V P-P, DIFF ) IR 558 G8 5

6 TYPICAL PEOR A CE CHARACTERISTICS U W = 5V, EN = High, T A = 25 C, f LO = 2.4GHz, P LO = dbm. BBPI, BBMI, BBPQ, BBMQ inputs 2.6V DC, Baseband Input Frequency f BB = 2MHz, I and Q 9 shifted without image or LO feedthrough nulling. f = f BB + f LO (upper sideband selection). P, OUT = dbm ( dbm/tone for 2-tone measurements), unless otherwise noted. (Note 3) 65 6 Output IP2 vs LO Frequency f BB, = 2MHz f BB,2 = 2.MHz f IM2 = f BB, + f BB,2 + f LO LO and Port Return Loss vs Frequency LO PORT, EN = LOW OIP2 (dbm) V, T A = C LO FREQUENCY (GHz) S (db) 2.3 PORT, EN = HIGH, NO LO PORT, EN = HIGH, P LO = dbm FREQUENCY (GHz) PORT, EN = LOW LO PORT, EN = HIGH 558 G9 558 G2 PI FU CTIO S U U U EN (Pin ): Enable Input. When the enable pin voltage is higher than V, the IC is turned on. When the input voltage is less than.5v, the IC is turned off. (Pins 2, 4, 6, 9,, 2, 5): Ground. Pins 6, 9, 5 and 7 (exposed pad) are connected to each other internally. Pins 2 and 4 are connected to each other internally and function as the ground return for the LO signal. Pins and 2 are connected to each other internally and function as the ground return for the on-chip balun. For best performance, pins 2, 4, 6, 9,, 2, 5 and the Exposed Pad (Pin 7) should be connected to the printed circuit board ground plane. LO (Pin 3): LO Input. The LO input is an AC-coupled singleended input with approximately 5Ω input impedance at frequencies. Externally applied DC voltage should be within the range.5v to +.5V in order to avoid turning on ESD protection diodes. BBPQ, BBMQ (Pins 7, 5): Baseband Inputs for the Q-Channel, with 2.9kΩ Differential Input Impedance. Internally biased at about 2.6V. Applied common mode voltage must stay below 2.5V. (Pins 8, 3): Power Supply. Pins 8 and 3 are connected to each other internally. It is recommended to use.µf capacitors for decoupling to ground on each of these pins. (Pin ): Output. The output is an AC-coupled single-ended output with approximately 5Ω output impedance at frequencies. Externally applied DC voltage should be within the range.5v to +.5V in order to avoid turning on ESD protection diodes. BBPI, BBMI (Pins 4, 6): Baseband Inputs for the I-Channel, with 2.9kΩ Differential Input Impedance. Internally biased at about 2.6V. Applied common mode voltage must stay below 2.5V. Exposed Pad (Pin 7): Ground. This pin must be soldered to the printed circuit board ground plane. 6

7 BLOCK DIAGRA W 8 3 BBPI BBMI 4 6 V-I 9 BALUN BBPQ BBMQ 7 5 V-I EN LO BD APPLIC S I FOR The consists of I and Q input differential voltageto-current converters, I and Q up-conversion mixers, an output balun, an LO quadrature phase generator and LO buffers. External I and Q baseband signals are applied to the differential baseband input pins, BBPI, BBMI, and BBPQ, BBMQ. These voltage signals are converted to currents and translated to frequency by means of double-balanced up-converting mixers. The mixer outputs are combined in an output balun, which also transforms the output impedance to 5Ω. The center frequency of the resulting signal is equal to the LO signal frequency. The LO input drives a phase shifter which splits the LO signal into in-phase and quadrature LO signals. These LO signals are then applied to on-chip buffers which drive the upconversion mixers. Both the LO input and output are single-ended, 5Ω-matched and AC coupled. = 5V C BALUN LOMI FROM Q LOPI BBPI 2Ω V REF = 5mV.8pF.3k CM BBMI 2Ω.8pF.3k Figure. Simplifi ed Circuit Schematic of the (Only I-Half is Drawn) 558 F 7

8 APPLIC S I FOR Baseband Interface The baseband inputs (BBPI, BBMI), (BBPQ, BBMQ) present a differential input impedance of about 2.9kΩ. At each of the four baseband inputs, a lowpass fi lter using 2Ω and.8pf to ground is incorporated (see Figure ), which limits the baseband bandwidth to approximately 25MHz ( db point). The common mode voltage is about 2.6V and is slightly temperature dependent. At T A = o C, the common mode voltage is about 2.9V and at T A = 85 o C it is about.92v. If the I/Q signals are DC-coupled to the, it is important that the applied common mode voltage level of the I and Q inputs is about 2.6V in order to properly bias the. Some I/Q test generators allow setting the common mode voltage independently. In this case, the common mode voltage of those generators must be set to.3v to match the internal bias, because for DC signals, there is no 6dB source-load voltage division (see Figure 2). + Figure 2. DC Voltage Levels for a Generator Programmed at.3v DC for a 5Ω Load and for the as a Load 8 5Ω 2.6V DC.3V DC GENERATOR 5Ω + 5Ω 2.6V DC 2.6V DC GENERATOR 558 F2.5k 2.6V DC The should be driven differentially; otherwise, the even-order distortion products will degrade the overall linearity severely. Typically, a DAC will be the signal source for the. A reconstruction fi lter should be placed between the DAC output and the s baseband inputs. DC coupling between the DAC outputs and the baseband inputs is recommended. Active level shifters may be required to adapt the common mode level of the DAC outputs to the common mode input voltage of the. It is also possible to achieve a DC level shift with passive components, depending on the application. For example, if fl at frequency response to DC is not required, then the interface circuit of Figure 3 may be used. This figure shows a commonly used ma 2mA DAC output followed by a passive 5th order lowpass filter. The DC-coupled interface allows adjustment of the + DAC s differential output current to minimize the LO to feedthrough. Resistors R3A, R3B, R4A and R4B translate the DAC s output common mode level from about.5v DC to the s input at about 2.6V DC. For these resistors, % accuracy is recommended. For different ambient temperatures, the input common mode level varies with a temperature coefficient of about 2.7mV/ C. The internal common mode feedback loop will correct these level changes in order to bias the at the correct operating point. Resistors R3 and R4 are chosen high enough that the common mode compliance current value will not be exceeded at the inputs of the as a result of temperature shifts. Capacitors C4A and C4B minimize the input signal attenuation caused by the network R3A, R3B, R4A and R4B. This results in a gain difference between low frequency and high frequency baseband signals. The high frequency baseband 3dB corner point is approximately given by: f 3dB = /[2π C4A (R3A R4A (R IN, DIFF /2)] In this example, f 3dB = 58kHz. This corner point should be set significantly lower than the minimum baseband signal frequency by choosing large enough capacitors C4A and C4B. For signal frequencies significantly lower than f 3dB, the gain is reduced by approximately G DC = 2 log [R3A (R IN, DIFF /2)]/[R3A (R IN, DIFF /2) + R4A] In this example, G DC = db. Inserting the network of R3A, R3B, R4A, R4B, C4A and C4B has the following consequences: Reduced LO feedthrough adjustment range. LO to feedthrough can be reduced by adjusting the differential DC offset voltage applied to the I and/or Q inputs. Because of the DC gain reduction, the range of adjustment is reduced. The resolution of the offset adjustment is improved by the same gain reduction factor. DC notch for uneven number of channels. The interface drawn in Figure 3 might not be practical for an uneven number of channels, since the gain at DC is lower and will appear in the center of (one of) the channel(s). In that case, a DC-coupled level shifting circuit is required, or the LT5528 might be a better solution.

9 APPLIC S I FOR Introduction of a (low frequency) time constant during startup. For TDMA-like systems the time constant introduced by C4A and C4B can cause some delay during start-up. The associated time constant is approximately given by T D = R IN, CM (C4A + C4B). In this example it will result in a delay of about T D = 5 6.6n = 693ns. The maximum sinusoidal single sideband output power is about 5.5dBm for a full ma to 2mA DAC swing. This maximum output level is usually limited by the compliance voltage range of the DAC (V COMPL ) which is assumed here to be.25v. When the DAC output voltage swing is larger than this compliance voltage, the baseband signal will distort and linearity requirements usually will not be met. The following situations can cause the DAC s compliance voltage limit to be exceeded:. Too high DAC load impedance. If the DC impedance to ground is higher than V COMPL /I MAX =.25/.2 = 62.5Ω, the compliance voltage is exceeded for a full DAC swing. In Figure 3, two Ω resistors in parallel are used, resulting in a DC impedance to ground of 5Ω. 2. Too much DC offset. In some DACs, an additional DC offset current can be set. For example, if the maximum offset current is set to I MAX /8 = 2.5mA, then the maximum DC DAC load impedance to ground is reduced to V COMPL /I MAX ( + /8) =.25/.225 = 55Ω. 3. DC shift caused by R3A, R3B, R4A and R4B if used. The DC shift network consisting of R3A, R3B, R4A and R4B will increase the voltage on the DAC output by dumping an extra current into resistors RA, RB, R2A and R2B. This current is about ( V DAC )/(R3A + R4A) = (5.5)/(3.k k) =.52mA. Maximum impedance to ground will then be V COMPL /(I MAX + I LS ) =.25/.252 = 6.9Ω. 4. Reflection of out-of-band baseband signal power. DAC output signal components higher than the cut-off frequency of the lowpass filter will not see R2A and R2B as load resistors and therefore will see only RA, RB and the filter components as a load. Therefore, it is important to start the lowpass filter with a capacitor (C), in order to shunt the DAC higher frequency components and thereby, limit the required extra voltage headroom. The s output db compression point is about 8.5dBm, and with the interface network described above, a common DAC cannot drive the part into compression. However, it is possible to increase the driving capability by using a negative supply voltage. For example, if a V supply is available, resistors RA, RB, R2A and R2B can be made 2Ω each and connected with one side to the V supply instead of ground. Typically, the voltage compliance range of the DAC is V to.25v, so the DAC s output voltage will stay within this range. Almost 6dB extra voltage swing is available, thus enabling the DAC to drive the beyond its db compression point. Resistors R3A, R3B, R4A, R4B and the lowpass filter components must be adjusted for this case. = 5.5dBm, MAX 5V C BALUN LOMI FROM Q C4A 3.3nF LOPI DAC ma TO 2mA ma TO 2mA RA Ω C RB Ω LA LB C2 L2A L2B C3.53V DC R2A R4A Ω 3.k R2B Ω R4B 3.k BBPI 2.V R3A DC 5.63k R3B 5.63k BBMI 2Ω 2Ω.8pF.3k.8pF.3k V REF = 5mV CM.53V DC 2.V DC C4B 3.3nF Figure 3. 5th Order Filtered Baseband Interface with Common DAC (Only I-Channel is Shown) 558 F3 9

10 APPLIC S I FOR Some DACs use an output common mode voltage of 3.3V. In that case, the interface circuit drawn in Figure 4 may be used. The performance is very similar to the performance of the DAC interface drawn in Figure 3, since the source and load impedances of the lowpass ladder fi lter are both 2Ω differential and the current drive is the same. There are some small differences: The baseband drive capability cannot be improved using an extra supply voltage, since the compliance range of the DACs in Figure 4 is typically 3.3V.5V to 3.3V +.5V, so its range has already been fully used. G DC and f 3dB are a little different, since R3A (and R3B) is 4.99k instead of 5.6k to accommodate the proper DC level shift. LO Section The internal LO input amplifi er performs single-ended to differential conversion of the LO input signal. Figure 5 shows the equivalent circuit schematic of the LO input. The internal, differential LO signal is split into in-phase and quadrature (9 phase shifted) signals that drive LO buffer sections. These buffers drive the double balanced I and Q mixers. The phase relationship between the LO input and the internal in-phase LO and quadrature LO signals is fixed, and is independent of start-up conditions. The phase shifters are designed to deliver accurate quadrature signals for an LO frequency near 2GHz. For frequencies LO INPUT 558 F5 2pF Z IN 57Ω Figure 5. Equivalent Circuit Schematic of the LO Input significantly below.8ghz or above 2.4GHz, the quadrature accuracy will diminish, causing the image rejection to degrade. The LO pin input impedance is about 5Ω, and the recommended LO input power is dbm. For lower LO input power, the gain, OIP2, OIP3 and dynamic range will degrade, especially below 5dBm and at T A = 85 C. For high LO input power (e.g. 5dBm), the LO feedthrough will increase, without improvement in linearity or gain. Harmonics present on the LO signal can degrade the image rejection, because they introduce a small excess phase shift in the internal phase splitter. For the second (at 4GHz) and third harmonics (at 6GHz) at 2dBc level, the introduced signal at the image frequency is about dbc or lower, corresponding to an excess phase shift much less than degree. For the second and third harmonics at dbc, still the introduced signal at the image frequency is about 46dBc. Higher harmonics than the third will have less impact. The LO return loss typically will be better than 4dB over the.7ghz to 2.4GHz range. Table shows the LO port input impedance vs frequency. = 5.5dBm, MAX 5V C BALUN LOMI FROM Q 3.3V ma TO 2mA DAC ma TO 2mA LA C LB C2 L2A L2B C3 3.3V DC C4A 3.3nF R4A 3.k R4B 3.k C4B 3.3nF BBPI 2.V DC R3A 4.99k R3B 4.99k BBMI 3.3V DC 2.V DC 2Ω 2Ω.8pF.3k.8pF.3k V REF = 5mV Figure 4. 5th Order Filtered Baseband Interface with 3.3V CM DAC (Only I-Channel is Shown). CM LOPI 558 F4

11 APPLIC S I FOR Table. LO Port Input Impedance vs Frequency for EN = High Frequency Input Impedance S MHz Ω Mag Angle j j j j j j j j The input impedance of the LO port is different if the part is in shut-down mode. The LO input impedance for EN = Low is given in Table 2. Table 2. LO Port Input Impedance vs Frequency for EN = Low Frequency Input Impedance S MHz Ω Mag Angle j j j j j j j j Section After up-conversion, the outputs of the I and Q mixers are combined. An on-chip balun performs internal differential to single-ended output conversion, while transforming the output signal impedance to 5Ω. Table 3 shows the port output impedance vs frequency. Table 3. Port Output Impedance vs Frequency for EN = High and P LO = dbm Frequency Input Impedance S 22 MHz Ω Mag Angle j j j j j j j j Ω 2pF 3nH 2pF 558 F6 OUTPUT The output S 22 with no LO power applied is given in Table 4. Table 4. Port Output Impedance vs Frequency for EN = High and No LO Power Applied Frequency Input Impedance S 22 MHz Ω Mag Angle j j j j j j j j For EN = Low the S 22 is given in Table 5. Table 5. Port Output Impedance vs Frequency for EN = Low Frequency Input Impedance S 22 MHz Ω Mag Angle 2.9+j j j j j j j j To improve S 22 for lower frequencies, a shunt capacitor can be added to the output. At higher frequencies, a shunt inductor can improve the S 22. Figure 6 shows the equivalent circuit schematic of the output. Figure 6. Equivalent Circuit Schematic of the Output Note that an ESD diode is connected internally from the output to ground. For strong output signal levels (higher than 3dBm) this ESD diode can degrade the linearity performance if the 5Ω termination impedance is connected directly to ground. To prevent this, a

12 APPLIC S I FOR coupling capacitor can be inserted in the output line. This is strongly recommended during a db compression measurement. Enable Interface Figure 7 shows a simplifi ed schematic of the EN pin interface. The voltage necessary to turn on the is.v. To disable (shutdown) the chip, the Enable voltage must be below.5v. If the EN pin is not connected, the chip is disabled. This EN = Low condition is guaranteed by the 75kΩ on-chip pull-down resistor. It is important that the voltage at the EN pin does not exceed by more than.5v. If this should occur, the full chip supply current could be sourced through the EN pin ESD protection diodes. Damage to the chip may result. J BBIM J BBIM EN BBQM J4 LO IN J5 R R3 3.k R5 52.3Ω C 3.3nF BOARD NUMBER: DC83A BBMI BBPI EN LO BBMQ BBPQ Figure 8. Evaluation Board Circuit Schematic R 5.62k C2 3.3nF R4 3.k C nf BOARD NUMBER: DC729A R2 5.62k J2 BBIP J6 C2 nf J3 OUT BBQP 558 F8 R6 52.3Ω J2 BBIP E2 Evaluation and Demo Boards Figure 8 shows the schematic of the evaluation board that was used for the measurements summarized in the Electrical Characteristics tables and the Typical Performance Characteristic plots. Figure 9 shows the demo board schematic. Resistors R3, R4, R and R may be replaced by shorting wires if a flat frequency response to DC is required. A good ground connection is required for the exposed pad of the package. If this is not done properly, the performance will degrade. The exposed pad also provides heat sinking for the part and minimizes the possibility of the chip overheating. R7 (optional) limits the Enable pin current in the event that the Enable pin is pulled high while the inputs are low. In Figures, and 2 the silk screen and the demo board PCB layouts are shown. If improved LO and Image suppression is required, an LO feedthrough calibration and an Image suppression calibration can be performed. 2 EN 75k 25k 558 F7 Figure 7. EN Pin Interface BBQM R7 EN E J4 LO IN J5 R2 52.3Ω C5 3.3nF E BBMI BBPI EN LO BBMQ BBPQ 5 R k E3 R8 5.62k C6 3.3nF R 3.k C4 nf C3 nf J3 OUT R9 5.62k R3 52.3Ω Figure 9. Demo Board Circuit Schematic Figure. Component Side Silk Screen of Demo Board J6 BBQP 558 F9

13 APPLIC S I FOR Figure. Component Side Layout of Demo Board Figure 2. Bottom Side Layout of Demo Board I-DAC 4 6 V-I 8, 3 5V nf 2 =.5GHz TO 2.4GHz Q-DAC EN 7 5 I-CHANNEL Q-CHANNEL V-I 9 BALUN CAL PA LO FEEDTHROUGH CAL OUT IMAGE CAL OUT BASEBAND GENERATOR 2, 4, 6, 9,, 2, 5, 7 3 VCO/SYNTHESIZER ADC 558 F3 Figure 3..5GHz to 2.4GHz Direct Conversion Transmitter Application with LO Feedthrough and Image Calibration Loop Application Measurements The is recommended for base-station applications using various modulation formats. Figure 3 shows a typical application. The CAL box in Figure 3 allows for LO feedthrough and Image suppression calibration. Figure 4 shows the ACPR performance for W-CDMA using one or four channel modulation. Figures 5, 6 and 7 illustrate the, 2 and 4-channel W-CDMA measurement. To calculate ACPR, a correction is made for the spectrum analyzer noise fl oor. If the output power is high, the ACPR will be limited by the linearity performance of the part. If the output power is low, the ACPR will be limited by the noise performance of the part. In the middle, an optimum ACPR is obtained. Because of the s very high dynamic range, the test equipment can limit the accuracy of the ACPR measurement. Consult the factory for advice on ACPR measurement, if needed. The ACPR performance is sensitive to the amplitude match of the BBIP and BBIM (or BBQP and BBQM) input voltage. This is because a difference in AC voltage amplitude will give rise to a difference in amplitude between the even-order harmonic products generated in the internal V-I converter. As a result, they will not cancel out entirely. Therefore, it 3

14 APPLIC S I FOR ALTCPR (dbc) ACPR, CH NOISE 4-CH ACPR -CH ALTCPR 4-CH ALTCPR -CH ACPR -CH NOISE DOWNLINK TEST MODEL 64 DPCH OUTPUT POWER PER CARRIER (dbm) is important to keep the amplitudes at the BBIP and BBIM inputs (or BBQP and BBQM) as equal as possible. When the temperature is changed after calibration, the LO feedthrough and the Image Rejection performance will change. This is illustrated in Figure 8. The LO feedthrough 558 F Figure 4. W-CDMA ACPR, ALTCPR and Noise vs Output Power at 24MHz for and 4 Channels NOISE FLOOR AT 3MHz OFFSET (dbm/hz) and Image Rejection can also change as function of the baseband drive level, as is depicted in Figure 9. The output power, IM2 and IM3 vs two-tone baseband drive level are given in Figure 2. POWER IN 3kHz BW (dbm) UNCORRECTED SPECTRUM DOWNLINK TEST MODEL 64 DPCH CORRECTED SPECTRUM SYSTEM NOISE FLOOR FREQUENCY (MHz) 558 F5 Figure 5. -Channel W-CDMA Spectrum POWER IN 3kHz BW (dbm) UNCORRECTED SPECTRUM DOWNLINK TEST MODEL 64 DPCH CORRECTED SPECTRUM SYSTEM NOISE FLOOR FREQUENCY (MHz) Figure 6. 2-Channel W-CDMA Spectrum 558 F6 POWER IN 3kHz BW (dbm) UNCORRECTED SPECTRUM SYSTEM NOISE FLOOR DOWNLINK TEST MODEL 64 DPCH CORRECTED SPECTRUM FREQUENCY (MHz) Figure 7. 4-Channel W-CDMA Spectrum 558 F7 LO FT (dbm), IR (db) CALIBRATED WITH P = dbm 45 IMAGE REJECTION 65 LO FEEDTHROUGH TEMPERATURE ( C) 558 F8 Figure 8. LO Feedthrough and Image Rejection vs Temperature after Calibration at 25 C 4

15 APPLIC S I FOR P, LO FT (dbm), IR (dbc) P LO FT T A = C T A = 85 C T A = 25 C I AND Q BASEBAND VOLTAGE (V P-P, DIFF ) Figure 9. Image Rejection and LO Feedthrough vs Baseband Drive Voltage After Calibration at 25 C and V BBI =.2V P-P, DIFF IR f BBI = 2MHz, f BBQ = 2MHz, 9 P LO = dbm f = f BB + f LO f LO = 2.4GHz = 5V EN = HIGH 558 F9 HD2, HD3 (dbc) T A = C T A = 85 C T A = 25 C I AND Q BASEBAND VOLTAGE (V P-P, DIFF, EACH TONE ) IM3 IM2 Figure 2. Two-Tone Power, IM2 and IM3 at 24MHz vs Baseband Voltage f BBI = 2MHz, 2.MHz, f BBQ = 2MHz, 2.MHz, 9 P LO = dbm f = f BB + f LO f LO = 2.4GHz IM2 = POWER AT f LO + 4.MHz IM3 = MAX POWER AT f LO +.9MHz or f LO + 2.2MHz = 5V EN = HIGH 558 F2 PACKAGE DESCRIPTIO U UF Package 6-Lead Plastic QFN (4mm 4mm) (Reference LTC DWG # ) 4.35 ± ± ±.5 (4 SIDES).72 ±.5 NOTE:. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-22 VARIN (WGGC) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED.5mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN LOCN ON THE TOP AND BOTTOM OF PACKAGE PACKAGE OUTLINE.3 ±.5.65 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS BOTTOM VIEW EXPOSED PAD 4. ±..75 ±.5 R =.5 (4 SIDES) TYP 5 6 PIN TOP MARK (NOTE 6) 2.5 ±. (4-SIDES) PIN NOTCH R =.2 TYP OR CHAMFER.55 ± REF..5 Information furnished by Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. (UF6) QFN -4.3 ±.5.65 BSC 5

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