Experimental Results for Slow Speed Testing. Experimental Results for Slow Speed Testing. Chao-Wen Tseng

Transcription

1 enter for Reliable omputing Experimental Results for Slow Speed Testing hao-wen Tseng enter for Reliable omputing, Stanford University Outline Problem Definition Introduction Test hip Experiments Results Summary 2 hao-wen Tseng Page Nov., 2

2 Problem Definition chieve Good Test Quality Without Expensive Test Equipments Experimental Results Slow Speed Testing Nominal voltage Low voltage IDDQ Testing 3 Outline Problem Definition Introduction Test hip Experiments Results Summary 4 hao-wen Tseng Page 2 Nov., 2

3 Test Quality Test Patterns Test onditions Voltage Temperature Speed Introductions Test Patterns Metric Stuck-at Fault overage N-detect overage TRO overage omparison Experiments Murphy [Mcluskey ] [Li ] [Tseng ] ELF3 ELF3 Sematech [Nigh 7] 6 hao-wen Tseng Page 3 Nov., 2

4 Test onditions Voltage Very-Low-Voltage [Hong 3][hang 6][Tseng ] Reliability Defects Timing Defects Hard Failures SHOVE [hang 7] Reliability Defect Defective Oxides Timing Defects Resistive Vias 7 Test onditions Temperature Temperature oefficient (T) Defects Low Temperature Testing Silicide Opens [Tseng ] Resistance Negative T Low temperature Higher Resistance Timing Failures MINVDD Outliers hao-wen Tseng Page 4 Nov., 2

5 Speed Full-speed Testing Timing Failures Test onditions Resistive Opens [Li ] Expensive Tester Slow Speed Testing More escapes How much?? Outline Problem Definition Introduction Test hip Experiments Results Summary hao-wen Tseng Page Nov., 2

6 Murphy hip LSI Logic k MOS Gate rray (with rosscheck embedded array) 2k gate design 2-pin eramic PG package 6 signal pins L eff =.7µm Normal VDD = V Murphy hip Special purpose chip design different combinational circuit designs 3 control logic designs 2 data path designs 4 copies of each UT Support (DFT) circuitry 2 hao-wen Tseng Page 6 Nov., 2

7 ELF 3 hip LSI Logic GP technology L eff =.3µm 264k gates 272-pin Plastic BG package 3.3V Normal VDD 6 UT designs 2 sequential (2 s) with full scan 4 combinational translator, 3 data path 3 Outlines Problem Definition Introduction Test hip Experiments Results Test Speed Test Patterns Summary 4 hao-wen Tseng Page 7 Nov., 2

8 Failed Speed hip Failed Different Test Sets % SSF SSF N-detect % Transition TRO Different Voltages NV VLV Test Speeds Murphy SSF TRNSITION Others TRO omments E E s@ (NND) 2 E E E s@ (NND) 3 E s@ (NOR) 4 E s@ (NOR) E E s@ (NOT) 6 E E s@ (ND) 7 E E s@ (NOR) E E E E s@ (OR) E E E E E E E E E E 2 E E E 3 E E E 6 hao-wen Tseng Page Nov., 2

9 Murphy (ont.) SSF TRNSITION TRO omments STDE E E E E E E E E E VLV Fail all 2 E E VLV Fail all TDE 3 E E 4 E E R.O. (NOT) E E E E E E E E 2 E E SDE 3 E 4 E E E E E E E E E E E E E 6 E E E E S.O (NOR) 7 E E E S.O (NOR) E E E E E S.O (NND) 7 Murphy Penalty % full speed Fault Model Tool overage SSF Penalty TR T R O hao-wen Tseng Page Nov., 2

10 Slow Speed Testing 3 escapes Murphy (ont.) TDE-, TDE-2, TDE-4 6 dpm Defect Level Other chips Failed Very slow speeds (3% of the full speed) Murphy (cont.) VLV & IDDQ Detect 2 more chips TDE-, TDE-2 UT Name Murphy Failed test speed at nominal voltage VLV testing % full speed IDDQ testing TDD- % FIL PSS TDE-2 % FIL FIL TDE-4 % PSS PSS 2 hao-wen Tseng Page Nov., 2

11 ELF3, ombinational Penalty % full speed Fault model SSF D * TR Tool 6/7 ** 2 coverage 3 N penalty * D path delay test set, fault coverage is not available ** N-detect test sets (tool 7 for PB, tool 6 for the others) 2 Penalty % full speed Fault model Tool coverage ELF3, Sequential SSF 4 * S E Q TR penalty 3 * is an academic sequential TPG tool, fault coverage not available 22 hao-wen Tseng Page Nov., 2

12 Fault Models overage Test Patterns 23 Fault Model Tool 2 Murphy 3 overage % Speed % % % % % *N-detect test sets 24 SSF TR T R O hao-wen Tseng Page 2 Nov., 2

13 Test Patterns: Murphy (ont.) % slower 3 escapes % fewer coverage 3 escapes Murphy Full Speed, % overage 2 % Speed, % overage Full Speed, % overage 2 Summary Slow Speed Testing Test escapes Not much Reduce Escapes Slow speed NV and VLV IDDQ Speed vs. overage overage more important 26 hao-wen Tseng Page 3 Nov., 2