Design for Test for Digital ICs and Embedded Core Systems. Digital System Testing and Testable Design
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1 Books A. Crouch. Design for Test for Digital ICs and Embedded Core Systems Prentice Hall, M. Abramovici, M. Breuer, A. Friedman. Digital System Testing and Testable Design Computer Science Press, A.J. van der Goor. Testing Semiconductor Memories: Theory and Practice John Wiley and Sons, K.P. Parker. The Boundary-Scan Handbook Kluwer Academic Publishers, J. Rajski, J. Tyszer. Arithmetic Built-In Self-Test For Embedded Systems Prentice Hall, Magazines and Journals IEEE Design and Test of Computers IEEE Transactions on CAD IEEE Transactions on Computers Journal of Electronic Testing (JETTA)
2 Conferences and Workshops Conferences/Tutorials International Test Conference (ITC) Design Automation Conference (DAC) European Design and Test Conference VLSI Test Symposium (VTS) Workshops Testing Embedded Core-based Systems Memory Technology, Design, and Testing DFT and BIST Workshops Test Synthesis Workshop Additional Literature International Technology Roadmap for Semiconductors ASIC vendors reference manuals and web pages EDA vendor reference manuals and web pages Patent descriptions and US Patent and Trademark Office web site There are many patents in DFT!
3 References M. Abramovici. DFT Techniques: A Comparative Analysis. Tutorial, International Test Conference V. Agrawal, and A. K. Majhi. Tutorial: Delay Fault Models and Coverage. In Proc. International Conference on VLSI Design, pages P. Harrod. Testing Reusable IP A Case Study. In Proc. International Test Conference 1999, pages IEEE P1500 SECT. P1500 General Information. A. Kinra, A. Mehta, N. Smith, J. Mitchell, and F. Valente. Diagnostic Techniques for the UltraSPARC Microprocessors. In Proc International Test Conference, pages A. Kinra. Towards Reducing Functional Only Fails for the UltraSPARC Microprocessors. In Proc International Test Conference, pages M. Lousberg et.al. P1500 s Core Test Language. S. Ma, I. Shaik, R. S. Fetherston. A Comparison of Bridging Fault Simulation Methods. In Proc. International Test Conference 1999, pages E. Marinissen, Y. Zorian, R. Kapur, T. Taylor, L. Whetsel. Towards
4 a Standard for Embedded Core Test: An Example. In Proc. International Test Conference 1999, pages E. Marinissen, R. Kapur, Y. Zorian. On Using IEEE P1500 SECT for Test Plug-n-Play. In Proc. International Test Conference 2000, pages E. Marinissen, S. Goel, M. Lousberg. Wrapper Design for Embedded Core Test. In Proc. International Test Conference 2000, pages P.C. Maxwell, R.C. Aitken, K.R. Kollitz, A.C. Brown. IDDQ and AC scan: the war against unmodelled defects. In Proc. International Test Conference 1996, pages P. Nigh, W. Needham, K. Butler, P. Maxwell, R. Aitken. An Experimental Study Comparing the Relative Effectiveness of Functional, Scan, IDDq and Delay-fault Testing. In Proc. VLSI Test Symposium 1997, pages P. Nigh, W. Needham, K. Butler, P. Maxwell, R. Aitken, W Maly. So what is an optimal test miz? A discussion of the Sematech methods experiment. In Proc. International Test Conference 1997, pages P. Nigh, D. Vallett, A. Patel, J. Wright, F. Motika, D. Forlenza, R. Kurtulik, and W. Chong. Failure Analysis of Timing and IDDq-only Failures from the SEMATECH Test Methods Experiments. In Proc.
5 International Test Conference 1998, pages R. Rajsuman. Testing a System-On-a-Chip with Embedded Microprocessor. In Proc. International Test Conference 1999, pages M. Ricchetti. Overview of Proposed IEEE P1500 Scaleable Architecture for Testing Embedded Cores. D. Ross, T. Wood, D. Giles. Conversion of Small Functional Test Sets of Nonscan Blocks to Scan Patterns. In Proc. International Test Conference, 2000, pages T. Shinogi, T.Hayashi. A Simple and Efficient Method for Generating Compact IDDQ Test Set for Bridging Faults. In Proc 1998 VLSI Test Symposium, pages N. Tamarapalli, and J Rajski. Constructive multi-phase test point insertion for scan-based BIST. In Proc. International Test Conference 1996, pages T. Aruna Unni, D.M.H. Walker. Model-Based I DDQ Pass/Fail Limit Setting. In Proc IEEE International Workshop on IDDQ testing, pages VSI Alliance. VSI Alliance Architecture Document. K.D. Wagner. Robust scan-based logic test in VDSM technologies.
6 Computer, Volume 32, Issue 11, November Pages T.W. Williams, et.al. Iddq Test: Sensitivity Analysis of Scaling. In Proc International Test Conference, pages Y. Zorian, E. Marinissen, S. Dey. Testing Embedded-Core Based System Chips. In Proc International Test Conference 1998, pages
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