A Clustering Method for i DDT -Based Testing

Transcription

1 A Clustering Method for i DDT -Based Testing Ali Chehab ECE Department American University of Beirut P.O.Box Beirut, Lebanon chehab@aub.edu.lb Rafic Makki and Saurabh Patel ECE Department University of North Carolina at Charlotte Charlotte, North Carolina 28223, U.S.A makki@uncc.edu Abstract This paper presents a test method that can allow the scaling of some i DDT -based testing methods to test larger circuits. The method uses a clustering technique that organizes the gates in the circuit under test into different clusters in a way that controls the switching activity and disciplines i DDT. The individual i DDT responses can be monitored on a cluster-by-cluster basis. We describe the software implementation of the clustering technique and qualify its application on the ISCAS 85 benchmark circuits. We present fault simulation results on selected benchmark circuits as well as physical test results. 1. Introduction Current-based test methods may improve the test quality and coverage when used to augment traditional voltage-based test methods [1]. The current-based techniques include variations to the single-threshold I DDQ method [2]-[10], and include the transient or dynamic current, i DDT, test methods [11]-[19]. Some i DDT -based techniques, such as the Double Threshold technique [19] that is based on monitoring the peak value of i DDT, require a set of test vector-pairs that will attempt to activate every net in the circuit. The Double Threshold method establishes upper and lower bounds on i DDT for a good circuit in response to a fixed test set composed of a predetermined number of test vector pairs. These bounds are established for specific test pattern sets that switch circuit nodes for the purpose of detecting defects using i DDT. The defect detection capability of such a technique decreases as the circuit size increases. This is due to the fact that, as the number of switching components increases, the relative contribution of a single component to the overall i DDT pulse decreases. Thus, it would be very difficult to account for one faulty component among a sea of switching components. This is one of the principal reasons that limits the effectiveness of i DDT testing in random logic gates. However, this technique can detect defects that are difficult to detect by traditional tests [17]. Thus, it can be employed for select locations on a chip to improve detection capability, even though it may not be practical to use on the entire chip. Clearly, the test method is not intended to be a standalone test method, but its defect detection capability can be significantly enhanced by controlling the number of switching components in response to a test vector set. Indeed, such control can improve the detection capability of most i DDT test methods because the relative contribution of a single faulty component becomes greater. In other words, we need to reduce and keep almost constant the switching activity in the circuit under test as we apply the test vector-pairs. The proposed clustering method is driven by the ATPG-produced test vector pairs. The ATPG is presented in [20] and it is briefly reviewed in the next section. In section 3, we describe the clustering algorithm and its software implementation, and then in section 4 we show the clustering results when applied to the ISCAS 85 benchmark circuits. In section 5 we present the fault simulation results and show the postclustering improvement of an i DDT -based test method. In section 6 we present physical test results and finally, we conclude the paper in section Review of ATPG for i DDT -based Test The ATPG is presented in [20] and it is briefly described below for convenience. The ATPG generates a set of test vectors based on the following criteria: Each test vector consists of a pair of two vectors, the application of which will activate at least one net in the circuit. One vector will set the target-net to a logic value of 1/0 while the second vector will set the same net to a logic value of 0/1.

2 While targeting a specific net, a test vector-pair should be chosen in a way that minimizes the number of the switching gates in the circuit. This condition is important to minimize the peak value of i DDT, which will allow for the distinction between the peak i DDT values of a defective circuit and a fault-free circuit. The vector set should activate every net in the circuit to maximize the fault coverage, yet it should contain a minimum possible number of input vectors to minimize the test length. The ATPG selects a minimum set of paths covering all the nets in the circuit. Then, for every selected path, it generates a test vector-pair that sensitizes this path. The resulting vector-pair will be retained as part of the i DDT test set only if it is unique. When applied to the C432 benchmark circuit, for example, the ATPG resulted in 79 vector-pairs. 3. Clustering Methodology Controlling the switching activities of a CUT (Circuit Under Test) in response to test vectors is a key factor for the improvement of the detection capability of i DDT -based test methods. We need to minimize and keep almost constant the switching activity in the CUT as we apply the test vector-pairs. Hence, we need to: ƒ Reduce the number of gates that switch in response to test vectors ƒ Reduce the number of i DDT spikes per transition ƒ Reduce the variations of the peak i DDT values among all test vectors. One way to achieve these objectives is to organize the gates in the circuit into different clusters. The main power supply will have different branches, one per cluster. This is not to say that there will be a separate V DD supply pad for each cluster, but that each cluster receives its supply from a separate branch coming from the chip V DD supply pad. All the gates in the same cluster will share the same power supply branch. The i DDT response from each cluster can be monitored separately. When a test vector is applied to the CUT, the switching activity will be spread among the various clusters and it will impact the different clusters differently. The gates will be grouped in a way such that the maximum number of switching gates in one cluster, in response to the vector-pairs, does not exceed a specific parameterized value. Note that for every subset of gates belonging to the same cluster, there corresponds a subset of vectorpairs, among the space of the total test vectors generated by the ATPG, that will be used to test the gates in this cluster We can then monitor the individual i DDT response on a cluster-by-cluster basis. The parameterized value will be chosen depending on the resolution of the current monitoring technique. The following is a description of the proposed clustering technique. First, we apply the ATPG-generated test vectors to the defect-free circuit. For every vector-pair we record the specific nets in the circuit which switched in response to this vector pair and we store the switching information in a 2-dimensional array. For a circuit with N gates and for which the ATPG produced M vector-pairs, the dimensions of the array are MxN. Every element, E ij in the array is set to 1 if vector-pair V i switches any input in gate G j, and set to 0 otherwise. The range of subscript i is [1 to M], and the range of subscript j is [1 to N]. After running all the vector-pairs on the CUT and checking the switching gate-inputs, the array would be similar to the one shown in table 1. Table 1. Vectors and Switching-Gates Relationship G 1 G 2 G 3 G N-1 G N V V V M V M Second, we start grouping the gates into different clusters based on the criterion that the number of switching gates in a cluster, in response to any vectorpair in the corresponding subset of vector-pairs, does not exceed a preset maximum value. The pseudo-code description of the clustering algorithm is shown below: While the set of un-clustered gates is not empty Generate a new cluster, C x For every un-clustered gate, G i Compute the maximum number of switching gates for the cluster C x when G i is added to it If this maximum <= allowed maximum number Add the gate to the cluster Remove G i from the set of un-clustered gates End of for loop End of while loop

3 In order to compute the maximum number of switching gates for a cluster C x, when a gate G i is added to it, we look up the switching information from the 2- dimensional array. For every test vector-pair, we count the total number of switching gates that belong to Cx, and we select the maximum out of these numbers. A pseudo-code that describes this operation is shown below. Initialize max_switch_gates to 0 For every vector-pair, V j If the vector switches G i Initialize switch_counter to 1 For every gate, G k in C x If V j switches G k Increment switch_counter End if End for loop If switch_counter > max_switch_gates Set max_switch_gates = switch_counter End if End if End for loop Return max_switch_gates 4. Clustering Results The clustering algorithm was implemented in software using the C++ programming language. The program was first tested on the C432 circuit and the results for different parameter values of maximum switching gates per cluster are shown in Table 2. The first column indicates the maximum number of allowed switching gates per cluster. The second column shows the total number of clusters formed, and the third column shows the number of gates in every cluster. Table 2. Clustering Results on C432. SG #C Number of Gates in Each of the Various Clusters Note that the number of gates in the various clusters is not balanced. This is due to the way in which the algorithm was implemented, where gates will be added to a cluster as long as the number of switching gates in this cluster does not exceed the maximum allowed value. However, it is possible to make use of the clustering algorithm in order to obtain a more balanced set of clusters whereby all the clusters will have more or less the same number of gates. This is definitely preferable from a layout perspective and to achieve a uniform sizing for the power supply branches feeding the various clusters. One possible way to achieve this objective is to use the clustering algorithm in an iterative manner as follows: Step 1: Run the clustering algorithm based only on the constraint that the maximum number of switching gates in every cluster should not exceed a predefined value. Let N be the resulting number of clusters. This will give us an estimate of the number of gates per cluster, say M, being equal to the total number of gates divided by N. Step 2: Run the clustering algorithm with an additional constraint whereby the total number of gates in a cluster should not exceed the average value M Step 3: If the number of resulting clusters is much greater than N, increment the value of M and go to step 2. Otherwise stop. These iterations will lead to a number of clusters approximately = N, except that the clusters will be more balanced. When we applied this modified technique to the C432 circuit, we obtained a more balanced number of gates per cluster, an example of which is shown in Table 3, where the second column indicates the maximum number of allowed gates per cluster. The first and third rows in Table 3 show the unbalanced clusters, and the second and fourth rows show the balanced clusters. We can see that with the addition of a maximum of 1 cluster we can obtain better balanced clusters in terms of the number of gates per cluster. A graph illustrating the relationship between the maximum number of switching gates per cluster and the resulting number of clusters for the C432 circuit is shown in Figure 1. The graph shows that we can obtain a relatively small number of clusters without requiring a very low value of switching gates per cluster.

4 Table 3. Balanced Versus Unbalanced Clustering for C432. SG AC #C Number of Gates in Each of the Various Clusters Number of Clusters Clustering Algorithm Maximum Switching Gates Figure 1. Clustering results for C432 We have also applied the clustering technique to the ISCAS 85 C880, C3540, C5315 and C7552 circuits. We applied the technique with different numbers of switching gates and maximum number of gates per cluster. A sample of the results is shown in Table 4, where the first column identifies the ISCAS circuit number. The first two rows show how the clustering results vary for different constraints on the number of switching gates for the C880. The next two rows show the same for the C3540 and so on. 5. Clustering Assessment for i DDT -based Test In order to assess the effectiveness of the clustering technique we have applied the Double threshold i DDT testing method to the C432 and C880 benchmark circuits and we performed fault simulation with and without clustering. For the C432 circuit, the maximum number of switching gates per cluster was set to 10 resulting in 9 clusters. For the C880 circuit, the maximum number of switching gates was set to 15 resulting in 11 clusters. The fault simulation results were obtained using SPICE. The Spice models were created by utilizing parameters from the TSMC035 process. The fault models included opens and shorts. Table 4. Clustering results on ISCAS 85 circuits C SG AC #C # Gates in the Various Clusters A 1MΩ resistive open was used to model cracks, as they would insert delays in the circuit and not necessarily cause a catastrophic failure on the signal. These defects were placed on interconnects, and on transistor-level nodes within logic gates. Bridging faults were modeled with a 10Ω resistor connecting two nodes. The results show an improvement in the detection capability of the testing technique for the post-clustered circuits. These results are shown in Table 5. Table 5. Pre/Post clustering detection comparison C432 Fault Coverage C880 Fault Coverage Pre-Clustering 57.90% 30.23% Post-Clustering 92.00% 91.86% 6. Physical Test Results The clustering algorithm was applied to ISCAS 85 benchmark C432. The largest cluster was selected for implementation using the CMOS AMI 0.5-micron process. This cluster has 70 gates with a maximum of 23

5 gates switching for any of the input vectors generated by the algorithm. Two chips were fabricated containing one defect free version of the cluster and one with built-in defects. Table 6 shows the defect profile. Table 6. Summary of inserted defects Defect Defect Type and Placement 1 Pull-up drain open 2 Pull-down drain open 3 Line short (in Metal1) These defects were inserted in a way such that each would be excited by a unique vector set. Figure 2 shows the layout of the defect-free chip. All PFETs within the cluster were sized to 10λ 2λ and the NFETs were sized to 5λ 2λ.. Test Set-up For testing the fabricated chips, a Tektronix TLA720 Pattern Generator was used to supply test patterns to the circuit under test. The circuit response was monitored on a Tektronix TDS6604 Digital Storage Oscilloscope. This oscilloscope has the capability to measure signals with a sampling rate of 20G samples/sec. The chips were fabricated through MOSIS. using Ohm s law. A 0.01µF bypass capacitor was used to minimize the power supply noise. Test Results Figure 3 shows the response of both the good and faulty chips, where the fault being excited is the line short listed in Table 6. Figure 3(a) shows a voltage drop which corresponds to an i DDT of 118µA. Figure 3(b) shows a voltage drop which corresponds to an i DDT of 196µA. It should be noted that the horizontal axis of Figure 3(a) is 80ns/square and that of figure 3(b) is 200ns/square. The vertical axes in both figures are 100 mv/square. Figure 3(a). Good Circuit Response. Figure 3(b). Defective Circuit Response. Figure 2: Layout of the defect-free chip The circuit under test was mounted on a custom PCB with a large ground plane to minimize ground bounce and lower the noise levels. To measure i DDT, a 1KΩ resistor was added in series to the power line. The voltage across the resistor was used for calculating i DDT Table 7 lists the good and bad i DDT results. Column 1 lists the test vector pair and targeted defects. The up arrow indicates a rising input transition. Columns two and three show the good circuit and bad circuit i DDT responses respectively. A positive value in column four indicates that the good circuit i DDT magnitude was higher than that of the bad circuit and a negative value indicates

6 the opposite. The average difference between the good and bad circuit i DDT responses was 29%. Chip Variances Tables 8 and 9 show a summary of the process variation data obtained from two chip copies of the good circuit and two chip copies of the bad circuit respectively. It can be seen that within the same wafer, process variations can be in excess of 32%. The average variation in the good chips was 11.33%. The average variation in the defective chips was 5.83%. Table 7. Physical Testing Results Good Bad Difference i DDT i DDT (%) Vector Set and Pulse (ua) (ua) Set 1 (detects defects 1 and 3) % Set 1 (detects defects 1 and 3) % Set 2 (detects defects 2 and 3) % Set 2 (detects defects 2 and 3) % Set 3 (detects defect 3) % Set 3 (detects defect 3) % 6. Conclusions A clustering technique and its software implementation were presented, whereby the gates in a CUT are organized into different clusters such that the switching activity is reduced and the i DDT response disciplined. It was shown that this technique can be used with i DDT -based testing methods to improve their detection capability and scale up the test method to larger circuits. The results of the application of the clustering technique to the ISCAS 85 benchmark circuits were presented. We also showed the improvement of the detection capability of an i DDT test method, after clustering, when performing fault simulations on benchmark circuits. It should be noted that the clustering method is based on the availability of an on-chip sensor that can be multiplexed and used to monitor more than one cluster. Such a sensor is the subject of a utility patent [21]. 7. Acknowledgements This project was partially funded by the National Science Foundation (CCR ) and by DARPA Neo-CAD. Table 8. Defect-free i DDT Circuit Variations (PA). GOOD CHIPS iddt (uamps) VECTOR SET CHIP 1 CHIP 2 DEVIATION Rising edge of Set % Falling edge of Set % Rising edge of Set % Falling edge of Set % Rising edge of Set % Falling edge of Set % Table 9. Defective i DDT Circuit Variations in (PA). DEFECTIVE CHIPS iddt (uamps) VECTOR SET CHIP 1 CHIP 2 DEVIATION Rising edge of Set % Falling edge of Set % Rising edge of Set % Falling edge of Set % Rising edge of Set % Falling edge of Set % 8. References [1] M. Sachdev, Current-Based Testing for Deep-Submicron VLSIs, IEEE Design & Test of Computers, March-April 2001, pp [2] C. Thibeault, An Histogram Based Procedure for Current Testing of Active Defects, Int. Test Conf., 1999, pp [3] A. C. Miller, IDDQ Testing in Deep Submicron Integrated Circuits, Int. Test Conf., 1999, pp [4] K. Baker, SIA Roadmaps: Sunset Boulevard for IDDQ, Int. Test Conf., 1999, p [5] D. Bhavsar, ITC99 Panels, IEEE Design & Test, vol. 16, no. 4, Oct.-Dec. 1999, pp [6] C. F. Hawkins, J.M. Soden, Deep Submicron CMOS Current IC Testing: Is There a Future? IEEE Design & Test, vol. 16, no. 4, Oct.-Dec. 1999, pp [7] M. Sachdev, Deep Submicron IDDQ Testing: Issues and Solutions, Proc. European Design & Test Conf. (ED&TC 97), IEEE CS Press, Los Alamitos, Calif., 1997, pp [8] A. Keshavarzi, K. Roy, and C.F. Hawkins, Intrinsic Leakage in Low-Power Deep Submicron CMOS ICs, Proc.

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