Practical Fault Coverage of Supply Current Tests for Bipolar ICs

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1 Practical Coverage Supply Current Tests for Bipolar ICs Isao Tsukimoto, Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada Dept. Electronic Engineering, Takuma National College Technology Dept. Electrical and Electronic Engineering, Faculty Engineering, Univ. Tokushima Abstract Bipolar logic circuits are indispensable for implementing high-speed logic circuits. Since quiescent supply current flows into the circuits without faults, they can not be ed by a conventional IDDQ method. We proposed a quiescent supply current method which is applicable for the bipolar circuit s, and examined the ability open faults under an ideal assumption that there are not any process variations. Actually, there are some variations in the quiescent supply current each gate in implemented logic circuits. Thus, It is necessary to examine the practical ability the method before applying to production s bipolar logic ICs. In this paper, the practical ability obtained under an assumption that there are some unitto-unit variations supply current among gates is examined for ISCAS- benchmark circuits. experimental results show that larger fault can be obtained with a smaller input by our supply current method than the functional one based on stuck-at fault models.. Introduction It has been shown that quiescent supply current s logic circuits are indispensable for realizing high reliable logic systems [,2,3]. Especially, I DDQ ing is very effective in CMOS logic IC s. Also, input generation algorithms for the I DDQ ing have been proposed. In a fault-free CMOS IC, very small quiescent supply current will be generated in operation. If large quiescent supply current is generated, the circuit can be determined as faulty. I DDQ ing can detect physical defects, which can not be modeled as logical faults and is effective for realizing high reliable systems. Besides CMOS circuits, bipolar circuits like TT and EC circuits are ten used now for implementing logical systems. Especially, they are used in the electronic equipments which are required a high-speed operation and used as a core in logic system. If they do not work, the generated damage will be extremely large. Thus, very high reliability is requested for bipolar circuits. Quiescent supply current unfaulty bipolar gates depends on the output logic values [3]. Thus, even if any defects do not occur in a bipolar circuit, quiescent supply current flows from the VCC terminal to the GND terminal. It means that I DDQ technique for CMOS circuits is not applicable to fault detection problems bipolar ones. In order to detect faults in bipolar circuits with their quiescent supply currents, a new fault detection method should be developed. Thus, in the past, we proposed a supply current method for bipolar circuits [3]. method is to detect faults by measuring the quiescent supply current a circuit under and comparing it with one the unfaulty circuit. Also, we proposed a fast random input generation method for the supply current s and an algorithmic one in [4] and [5], respectively. re are some variations in the quiescent supply current each gate in implemented logic circuits. Thus, we proposed a method which is applicable even if there are some variations among gates [6]. In the past, we examined practical fault the supply current method for open faults in TT combinational circuits made TT S-type SSIs on printed-circuit-board, since open faults ten occur in logic circuits fabricated with the state--art technology [7]. results show that more open faults can be detected by the supply current method than functional ones based on stack-at fault models. However, fault supply current s for a bipolar logic circuit implemented in an IC has not been examined. Most the faults in the circuits fabricated with the state--art technologies are open faults any signal line and bridging ones between any signal lines. Testing bridging faults are easier than one open faults, since extremely large supply current change will appear by exciting bridging faults. Thus, most bridging faults can be easily detected by supply current ing. On the other hand, in the case open faults, large supply current change will not always appear even if they are excited. Thus, it is very difficult to detect open faults than

2 bridging faults. Thus, in this paper, the fault our supply current method for only open faults signal lines in bipolar IC is discussed. Our supply current method is introduced in section 2. After that, our ability analysis method and the obtained results are described in section Supply current method for bipolar logic circuit Even if any defects do not occur in a bipolar logic circuit, quiescent supply current flows from the VCC terminal to the GND terminal in each gates. Thus, the quiescent supply current I CCN (T j ) an unfaulty bipolar circuit with Ns gates which flows when the j-th input vector is applied to the circuit can be defined by Eq.(), I CCQN NS ( = ICCQNi( () i= where I CCQNi (T j ) is the quiescent supply current the i-th bipolar gate flowing when T j is provided to the unfaulty circuit. Also, quiescent supply current I CCQC (T j ) a circuit under, CUT, can be defined by Eq.(2), I CCQC NS ( = ICCQCi( (2) i= where I CCQCi (T j ) is the quiescent supply current the i-th bipolar gate in the CUT flowing by applying T j. If Eq.(3) is satisfied, the CUT is determined as faulty, ICCQ( Ith (3) where I CCQ (T j ) is defined by Eq.(4) and I th is the threshold value to determine whether the CUT is faulty or not. ICCQ( = IDDQC( IDDQN( (4) When an open fault is excited by the input vector Tj, any large quiescent supply current change will not be generated in the gate having the open fault at the output signal line. However, the supply current gate whose output logic value is changed by the fault propagation changes, since quiescent supply current unfaulty bipolar gates depends on the output logic values [3]. Thus, I CCQ (T j ) appears by the supply current changes gates whose output logic values are changed by the fault propagation. A set such gates is called Sg in this paper. I CCQ (T j ) can be obtained by Eq.(5), I CCQ( = Ii( (5) i Sg where I i (T j ) is quiescent supply current change the i-th gate which is generated when T j is provided to the circuit. I i (T j ) is defined by Eq.(6), Ii IiH, the output the i - th gate is changed from H to I i ( T j ) = (6) IiH Ii, the output the i - th gate is changed from to H where I i and I ih are quiescent supply currents i-th bipolar gate when the output logic value is and when it is H, respectively. example effects generated to supply current change by open fault is shown in Figure. In TT logic circuit, open faults are modeled as stuck-at- faults under assumption positive logic. In this example, gates whose output logic values are changed are 2, 3 and 4. Thus, Sg is {2, 3, 4} and I CCQ (T j ) generated by open fault signal line a is obtained by Eq.(7). ICCQ = I ( + I ( + I ( (7) T j ( re are some variations in quiescent supply current among gates. generation process variations can be modeled as a Gaussian distribution process. Thus, we model the variation quiescent supply current at the i-th gate in unfaulty bipolar logic circuit as a Gaussian distribution N(µ Ni (T j ), σ Ni (T j ) 2 ), which is defined by Eq.(8), Pr ob( I Figure. Effects generated by open fault CCQNi ( ) = σ ( T ) Ni open j Vcc I CCQC(T j) Stuck-at- H H 2 a b 5 H e H I exp 2π 2 I CCQ(T j) 3 5 c 4 6 d Sg CCQNi 2 ( T j) µ Ni( σ ( ) Ni Tj where µ Ni (T j ) and σ Ni (T j ) 2 are the mean value and the variance quiescent supply current in the i-th gate which flows when a input vector (T j ) is provided to the unfaulty circuit, respectively. Generally, it will be assumed that the variations quiescent supply current gates in a circuit are independent each other. refore, the supply current variation the unfaulty circuit can be modeled as a (8)

Gaussian distribution N(µ N (T j ) +µ N2 (T j )+ +µ NNs (T j ), σ N (T j ) 2 +σ N2 (T j ) 2 +...+σ NNs (T j ) 2 ), whose example is shown in Figure 2.

3 Gaussian distribution N(µ N (T j ) +µ N2 (T j )+ +µ NNs (T j ), σ N (T j ) 2 +σ N2 (T j ) σ NNs (T j ) 2 ), whose example is shown in Figure 2. Similarly, the distribution quiescent supply current a faulty circuit can be modeled as a Gaussian distribution. If the distributions I CCQN (T j ) and I CCQC (T j ) are separated each other, it can be judged without any errors whether the circuit is faulty. However, if they are 3. Testability analysis In order to evaluate the ability our supply current method for open faults signal lines in bipolar logic ICs, input are generated for ISCAS- benchmark circuits made the standard gates, which are shown in Table and Table 2. As circuit under (CUT), C8, C8, C35 and C535 are used in our ability analysis, whose specifications are shown in Table 3. Table. Quiescent supply current unfaulty -input TT gate Input INVERTER BUFFER X Z I CCQ [ma] Z I CCQ [ma] H H 0.6 H Figure 2. Examples distributions for unfaulty circuit and faulty one overlapped as shown in Figure 2, it is impossible to be judged without any errors whether the circuit is faulty. Thus, a statistical analysis method with level significance (α) is used in our method. That is, it is determined whether the CUT is faulty by checking whether any two distributions are separated each other statistically by means α. Test input our method are generated so that the distribution quiescent supply current a faulty circuit can be separated to the unfaulty one as shown in Figure 3 by introducing α [6]. Table 2. Quiescent supply current unfaulty 2-input gate Input AND NAND OR NOR X Y Z I CCQ [ma] Z I CCQ [ma] Z I CCQ [ma] Z I CCQ [ma].055 H H H.052 H 0.29 H H.052 H 0.29 H H H H H Table 3. Circuit under CUT PIs POs Signal ines Targeted Gates s C C C C analysis process the fault s in this evaluation is shown in Figure 4. At first, the quiescent supply current value each unfaulty gate is derived by DC analysis using SPICE. results are shown in Table and Table2. value obtained from this simulation is used as µ Νι, which is the mean value quiescent supply current in each gate. In the simulations, the internal electronic circuit TT S-type is used as one each gate. Figure 3. Criterion for selecting Tj as input vector

4 Gates used σ Ni each gate Netlist CUT DC analysis each gate Test input µ Ni each gate Test generation Target faults Significance level(α) s Figure 4. Analysis process fault s After that, the distribution supply current the circuit is derived from the distribution the supply current each gate in the CUT. With the distributions the unfaulty circuit and a circuit having an open fault, it is determined whether an input vector can be selected as a vector. In the past, we proposed a random generation algorithm [4] and a deterministic one [5] for the supply current s. In our experiments, input are derived by a modified random input generation method, which is almost the same as in [6]. Test input generation process is as follows. At first, an input vector is generated by using random s, and the output logic value each gate is determined by logical fault simulation. By using the values in Table. and Table 2 as the mean value quiescent supply current each gate and specifying the variation the distribution, a Gaussian distribution is derived, whose example is as shown in Figure 3. If the distribution quiescent supply current faulty circuit can be separated to the unfaulty one by specifying α, the input vector is employed as a input vector for detecting the fault. If any open faults can not be detected by the last 50 input generated by random s, the input generation process is terminated. results are shown in Table 4. Since experimental results depend on generated random s, 0 experiments per the variance supply current gates have been performed. average values are denoted in Table 4. In our experiments, the level significance (α) is assumed to be 0.. Also, we assume that the variance a gate is the same as the other gates in a bipolar logic circuit. We specify the variance quiescent supply current in each gate as the percentage to the nominal quiescent supply current each unfaulty gate. Table 4. Experimental results C8 C8 C35 Functional Testing σ/µ Supply Current Testing C535

5 obtained fault s C8 are plotted in Figure 5. As shown in Figure 5, the depends on the variation supply current. fault functional ing for C8 is 96.3 and the is.2. As shown in Figure 5, larger fault can be obtained with a smaller by our supply current method than the functional one, if the variance supply current each gate is smaller than 0.9. obtained fault s other CUTs are plotted in from Figure 6 to Figure 8. In the case these CUTs, almost the same results can be obtained as C8. fault depends on the variation supply current like in C8. As shown in Table 4, the fault functional ing for C8, C35 and C535 is respectively 94.3, 93.3 and 98.4, and the functional ing for C8, C35 and C535 is respectively 39.5, 9.8 and.0. As shown in from Figure 6 to Figure 8, if the variance is smaller than 0.7, 0.5 and 0.3 respectively for C8, C35 and C535, higher fault will be realized than the functional ing σ/µ Faut functional ing Figure 5. Obtained results for C8 σ/µ Faut functional ing Figure 7. Obtained results for C σ/µ Faut functional ing Figure 6. Obtained results for C8 σ/µ Faut functional ing Figure 8. Obtained results for C535

6 As the the gates in CUT increases, fault will become small as shown in the figures. That is the reason why the distribution quiescent supply current in a faulty circuit overlaps strongly to the one unfaluty one. By dividing CUT into circuit blocks and measuring supply current each circuit block instead the total circuit, the distribution in the faulty circuit will be separated from the one unfaulty one. Thus, as for the s large-scale bipolar circuits, our method should be applied to each circuit block, whose size is smaller than the total circuit. If a circuit block is determined as faulty by our method, the CUT is determined as faulty by using our method. According to the methodology, large size circuits will be ed by our method with high fault regardless the extent process variation. [5]T.Kuchii,M.Hashizume et.al : "Algorithmic Test Generation for Supply Current Testing TT Combination Circuits", Proc. od the IEEE Fifth Asian Test Symp., pp7-76(996) [6]M.Hashizume. et al : "Supply Current Test for Unit-to-Unit Variation Electrical Caracteristics in Gates", Proc. the IEEE Sixth Asian Test Symp., pp (997) [7]Y.Mushiaki, M.Hashizume, et al: "Practical Coverage Supply Current Testing for Open s in TT Combinational Circuits", Proc. ITC-CSCC'00, pp (2000) 4. Conclusion In this paper, fault our quiescent supply current method is examined for bipolar logic circuits implemented inside ICs. In this examination, it is assumed that there are some variations electrical characteristics in bipolar circuits. experimental results show that even if there are process variations, larger fault open faults can be obtained by our supply current method than functional one. Supply current is time-consuming. Thus, all faults should not be detected by the supply current method. On the other hand, faulty effects generated by fault excitation need not to be propagated to any primary output terminals in the supply current s. Thus, it is easy for input the supply current method to be generated. Hence, only the faults which are difficult to be detected by functional s based on stuck-at fault models should be detected by the supply current method. It is a future work to examine the ability for the faults which are difficult to be detected by the functional method. References []S.D.McEuen : "IDDq benefits",proc. IEEE VSI Test Symp., pp.2-2(99) [2]R.R.Fritzemeier, J.M.Soden, K.R.Treece and C.F.Hawkins : "Increased CMOS IC Stuck-at fault Coverage with Reduced IDDQ Test Sets", Proc. Int. Test Conf.,pp (9). [3]M.Hasizume et al.:" Detection Combinational Circuits Based on Supply Current ", Proc. Int. Test Conf., pp374-3(998). [4]M.Hashizume et.al : "Test Input Vectors for Supply Current Testing TT Combinational Circuits", Proc. the First IEEE Asian Test Symp., pp58 69(992)

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