Application Note AN-1125

Transcription

1 Application Note AN- IRS(7,8,7) and IR(7,8,7) Comparison By Jason Nguyen, Fang, David New Table of Contents Page Introduction... Block Diagram... Electrical Characteristic Differences... Figures... Summary... Introduction The IRS(7,8,7) are new HVIC products that replace the IR(7,8,7) and are pin-topin compatible with their corresponding predecessors. In many cases, little or no change is necessary to use the new products. This application note describes the various differences between the IRS(7,8,7) and the IR(7,8,7) HVICs. The IRS(7,8,7) are high voltage, high speed power MOSFET and IGBT drivers. Proprietary HVIC and latch immune CMOS technologies enable ruggedized monolithic construction. The logic input is compatible with standard CMOS or LSTTL outputs, down to. V. The protection circuitry detects over-current in the driven power transistor and terminates the gate drive voltage. An open drain FAULT signal is provided to indicate that an over-current shutdown has occurred. The output driver features a high pulse current buffer stage designed for minimum cross-conduction. The floating channel can be used to drive an N-channel power MOSFET or IGBT in the high-side or low-side configuration which operates up to V. AN-

2 Block Diagram (7,7) 8 The IRS(7,8,7) and IR(7,8,7) share the same block diagram. functionality of the two ICs is the same. The Electrical Characteristic Differences All measurement conditions remain unchanged unless noted. Parameters not mentioned have not changed. AN-

3 Absolute imum Ratings There are no changes to the Absolute imum Ratings Recommended Operating Conditions There are no changes to the Recommended Operating Conditions. Dynamic Electrical Characteristics Parameter IR(7,8,7) IRS(7,8,7) Symbol Definition min typ max min typ max t on Turn-on propagation delay - - Units t off Turn-off propagation delay - - t bl Start-up blanking time ns t cs CS shutdown propagation delay - - t flt CS to FAULT pull-up propagation delay The IRS(7,8,7) has reduced in propagation delays and increased blanking time when compared to the IR(7,8,7). Static Electrical Characteristics Parameter IR(7,8,7) IRS(7,8,7) Symbol Definition min typ max min typ max V IH Logic "" input voltage (V CC = V to V) Units V IL Logic "" input voltage (V CC = V to V) V OH V OL High level output voltage, V BIAS - V O Io = ma Io = ma Low level output voltage, V O Io = ma Io = ma I QBS Quiescent V BS supply current (V IN = V or V) - - V I IN + Logic input bias current I IN - Logic input bias current ua I CS + "High" CS Bias Current I CS - "Low" CS Bias Current With the IRS(7,8,7),. V IH is decreased to. V for better. V logic compatibility.. I QBS has increase slightly.. The I IN-, I CS+, and I CS- has increased to better reflect tester capabilities.. The V OL and V OH are tested using a new standardized test condition of I O = ma. AN-

4 Figures This figures shown in this section compare figures shown in the IR(7,8,7) (left column) and IRS(7,8,7) (right column) datasheets. Illustrations that have not changed between the two datasheets have not been included in this section. IR(7,8,7) IRS(7,8,7) Turn-On Delay Time (ns) Figure A. Turn-On Delay Time vs. Turn-On Delay Time (ns) Figure A. Turn-On Delay Time vs. Turn-On Delay Time (ns) Turn-On Delay Time (ns) 8 Figure B. Turn-On Delay Time vs. 8 Figure B. Turn-On Delay Time vs. AN-

5 Start-Up Blanking Time (ns) Start-Up Blanking Time (ns) Figure A. Start-Up Blanking Time vs. Figure A. Start-Up Blanking Time vs. Start-Up Blanking Time (ns) 8 Start-Up Blanking Time (ns) Figure B. Start-Up Blanking Time vs. Figure B. Start-Up Blanking Time vs. CS Shutdown Prop. Delay (ns) CS Shutdown Prop. Delay (ns) Figure A. CS Shutdown Prop. Delay vs. Figure A. CS Shutdown Prop. Delay vs. AN-

6 CS Shutdown Prop. Delay (ns) CS Shutdown Prop. Delay (ns) 8 8 Figure B. CS Shutdown Prop. Delay vs. Figure B. CS Shutdown Prop. Delay vs. CS to FAULT Pull-Up Prop. Delay (ns) Figure A. CS to FAULT Pull-Up Prop. Delay vs. CS to FAULT Pull-Up Prop. Delay (ns) Figure A. CS to FAULT Pull-Up Prop. Delay vs. CS to FAULT Pull-Up Prop. Delay (ns) 8 CS to FAULT Pull-Up Prop. Delay (ns) 8 Figure B. CS to FAULT Pull-Up Prop. Figure B. CS to FAULT Pull-Up Prop. Delay vs. Delay vs. AN-

7 Logic "" ("" for 8) V IH Threshold (V) Logic "" ("" for 8) V IH Threshold (V) Figure A. Logic "" ("" for 8) V IH Threshold vs. Figure A. Logic "" ("" for 8) V IH Threshold vs. Logic "" ("" for 8) V IH Threshold (V) Logic "" ("" for 8) V IH Threshold (V)... 8 Figure B. Logic "" ("" for 8) V IH Threshold vs. Figure B. Logic "" ("" for 8) V IH Threshold vs. High Level Output (I O = ma) (V) High Level Output (I O = ma) (V) Figure A. High Level Output (I O = ma) vs. Figure A. High Level Output (I O = ma) vs. AN- 7

8 High Level Output (I O = ma) (V) High Level Output (I O = ma) (V) Figure B. High Level Output (I O = ma) vs. Figure B. High Level Output (I O = ma) vs. Low Level Output (I O = ma) (V) Low Level Output (I O = ma) (V) Figure 7A. Low Level Output (I O = ma) vs. Figure 7A. Low Level Output (I O = ma) vs. Low Level Output (I O = ma) (V) Low Level Output (I O = ma) (V) Figure 7B. Low Level Output (I O = ma) vs. Figure 7B. Low Level Output (I O = ma) vs. AN- 8

9 V BS Supply Current (μa) Figure 9A. V BS Supply Current vs. V BS Supply Current (μa) Figure 9A. V BS Supply Current vs. 7 V BS Supply Current (μa) V BS Supply Current (μa) 8 Figure 9B. V BS Supply Current vs. 8 Figure 9B. V BS Supply Current vs. Logic "" Input Bias Current (μa) Figure A. Logic "" Input Bias Current vs. Logic "" Input Bias Current (μa) Figure A. Logic "" Input Bias Current vs. AN- 9

10 Logic "" Input Bias Current (μa) Logic "" Input Bias Current (μa) 8 8 Figure B. Logic "" Input Bias Current Figure B. Logic "" Input Bias Current vs. vs. Logic "" CS Bias Current (μa) Logic "" CS Bias Current (μa) Figure A. Logic "" CS Bias Current vs. Figure A. Logic "" CS Bias Current vs.. Logic "" CS Bias Current (μa).8... Logic "" CS Bias Current (μa) 8 8 Figure B. Logic "" CS Bias Current vs. Figure B. Logic "" CS Bias Current vs. AN-

11 . Logic "" CS Bias Current (μa) Logic "" CS Bias Current (μa) Figure A. Logic "" CS Bias Current vs. Figure A. Logic "" CS Bias Current vs.. Logic "" CS Bias Current (μa).8... Logic "" CS Bias Current (μa) 8 8 Figure B. Logic "" CS Bias Current vs. Figure B. Logic "" CS Bias Current vs. Summary This document highlights the differences between the IRS(7,8,7) and the IR(7,8,7) HVICs. AN-