FAN7390 High-Current, High and Low Side, Gate-Drive IC

Transcription

1 FAN739 High-Current, High and Low-Side, Gate-Drive IC Features! Floating Channels for Bootstrap Operation to +6V! Typically 4.5A/4.5A Sourcing/Sinking Current Driving Capability! Common-Mode dv/dt Noise Canceling Circuit! Built-in Under-Voltage Lockout for Both Channels! Matched Propagation Delay for Both Channels! Logic (S ) and Power (COM) Ground +/- 7V Offset! 3.3V and 5V Input Logic Compatible! Output In-phase with Input Applications! PDP Sustain Driver! HID Lamp Ballast! SMPS! Motor Driver Description November 28 The FAN739 is a monolithic high- and low-side gatedrive IC, which can drive high speed MOSFETs and IGBTs that operate up to +6V. It has a buffered output stage with all NMOS transistors designed for high pulse current driving capability and minimum cross-conduction. Fairchild s high-voltage process and common-mode noise canceling techniques provide stable operation of the high-side driver under high dv/dt noise circumstances. An advanced level shift circuit offers high-side gate driver operation up to =-9.8V (typical) for V BS =15V. The UV circuit prevents malfunction when V DD and V BS are lower than the specified threshold voltage. The high current and low output voltage drop feature make this device suitable for the PDP sustain pulse driver, motor driver, switching power supply, and highpower DC-DC converter applications. 8-SOP 8-DIP 14-SOP Ordering Information Part Number Package Operating Temperature Range Eco Status Packing Method FAN739N 8-DIP Tube FAN739M FAN739MX 8-SOP -4 C ~ 125 C RoHS Tube Tape & Reel FAN739M1 FAN739M1X 14-SOIC Tube Tape & Reel For Fairchild s definition of green Eco Status, please visit: FAN739 Rev. 1..3

2 Typical Application Circuit FAN739 1 Controller 2 3 COM V B RBOOT DBOOT CBOOT Up to 6V R1 Q1 R2 OUTPUT Figure 1. Application Circuit for Half-Bridge (Referenced 8-SOP/DIP) 15V 4 V DD 5 C1 R3 Q2 R4 Load FAN739 Rev.1 15V RBOOT DBOOT FAN739M1 Controller S S 4 V B CBOOT R1 R2 Up to 6V Q1 5 COM OUTPUT 7 V DD 8 Load C1 R3 Q2 R4 FAN739M1 Rev.3 Figure 2. Application Circuit for Half-Bridge (Referenced 14-SOIC) FAN739 Rev

3 Internal Block Diagram 2 FAN739 PULSE GENERATOR 1 NOISE CAELLER 2K 2K UV DELAY VSS/COM LEVEL SHIFT UV Figure 3. Functional Block Diagram (Referenced 8-SOP/DIP) R S R Q DRIVER DRIVER FAN739 Rev.6 V B V DD COM FAN739M1 13 V B UV PULSE GENERATOR 1 NOISE CAELLER 2K R S R Q DRIVER V DD UV 2 DELAY VSS/COM LEVEL SHIFT DRIVER 6 2K S 3 5 COM Pin 4, 8, 9, 1 and 14 are no connection FAN739M1 Rev.6 Figure 4. Functional Block Diagram (Referenced 14-SOIC) FAN739 Rev

4 Pin Configurations COM FAN739N FAN739M FAN739 6 FAN739 Rev V B V DD S COM Figure 5. Pin Assignments (Top View) FAN739M1 FAN739M1 FAN739M1 Rev V DD V B Pin Definitions 8-Pin 14-Pin Name Description 1 1 Logic Input for High-Side Gate Driver Output 2 2 Logic Input for Low-Side Gate Driver Output 3 S Logic Ground (FAN739M1 only) 3 5 COM Low-Side Driver Return 4 6 Low-Side Driver Output 5 7 V DD Low-Side and Logic Part Supply Voltage 6 11 High-Voltage Floating Supply Return 7 12 High-Side Driver Output 8 13 V B High-Side Floating Supply 4, 8, 9, 1, 14 No Connect FAN739 Rev

5 Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. T A =25 C, unless otherwise specified. Symbol Characteristics Min. Max. Unit High-Side Floating Supply Offset Voltage V B -25. V B +.3 V V B High-Side Floating Supply Voltage V V High-Side Floating Output Voltage -.3 V B +.3 V V DD Low-Side and Logic Fixed Supply Voltage V V Low-Side Output Voltage -.3 V DD +.3 V V IN Logic Input Voltage ( and ) S -.3 V DD +.3 V S Logic Ground (FAN739M1 only) V DD -25 V DD +.3 V d /dt Allowable Offset Voltage Slew Rate 5 V/ns P D (1, 2, 3) Power Dissipation 8-DIP SOP SOIC 1. 8-DIP 1 θ JA Thermal Resistance, Junction-to-Ambient 8-SOP 2 C/W 14-SOIC 11 T J Junction Temperature +15 C T STG Storage Temperature +15 C Notes: 1. Mounted on 76.2 x x 1.6mm PCB (FR-4 glass epoxy material). 2. Refer to the following standards: JESD51-2: Integral circuits thermal test method environmental conditions - natural convection JESD51-3: Low effective thermal conductivity test board for leaded surface mount packages 3. Do not exceed P D under any circumstances. W Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol Parameter Min. Max. Unit V B High-Side Floating Supply Voltage V High-Side Floating Supply Offset Voltage 6-V DD 6 V V High-Side Output Voltage V B V V DD Low-Side and Logic Supply Voltage 1 22 V V Low-Side Output Voltage COM V DD V V IN Logic Input Voltage ( and ) S V DD V T A Operating Ambient Temperature C FAN739 Rev

6 Electrical Characteristics V BIAS (V DD, V BS )=15.V, =S =COM, T A =25 C, unless otherwise specified. The V IL, V IH, and I IN parameters are referenced to S /COM and are applicable to the respective input signals and. The V O and I O parameters are referenced to COM and is applicable to the respective output signals and. Symbol Characteristics Test Condition Min. Typ. Max. Unit POWER SUPPLY SECTION (V DD AND V BS ) V DDUV+ V BSUV+ V DDUV- V BSUV- V DDUVH V BSUVH V DD and V BS Supply Under-Voltage Positive-going Threshold V DD and V BS Supply Under-Voltage Negative-going Threshold V DD and V BS Supply Under-Voltage Lockout Hysteresis Voltage I LK Offset Supply Leakage Current V B = =6V 5 I QBS Quiescent V BS Supply Current V IN =V or 5V 45 8 µa I QDD Quiescent V DD Supply Current V IN =V or 5V I PBS Operating V BS Supply Current f IN =2kHz, rms value I PDD Operating V DD Supply Current f IN =2kHz, rms value µa GIC INPUT SECTION (, ) V IH Logic "1" Input Voltage 2.5 V IL Logic "" Input Voltage 1.2 V I IN+ Logic "1" Input Bias Current V IN =5V 25 5 I IN- Logic "" Input Bias Current V IN =V µa R IN Input Pull-down Resistance 1 2 KΩ GATE DRIVER OUTPUT SECTION (, ) V OH High-level Output Voltage, V BIAS -V O No Load 1. V V OL Low-level Output Voltage, V O No Load 35 mv Output High, Short-circuit Pulsed I O+ Current (4) V O =V, V IN =5V with PW<1µs Output Low, Short-circuit Pulsed V I O =15V, V IN =V with O- Current (4) PW<1µs A Allowable Negative V Pin Voltage for S Signal Propagation to V S - COM S -COM/COM-S Voltage Educability V.5 V Note: 4. This parameter guaranteed by design. Dynamic Electrical Characteristics V BIAS (V DD, V BS )=15.V, =S =COM=V, C L =1pF and T A =25 C unless otherwise specified. Symbol Characteristics Test Condition Min. Typ. Max. Unit t on Turn-on Propagation Delay =V 14 2 t off Turn-off Propagation Delay =V 14 2 MT Delay Matching, HS & LS Turn-on/off 5 ns t r Turn-on Rise Time 25 5 t f Turn-off Fall Time 2 45 FAN739 Rev

7 Typical Characteristics t ON [ns] t R [ns] Figure 6. Turn-on Propagation Delay t OFF [ns] t F [ns] Figure 7. Turn-off Propagation Delay Figure 8. Turn-on Rise Time Figure 9. Turn-off Fall Time MT ON [ns] 3 2 MT OFF [ns] Figure 1. Turn-on Delay Matching Figure 11. Turn-off Delay Matching FAN739 Rev

8 Typical Characteristics (Continued) I QDD [ μa] I PDD [ μa] Figure 12. Quiescent V DD Supply Current I QBS [ μa] I PBS [ μa] Figure 13. Quiescent V BS Supply Current Figure 14. Operating V DD Supply Current Figure 15. Operating V BS Supply Current V DDUV+ [V] 8.5 V DDUV- [V] Figure 16. V DD UV+ Figure 17. V DD UV- FAN739 Rev

9 Typical Characteristics (Continued) V BSUV+ [V] V OH [mv] Figure 18. V BS UV V BSUV- [V] V OL [mv] Figure 19. V BS UV Figure 2. High-Level Output Voltage Figure 21. Low-Level Output Voltage V IH [V] V IL [V] Figure 22. Logic High Input Voltage Figure 23. Low Input Voltage FAN739 Rev

10 Typical Characteristics (Continued) I IN+ [ μa] Figure 24. Logic Input High Bias Current [V] Figure 25. Allowable Negative Voltage. FAN739 Rev

11 Switching Time Definitions 1nF 1 COM V B 2 7 1µF 1nF 3 4 FAN739 Rev V DD 5 1nF 15V 15V 1µF 1nF Figure 26. Switching Time Test Circuit (Referenced 8-SOP) Figure 27. Input/Output Timing Diagram FAN739 Rev.1 5% 5% t on t r t off t f 9% 9% 1% 1% FAN739 Rev.1 Figure 28. Switching Time Waveform Definitions 5% 5% 1% 1% MT MT 9% FAN739 Rev.1 9% Figure 29. Delay Matching Waveform Definitions FAN739 Rev

12 Physical Dimensions PIN ONE INDICATOR (.33) 1.75 MAX R.1 R (1.4) DETAIL A SCALE: 2: M C BA C A x B SEATING PLANE.1 C GAGE PLANE LAND PATTERN RECOMMENDATION SEE DETAIL A OPTION A - BEVEL EDGE OPTION B - NO BEVEL EDGE NOTES: UNLESS OTHERWISE SPECIFIED 5.6 A) THIS PACKAGE CONFORMS TO JEDEC MS-12, VARIATION AA, ISSUE C, B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT ILUDE MOLD FLASH OR BURRS. D) LANDPATTERN STANDARD: SOIC127P6X175-8M. E) DRAWING FILENAME: M8AREV13 Figure 3. 8-Lead Small Outline Package (SOP) Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor s online packaging area for the most recent package drawings: FAN739 Rev

13 Physical Dimensions (Continued). pdip8_dim.pdf Figure Lead Dual In-Line Package (DIP) Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor s online packaging area for the most recent package drawings: FAN739 Rev

14 Physical Dimensions (Continued) 6. B PIN ONE INDICATOR (.27) 1.8 MAX # TOP VIEW A B C B A C.5MIN B 1.7 LAND PATTERN RECOMMENDATION (R.2) # SEE DETAIL A.3.15 B SIDE VIEW.1 MAX C END VIEW NOTES: A) THIS DRAWING COMPLIES WITH JEDEC MS-12 EXCEPT AS NOTED. B) THIS DIMENSION IS OUTSIDE THE JEDEC MS-12 VALUE. C) ALL DIMENSIONS ARE IN MILLIMETERS. D) DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH, AND TIE BAR EXTRUSIONS. E) LANDPATTERN STANDARD: SOIC127P6X145-14M F) DRAWING FILE NAME AND REVISION : M14CREV1.36 GAGE PLANE SEATING PLANE 8 Æ (R.1).9.5 DETAIL A Figure Lead Small Outline Integrated Circuit Package (SOIC) Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor s online packaging area for the most recent package drawings: FAN739 Rev

15 FAN739 Rev