Design a pattern generator with low switching activity to test complex combinational logic with high test coverage

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1 Design a pattern generator with low switching activity to test complex combinational logic with high test coverage 1 Jay B Dabhi 1 VLSI & Embedded Systems Design GTU PG School, Ahmedabad, India E Mail: 1 jaydabhi001@gmail.com, 1 jaydabhi3@gmail.com Abstract In circuit large number of combinational logic used so logic depth is large, so it is impossible to test every fault with other techniques because it s take more time. In order to increase speed of an algorithm for test generation, it is necessary to reduce the number of backtracks in the algorithm and to shorten the process time between backtracks. To solve this problem an Automatic Test Pattern Generator (ATPG) is proposed based on modification of FAN (fan -out-oriented test generation algorithm) Algorithm is describe. Also with some techniques reduce the switching activity of generated patterns for decrease the power consumption of ATPG. Keywords- Automatic Test Pattern Generator (ATPG), fanout-oriented test generation algorithm (FAN), path oriented decision making algorithm (PODEM), stuck-at faults(s-a-f), Pattern Generator (PG). I. INTRODUCTION With the development of a Large Scale Integrated circuit (LSI) and Very Large Scale Integrated Circuit (VLSI) technologies, in circuit large number of combinational logic used so logic is very complex. So, problem of fault detection for logic circuits is becoming more and more difficult. As the logic circuits under test get larger, generating tests is becoming harder. One approach to overcome this is to take several techniques known as design for testability [3]. There are many test generation algorithms have been proposed over the years, but there is three best algorithms are available for logic circuit. Basic algorithm is D-algorithm widely used in testing developed by Roth in IBM However, it has been pointed out that the D-algorithm is extremely inefficient in generating tests for combinational circuits [3], because of some drawback are as under: 1. It establishes no strategy for the order of fault sensitization, justification, or fault propagation [2]. 2. It is algorithmically very complex because all combinations of paths must be examined. To improve drawbacks of D-algorithm, a new test generation algorithm called PODEM was developed by Goel in IBM 1981 & proves that it is significantly faster than the D- algorithm by presenting experimental results. But still some drawbacks remain in that algorithm are as under: 1. It will eventually try all the primary input combinations, either explicitly or implicitly, until it finds a test [2]. To improve test generation algorithm, it is necessary to reduce the number of occurrences of backtracks in the algorithm and to shorten the processing time between backtracks, which is presented by FAN (fan-out-oriented test generation algorithm). FAN is a complete algorithm in that it will generate a test if one exists [3]. The obvious reason to test circuits is to separate good ones from faulty ones [2]. In this paper we consider the stuck-at fault circuit because it stuck at model has been widely accepted as a standard target model for the generation of the test pattern for current circuit. Section II introduces to the basic architecture or block diagram of pattern generator. Section III introduce to the proposed algorithm. Section IV gives information about Implementation of algorithm in detail. Section V deals with Gray patterns by which reduce the switching activity of generated pattern. Section VI gives explanation of algorithm with example. Section VII concentrates on the testing time, power, & fault coverage respectively and finally section VIII discusses about conclusion and future scope. II. BLOCK DIAGRAM OF PATTERN GENERATOR In this section discussed about the architecture of proposed design, figure 1 Show the block diagram of proposed design. A first step in this is to generate the patterns to test combinational circuit and it s done by only applying proposed algorithm to the circuit. Page 286

2 Generated patterns are stored in memory or in one file and gives to the CUT for testing propose and check the results for circuit using ORA. Result comes in PASS/FAIL, its filter the bad circuit from good one and ship to the customer. Check & Implication process: The tasks of the process are Compute all values that can be uniquely determined by. There are two types of ass per discussion above: Input File (.v) Verilog code circuit design Proposed Algorithm Pattern generated with gray techniques 1. Backward Implication 2. Forward Implication START Generated pattern apply to the CUT for test Define directive, integer & arrays to store net value Result (Pass/Fail)? ORA (output response analyzer) CUT (circuit under test) Open a file (.V) in read mode by open in perl and another in write mode to store generated pattern III. Figure 1: Pattern Generator block diagram PROPOSED ALGORITHM FOR PATTERN GENERATOR Main steps are described below with the flow chart of proposed ATPG algorithm for the test generation. It s used for the combinational circuit with 2 fanin-fanout gates like AND, OR, NAND, NOR, XOR, XNOR. Flow chart of proposed ATPG algorithm is given in figure 2. Scan input file to find input output and wire and fan-in & fan-outs with respect to gate Perform backward by calling imply_check function Set current objective and select one by one & call multiple backtrack Backward Multiple backtracks IV. IMPLIMENTATION OF ALGORITHM To implement pattern generator modified algorithm based on FAN which is shown in figure 2 with detail description in blocks. The steps for implementation of proposed algorithm are as under. The first step for the develop program is to find the name of the signal like head objectives, free lines, bound lines etc. from the combinational circuit, so define all the directives, data and array to store names of signals. Next step is to open a file (Verilog file with.v extension) for which you want to generate pattern by open function in Perl script. Scan the input file line by line with file handler and store the data in storage element like array or hash in Perl, or also generate one netlist.txt file as input for further process. After define all signal take one by one signal from the list of signals and perform imply_check function. We determine as many signal values as possible which can be uniquely implied. To do this, we take the operation which completely traces such signal determination both forwards and backwards through the circuit [1]. Select all head objective from array and perform forward for each head objective by call imply_check function Justify all unjustified headlines if its primary IP & store the value in pattern file Is there fault propagate at output & all lines justified? END Forward Assign value & add in current objective Figure 2: Proposed Algorithm for PG Backward Implication: First step in the backward is set all signal value to x by. Now select one signal from the signal list and give inverse value to that signal is called activation of fault. Activation of Fault is to give an opposite value to the Stuck-at value denoted by D or D. Figure 3 shows the example of activations of faults. Page 287

A=1 B=1 (A) E=D A=X B=X (B) B=1 E=D A=1 C=1 E=D (C) Set Current Objective: now set the current objective for the multiple back trace process, if fault is at PI and its stem then find branches of it &

Multiple backtracks Figure 3: Activation of faults (A) E s-a-0 (B) E s-a-1 (C) E s-a-0 Take justification value v where v (0 and 1) is fault at signal & perform the backward process.

3 A=1 B=1 (A) E=D A=X B=X (B) B=1 E=D A=1 C=1 E=D (C) Set Current Objective: now set the current objective for the multiple back trace process, if fault is at PI and its stem then find branches of it & put it in current objective. If fault is on Pi and if it is fan-in then repeats process. In XOR gate case, no controlling value so both fan-in s put in the current objective. Multiple backtracks Figure 3: Activation of faults (A) E s-a-0 (B) E s-a-1 (C) E s-a-0 Take justification value v where v (0 and 1) is fault at signal & perform the backward process. The flow chart of the Backward Implication process is shown in figure 4 [1].Perform it until the primary input reaches. If only 1 fan-in is to be justify then use less controlling value & we can got it from controllability 0 and 1 (CC0, CC1) from [5]. Set all vaule to x Find the name of signal which fault is present if stuck at 1 then set value to 0 else set value to 1. If it is form (fanout branch) Backward If it is O/p of gates If its P/I Fanin1 Its Headline? Store signal name & value in head objective Input value 0 & C0_1<C1_2 Fanin2 Input value = control value? Find fanin 1 & fainin 2 name Select signal from current objective and value respectively and fine signal position at gate Input value 1 & C0_1<C1_2 Fanin1 Its input of gate? Calculate input value Input value!= control value? Find fanin 1 & fainin 2 name Fanin2 Assign oncountrolling value to Both the fanin ( first to fanin which has highest controllability value Its from fan-out? Find the stream of fanout braches value Is 0? Increment n0 by 1 Store name of signal also n0 & n1 Strm Objectives Null? Exit Increment n1 by 1 Find stream of fan-out and set value for steam Store the value Exit Figure 5: Flow chart of multiple Back trace AND with 0 or NAND with 1 Find fanin1,fanin2 Assign value=0 fanin with less CC0 value if CC0 of both fanin are equal then to fanin NAND with 0 or AND with 1 Find fanin1 and fanin2 value=1 to both NOR with 0 or OR with 1 Find fanin1,fanin2 Assign value=1 Fanin with less CC0 value if CC0 of both fanin are equal then to fanin OR with 0 or NOR with 1 Find fanin1 and fanin2 value=1 to both Figure 4: Flow chart of Backward Implication Multiple Back trace: Then call Multiple Back trace function used by FAN algorithm and perform until current objective is null. If between this processes if any stems comes then add it in to steam objective [1]. Here an array is formed for stem objective with stem netno, n0 (netno), n1 (netno). Where n0 (netno) shows how many times the logic value 0 comes at the stem netno and n1 (netno) shows the how many times the logic 1 value comes at stem netno [1]. If one of them is zero then contradiction will not occurs. If n0>n1 then take logic value 0 for further back tracing. If n1>n0 then take logic value 1 for further back tracing. Figure 5 shows the flow of multiple backtracking for current objective. Forward Implication: Take head objective one by one and perform forward until to PO. If PO Page 288

4 reaches then stop. In each step of forward, check the value on net ed during the backward [1]. If both the values, ed during backward and value to be during forward are matches then Only otherwise take the reverse decision, make complimentary value of head objective and do forward [1]. Even if there is a mismatch or contradiction then return to the end of program. Forward logic is described by the flow chart given in figure 6. After perform forward process check all bound lines are justified or not. If not then take it as a current objective & call Multiple Back trace function for these lines. Forward Take inverse value of signal value and check its gate or stem or PO generates patterns in gray sequence from binary. Let s Consider, The Binary number B 1 B 2 B 3 B 4... B n and the Gray code is G 1 G 2 G 3 G 4... G n. 1. Most significant bit (B 1 ) is same as the most significant bit in Gray Code (B 1 = G 1 ) 2. To find next bit perform Ex-OR (Exclusive OR) between the Current binary bit and previous bit. G n = B n (Ex-OR) B n-1 Now compare the first gray pattern with generated patterns by algorithm for particular circuit. If pattern match then puts in first place, now take second pattern from gray sequence and repeat process again and it will continue up to the end of all patterns of gray sequence. Example: consider 3PI circuit, here apply algorithm and pattern generated for that is in table 1 now compare it with 3 bit gray pattern sequence and rearrange it in gray sequence. Now check the switching activity difference between generated pattern after algorithm and patterns after rearranged, it shows the reduction of switching activity in patterns. So by these techniques we can reduce power consumption for pattern generator. F_value =1 and Make PO flag on Exit PO For AND 0 to O/P For NAND 1 to O/P F_value =0 or Signal value is 0? Temp_set_value=1 set_value=x o/p set_value=contra Temp_set_value=0 set_value=x o/p set_value=contra Gate Signal is fanin1 or fanin 2? N F_value=1 Stem For NOR 0 to O/P For OR 1 to O/P F_value= 1, nand Find fanout branches Fanin 1 Fanin2 s Assign value=temp_set_value F_value =0 nor Temp_set_value=1 set_value=x o/p set_value=contra Temp_set_value=0 set_value=x o/p set_value=contra Here in figure 7, gray patterns shows in blue color with minimum switching activity, before block show the generated patterns in by algorithm with 9 switching activity and after block patterns after rearrangement in gray sequence with reduction up to 7 switching activity. Gray sequence Before After Generated patterns Compared with gray sequence Total number of switching activity is Total number of switching activity is 7 Figure 7: Reduction of switching activity Figure 6: Flow chart of Forward Implication V. GRA TECHNIQUES TO REDUCE SWITCHING ACTIVIT For reduction of switching activity of generated patterns we need to rearrange it s in gray number sequence. First as per the no of inputs of the circuit we want to generate all patterns in Gray sequence by the gray counter generation. By equation 1 VI. EXAMPLE In figure 8 circuits is taken to explain the working of proposed ATPG algorithm. Consider the s-a-0 fault in the signal OP. Now justify the value 1. First of all consider initial value of each net is X. Now activate the fault by apply opposite value 1 to w1 net and perform backward. In this case when only one input is to be justify then compare controllability values of both the fan-in of Page 289

5 gate and to the fan-in with less controllability value. i1 i2 i3 and w1 Figure 8: CUT Here (op, 1) is the initial objective. Select one gate from the D frontier, controlling value to the input of the gate which has x value. In this case controlling value 1 to the i1. Remove one current objective. Take one current objective (w1, 1). Now call multiple back trace function and perform. Now current objective is (i1, 1). It is head line so stop the back trace here for this objective. Store net no in head objective (i1, 1). The various objective statuses are shown in table. Current Process Entry Objective (op, 1) (op, 1) (w1, 1) (w1, 1) (i1, 1) (i1, 1) or Table 1 : status of Objectives op Head Objective - - (i1, 1) But with the fault collapse method we reduce is up to 2 faults shown in window 2(figure 10). Now apply algorithm to the reduced fault and generate pattern for each fault. In figure 11 shows the generated pattern according to the fault of particular net. Figure 10: Total no of faults after reduction Now current objective is null. Take head objective one by one and apply forward. Here no contradiction has occurred. Now check there are any unjustified bound lines or not. Here no any lines available. And fault is propagating to the PO. So for s-a-0 at w signal pattern generated is 110. VII. RESULT OF EXAMPLE A result for above circuit is shown below. The program for proposed design is return in Perl language and output is show by the snap shot of output cmd window. Proposed design is generic. Here total no of fault is 5 in the circuit as shown in figure 9 with net no. Figure 11: pattern generated for faults. The number of reduced bits and computing time for these circuits are mentioned in table 2. Circuit No No of bits Computi No. of nets Before fault reduction After fault reduction ng time (Sec.) Circuit C Circuit Table10: comparison of bits and computing time. Figure 9: Total no of faults before e reduction VIII. CONCLUSION By proposed ATPG design we can test any random complex logic circuits so, it is totally in-depended to the circuit. In circuit large number of combinational logic used so logic depth is large, so it is impossible to test every fault with Page 290

6 the hand because its take more time. To overcome this problem new ATPG design is discussed which tests logical designs automatically. As complexity increase no of test pattern increase so we can reduce the test pattern by the proposed system which increase the speed of testing so, by proposed architecture we reduce the test time. By reducing switching activity reduce the power consumption of the Proposed ATPG equipment. The target of proposed architecture is to get fault coverage larger up-to 100% for combinational circuit. ACKNOWLEDGMENT Any accomplishment requires the effort of many people and this work is not different. And it is my prime duty to acknowledge the person who directly or indirectly helped me during completion of this dissertation report. So I take opportunity to heartily thank our project guide respected Mr. Hitesh Pradhan for his valuable guidance and touch of inspiration and motivation throughout the literature work without whose help the work would not have been in the shape what it is. REFERENCES [1] National Institute of Vaishali Dhare, Dr. Usha Mehta, Advanced ATPG Based on Fan, Testability Measures and Fault Reduction International Journal of VLSI design & Communication Systems (VLSICS) Vol.5, No.2, April [2] Tom Kirkland, M. Ray Mercer, A Tutorial of Algorithm for Automatic Test Pattern Generation, Design &Test of Computers, IEEE (Volume: 5, Issue: 3), June1988. [3] Hideo Fujiwara., Takeshi Shimono, On the Acceleration of Test Generation Algorithm, IEEE transaction on computers, Vol. C-32, No 12, December 1983, pp [4] Roland Dobai, Elena Gramatová Institute of Informatics Slovak Academy of Sciences, Test Pattern Generation for the Combinational Representation of Asynchronous Circuits, 2010 IEEE. [5] Vaishali Dhare, Usha Mehta, Development of Controllability Observability Aided Combinational ATPG with Fault Reduction, Lecture Notes in Computer Science, Recent Trends in Networks and Communications, Springer, Pg. No , July [6] S.Saravanan, Har Narayan Upadhyay, Asst. Prof., School Of Computing, Assoc. Dean, School Of Electrical And Electronics, Sastra, Transition Based Input Test Vector Partitioning For Low Power Switching Activity, Journal Of Theoretical And Applied Information Technology, 31st October [7] Abramovici, M.A. Breuer and A.D. Friedman, Digital Systems Testing and Testable Design, IEEE Press, NJ [8] Micheal Bushnell and Vishwani Agrawal, Essentials of Electronic Testing, Springer Publication. [9] Alexander Miczo, Digital Logic Testing And Simulation Published by John Wiley & Sons, Inc., Hoboken, New Jersey. Page 291

Testing Digital Systems I

Testing Digital Systems I Testing igital Systems I Testing igital Systems I Lecture 8: Boolean Testing Using Fault Models ( Algorithm) Instructor: M. Tahoori Copyright 2, M. Tahoori TS I: Lecture 8 Specific-Fault Oriented Test