SEMICONDUCTOR TECHNICAL DATA

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1 SEIONDUTOR TEHNIL DT The 44 programmable timer coists of a stage binary counter, an integrated oscillator for use with an external capacitor and two resistors, an automatic power on reset circuit, and output control logic. Timing is initialized by turning on power, whereupon the power on reset is enabled and initializes the counter, within the specified range. With the power already on, an external reset pulse can be applied. Upon release of the initial reset command, the oscillator will oscillate with a frequency determined by the external R network. The stage counter divides the oscillator frequency (fosc) with the nth stage frequency being fosc/2n. vailable Outputs 28, 2, 2 or 2 Increments on Positive Edge lock Traitio uilt in Low Power R Oscillator (± 2% accuracy over temperature range and ± 2% supply and ± % over processing at < khz) Oscillator ay e ypassed if External lock Is vailable (pply external clock to Pin ) External aster Reset Totally Independent of utomatic Reset Operation Operates as 2n Frequency Divider or Single Traition Timer / Select Provides Output Logic Level Flexibility Reset (auto or master) Disables Oscillator During Resetting to Provide No ctive Power Dissipation lock onditioning ircuit Permits Operation with Very Slow lock Rise and Fall Times utomatic Reset Initializes ll ounters On Power Up Supply Voltage Range =. to 8 with uto Reset Disabled (Pin = ) = 8. to 8 with uto Reset Enabled (Pin = VSS) Î XIU RTINGS* (Voltages Referenced to VSS) Symbol Parameter ÎÎ Value Unit D Supply Voltage ÎÎ. to + 8. V Vin, Vout Input or Output Voltage (D or Traient)ÎÎ Iin Input urrent (D or Traient), per Pin ÎÎ Iout Output urrent (D or Traient), per PinÎÎ PD Power Dissipation, per Package Tstg Storage Temperature TL Lead Temperature (8 Second Soldering)ÎÎ. to +. V ± m ± 4 m mw to + 2 * aximum Ratings are those values beyond which damage to the device may occur. Temperature Derating: Plastic P and D/DW Packages: 7. mw/ From To 2 eramic L Packages: 2 mw/ From To 2 L SUFFIX ERI SE 2 ORDERING INFORTION 4XXXP 4XXXL 4XXXD Plastic eramic SOI T = to 2 for all packages. PIN SSIGNENT Rtc tc N R R VSS N = NO ONNETION P SUFFIX PLSTI SE 48 D SUFFIX SOI SE 7 N / SEL REV /4 OTOROL otorola, Inc. OS LOGI DT 44

2 ÎÎ ELETRIL HRTERISTIS (Voltages Referenced to VSS) haracteristic Output Voltage Vin = or Vin = or Level Level Input Voltage Level (VO = 4. or. ) (VO =. or. ) (VO = or ) (VO =. or 4. ) (VO =. or. ) (VO = or ) Output Drive urrent (VOH = 2. ) (VOH =. ) (VOH = ) (VOL =.4 ) (VOL =. ) (VOL = ) Level Source Sink Symbol VOL VOH VIL VIH IOH 2 2 in ax in Typ # ax in ax Unit IOL Input urrent Iin ±. ±. ±. ±. µdc Input apacitance (Vin = ) in 7. pf. mdc mdc uiescent urrent (Pin is High) uto Reset Disabled IDD µdc uto Reset uiescent urrent (Pin is low) IDDR µdc Supply urrent** (Dynamic plus uiescent) ID ID = (.4 µ/khz) f + IDD ID = (.8 µ/khz) f + IDD ID = (.2 µ/khz) f + IDD #Data labelled Typ is not to be used for design purposes but is intended as an indication of the I s potential performance. ** The formulas given are for the typical characteristics only at 2. When using the on chip oscillator the total supply current (in µdc) becomes: IT = ID + 2 tc f x where ID is in µ, tc is in pf, in Volts D, and f in khz. (see Fig. ) Dissipation during power on with automatic reset enabled is typically =. µdc This device contai protection circuitry to guard agait damage due to high static voltages or electric fields. However, precautio must be taken to avoid applicatio of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be cotrained to the range VSS (Vin or Vout). Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or ). Unused outputs must be left open OTOROL OS LOGI DT

3 ÎÎ SWITHING HRTERISTIS* (L = pf, T = 2 ) Output Rise and Fall Time ttlh, tthl = ( /pf) L + 2 ttlh, tthl = (.7 /pf) L + 2. ttlh, tthl = (. /pf) L +. haracteristic Symbol in Typ # ax Unit Propagation Delay, lock to (28 Output) tplh, tphl = (.7 /pf) L + 4 tplh, tphl = (. /pf) L + 27 tplh, tphl = (. /pf) L + 87 Propagation Delay, lock to (2 Output) tphl, tplh = (.7 /pf) L + tphl, tplh = (. /pf) L + 47 tphl, tplh = (. /pf) L ttlh, tthl tplh tphl tphl tplh lock Pulse Width twh(cl) lock Pulse Frequency (% Duty ycle) fcl R Pulse Width twh(r) aster Reset Removal Time trem * The formulas given are for the typical characteristics only at 2. #Data labelled Typ is not to be used for design purposes but is intended as an indication of the I s potential performance µs µs Hz PULSE GENERTOR R / SELET R L PULSE GENERTOR R / SELET R L VSS VSS (Rtc ND tc OUTPUTS RE LEFT OPEN) % % % % DUTY YLE % % % tplh % % % ttlh % % tphl tthl Figure. Power Dissipation Test ircuit and Waveform Figure 2. Switching Time Test ircuit and Waveforms OTOROL OS LOGI DT 44

4 EXPNDED LOK DIGR 2 Rtc tc 2 OS 8 STGE 28 OUNTER STGE OUNTER OF 4 UX 8 UTO POWER ON = PIN 4 VSS = PIN 7 STER / SELET FREUENY SELETION TLE Number of ounter Stages n ount 2n TRUTH TLE State Pin uto Reset, uto Reset Operating uto Reset Disabled aster Reset, Timer Operational aster Reset On /, Output Initially Low fter Reset Output Initially High fter Reset ode, Single ycle ode Recycle ode TO LOK IRUIT INTERNL 2 tc RT Figure. Oscillator ircuit Using R onfiguration 44 4 OTOROL OS LOGI DT

5 TYPIL R OSILLTOR HRTERISTIS FREUENY DEVITION (%) R T = kω, = pf 2 2 V = V V R S =, f =. V DD = V, T = 2 R S = 2 kω, f = 7.8 V DD = V, T = 2 7 T, IENT TEPERTURE ( ) Figure 4. R Oscillator Stability 2 f, OSILLTOR FREUENY (khz) f S FUNTION OF (RT = kω) ( = 2 kω) = V f S FUNTION OF RT ( = pf) ( 2RT).. k k k. m RT, RESISTNE (OHS)...., PITNE (µf) Figure. R Oscillator Frequency as a Function of Rtc and tc OPERTING HRTERISTIS With uto Reset pin set to a the counter circuit is initialized by turning on power. Or with power already on, the counter circuit is reset when the aster Reset pin is set to a. oth types of reset will result in synchronously resetting all counter stages independent of counter state. uto Reset pin when set to a provides a low power operation. The R oscillator as shown in Figure will oscillate with a frequency determined by the external R network i.e., f = 2. Rtctc and 2 Rtc where kω if ( khz f khz) The time select inputs ( and ) provide a two bit address to output any one of four counter stages (28, 2, 2 and 2). The 2n counts as shown in the Frequency Selection Table represents the output of the Nth stage of the counter. When is, 2 is selected for both states of. However, when is, normal counting is interrupted and the th counter stage receives its clock directly from the oscillator (i.e., effectively outputting 28). The / select output control pin provides for a choice of output level. When the counter is in a reset condition and / select pin is set to a the output is a, correspondingly when / select pin is set to a the output is a. When the mode control pin is set to a, the selected count is continually tramitted to the output. ut, with mode pin and after a reset condition the flip flop (see Expanded lock Diagram) resets, counting commences, and after 2n counts the flip flop sets which causes the output to change state. Hence, after another 2n counts the output will not change. Thus, a aster Reset pulse must be applied or a change in the mode pin level is required to reset the single cycle operation. DIGITL TIER PPLITION tr INPUT Rtc tc N R S R R / N.. OUTPUT When aster Reset (R) receives a positive pulse, the internal counters and latch are reset. The output goes high and remai high until the selected (via and ) number of clock pulses are counted, the output then goes low and remai low until another input pulse is received. This one shot is fully retriggerable and as accurate as the input frequency. n external clock can be used (pin is the clock input, pi and 2 are outputs) if additional accuracy is needed. Notice that a setup time equal to the desired pulse width output is required immediately following initial power up, during which time output will be high. t + tr OTOROL OS LOGI DT 44

6 OUTLINE DIENSIONS L SUFFIX ERI DIP PKGE SE 2 ISSUE V T SETING PLNE F 8 E G D PL.2 (.) T N S K L J PL.2 (.) T S NOTES:. DIENSIONING ND TOLERNING PER NSI Y4., ONTROLLING DIENSION: INH.. DIENSION L TO ENTER OF LED WHEN FORED PRLLEL. 4. DIENSION F Y NRROW TO.7 (.) WHERE THE LED ENTE THE ERI ODY. INHES ILLIETE DI IN X IN X D..2.. E S.27 S F..4. G. S 2.4 S H K L. S 7.2 S N P SUFFIX PLSTI DIP PKGE SE 48 8 ISSUE R H 8 G F D PL S K.2 (.) T SETING T PLNE J L NOTES:. DIENSIONING ND TOLERNING PER NSI Y4., ONTROLLING DIENSION: INH.. DIENSION L TO ENTER OF LEDS WHEN FORED PRLLEL. 4. DIENSION DOES NOT INLUDE OLD FLSH.. ROUNDED ORNE OPTIONL. INHES ILLIETE DI IN X IN X D..2.. F G. S 2.4 S H S.27 S J K L S OTOROL OS LOGI DT

7 OUTLINE DIENSIONS D SUFFIX PLSTI SOI PKGE SE 7 ISSUE J T SETING PLNE 8 G D PL K P 8 PL.2 (.) S.2 (.) T S S R X 4 J F NOTES:. DIENSIONING ND TOLERNING PER NSI Y4., ONTROLLING DIENSION: ILLIETER.. DIENSIONS ND DO NOT INLUDE OLD PROTRUSION. 4. XIU OLD PROTRUSION. (.) PER SIDE.. DIENSION D DOES NOT INLUDE DR PROTRUSION. LLOWLE DR PROTRUSION SHLL E.27 (.) TOTL IN EXESS OF THE D DIENSION T XIU TERIL ONDITION. ILLIETE INHES DI IN X IN X D F G.27 S S J K P R.2... otorola reserves the right to make changes without further notice to any products herein. otorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does otorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation coequential or incidental damages. Typical parameters which may be provided in otorola data sheets and/or specificatio can and do vary in different applicatio and actual performance may vary over time. ll operating parameters, including Typicals must be validated for each customer application by customer s technical experts. otorola does not convey any licee under its patent rights nor the rights of others. otorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applicatio intended to support or sustain life, or for any other application in which the failure of the otorola product could create a situation where personal injury or death may occur. Should uyer purchase or use otorola products for any such unintended or unauthorized application, uyer shall indemnify and hold otorola and its officers, employees, subsidiaries, affiliates, and distributors harmless agait all claims, costs, damages, and expees, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that otorola was negligent regarding the design or manufacture of the part. otorola and are registered trademarks of otorola, Inc. otorola, Inc. is an Equal Opportunity/ffirmative ction Employer. How to reach us: US/EUROPE/Locatio Not Listed: otorola Literature Distribution; JPN: Nippon otorola Ltd.; Tatsumi SPD JLD, F Seibu utsuryu enter, P.O. ox 22; Phoenix, rizona or Tatsumi Koto Ku, Tokyo, Japan FX: RFX@ .sps.mot.com TOUHTONE SI/PIFI: otorola Semiconductors H.K. Ltd.; 8 Tai Ping Industrial Park, INTERNET: NET.com Ting Kok Road, Tai Po, N.T., Hong Kong OTOROL OS LOGI DT 44/D 7

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