An Integrated Voltage-Mode Boost DC-DC Converter for Portable Electronic Systems

Transcription

1 An ntegrated Voltage-Mode Boost DC-DC Converter for Portable Eletroni Systems An ntegrated Voltage-Mode Boost DC-DC Converter for Portable Eletroni Systems Mei-Chu Jen Yeong-Tsair Lin Jiann-Jong Chen Dong-Shiuh Wu Ho-Cheng Lin Department of Eletroni Engineering, Lunghwa University of Siene and Tehnology Graduate nstitute of Computer and Communiation Engineering, National Taipei University of Tehnology Abstrat A monolithi CMOS voltage-mode, boost DC-DC onverter with integrated power swithes and on-hip pulse-width modulation (PWM) tehnique of swithing ontrol is presented in this paper. The PWM sheme used in this onverter is onstruted by a CMOS ring osillator, whose duty is ompensated by a pseudo hyperbola urrent generator to ahieve almost onstant frequeny operation. The proposed boost DC-DC onverter with a hip area of 0.95 mm is fabriated in a P4M 0.35-μm CMOS proess. The experimental results show that the onverter is well regulated over an output ranges from. to 3.6 V, with an input voltage of. V. The maximum effiieny of the onverter is 9%, and its effiieny is kept above 8% over an output power ranges from 30 to 600mW. Keywords: Pulse-width modulation (PWM), Ring osillator, Voltage-mode, Boost DC- DC onverter.. ntrodution Due to the rapid progress of CMOS tehnology reently, the power supply voltage for many ommerial very large sale integrated hips have dereased to. V and will ontinue to derease to lower levels. This trend is driven by feature size saling down in VLS tehnologies, power management in VLS hip, and inreasing market demands for portable batterypowered produts [] simultaneously. As a result, battery powered devies beome an important appliation area for power semiondutor integrated iruits. Batterypowered systems require high-effiieny low-voltage DC-DC onverters to maximize the run time of the systems from a single battery soure. The trend is foused on implementation of power onverter with high-effiieny and low-power onsumption []-[8]. Pulse-width modulation (PWM) tehnique is the most frequently used tehnique in swithing onverters [5]-[9]. The kernel iruit of PWM is voltageontrol duty-yle (VCDC) iruit. Many tehniques are available to modulate the pulse width of the ontrol signal, suh as by omparing a modulation referene signal to onstant frequeny arrier [0], [], by digitally ontrol []-[4], or by urrentmode ontrol [5], [6], et. Two voltage-mode realizations of pulsewidth modulators have been presented in [0] and [], respetively. These two iruits have the potential to maintain the onstant frequeny operation. However, these realizations require a large number of passive omponents, whih are diffiult to fabriate by digital CMOS proesses and to operate at low supply voltage. n order to ahieve the multi-funtion from the programmability, [-4] reported a digital

2 龍華科技大學學報第二十四期,007. PWM iruit, respetively. These digital iruits usually are implemented with analog-to-digital onverters (ADCs) and miroproessors. Resulting their size and ost are rather higher than most of the analog ounterparts. As a result, these tehniques are not suitable for portable appliations. Consequently, we proposed a low-voltage, high-effiieny boost DC-DC onverter for portable eletroni systems. The PWM tehnique [7] used in the proposed boost DC-DC onverter an operate with low supply voltage of.0 V. This boost DC-DC onverter will be useful in low-power multimedia iruits, power eletronis, and teleommuniation appliations.. Ciruit Desriptions An integrated low-voltage, higheffiieny boost DC-DC onverter is designed based on digital CMOS proess. The simplified system blok diagram of the boost onverter is shown in Fig., whih onsists of a power onverter, a CMOS PWM generator, a frequeny-ompensation iruit (error amplifier), a ontrol driver, and a passive low-pass filter. The frequenyompensation iruit is used to set a target output voltage based on referene input voltage and to provide frequeny ompensation to improve overall system stability and dynami response. The PWM iruit is a low-voltage ring osillator, whih harge/disharge urrent is ompensated by a pseudo hyperbola urve urrentgenerating iruit. The ontrol driver provides dead-time ontrol and driving signals that are used to swith on/off the power swith transistors.. PWM Ciruit Design The PWM iruit is onstruted by the delay ell as shown in Fig., whih is used to ontrol the osillation frequeny and duty yle of the CMOS PWM iruit. The MOS transistor, M C, in Fig., funtions as a apaitor for the delay ell. The transfer Fig.. Blok diagram of the proposed boost DC-DC onverter. voltage of the delay ell an be, approximately, obtained as V V + + Mi TN i = VTN VOD () W μ ncox where V TN is the threshold voltage, μ n is the mobility of harge arrier, C ox is the gate oxide apaitane per unit area, W is the hannel width, and L is the hannel length of the NMOS transistor, respetively. And V OD = μnc i ox W L The rise time of this delay ell an be derived as CPVMi ti, for i=, () i where C P is the equivalent input apaitane of the delay ell inluding the MOS apaitor, M C. Based on the delay ell, the PWM iruit an be onstruted as shown in Fig. 3, whih is a urrent-ompensation duty ring osillator. To satisfy the osillation ondition, the stages of this osillator must be odd, and the seven-stage osillator was hosen to obtain the suitable frequeny in this iruit. n Fig.3, both urrents p and p are a ompensated urrent soure. For L

3 An ntegrated Voltage-Mode Boost DC-DC Converter for Portable Eletroni Systems V OD <<V TN and ignore the delay time of the last stage, the transfer voltages of the delay ells are equal and an be written as V M. Then, the osillating period (T) and duty ratio (D) will be given by equations (3) and (4), respetively. As shown in equation (5), the harge urrent of the ring osillator must be a pseudo hyperbola funtion. Through SPCE simulation, the urve of bias urrent b ( b = p + p ) versus ontrolled voltage V an be desribed as Fig. 4. T 3C + PVM (3) p p D 3C V P M p p = = (4) T p + p b Where b = p + p. From equations (3) and (4), it is seen that, if the sum of the ontrol urrent p and p is onstant and equal to the bias urrent, the osillating period of the PWM iruit shown in Fig. 3 an not be a onstant for the different ontrol voltage V. To ahieve onstant osillation period T, the sum of p and p would be ompensated and fulfilled the following ondition, derived from equation (3), p + p T = 3C V P M = onstant (5) Fig. 4. The urve of the bias urrent b of the ompensation iruit versus ontrolled voltage V with V = V, (V: b, H: V )... Priniples of Current ompensation Aording to equation (5) and Fig. 4, we an use the approximate linearity approah to find the bias urrent b of the ompensation iruit. As shown in Fig. 5, the ompensation urrent an be desribed as follows: V b = + Gm V (6) b V p = + Gm V (7) Fig.. The delay ell. b V p = Gm V (8) where G m = μ n C ox ( W L ) and = μ C ( W L Gm p ox ) From equations (6), (7), and (8) we an get the following equation: b Fig. 3. PWM iruit. p 4 + =, if V = 0. 5V (9) p

4 龍華科技大學學報第二十四期,007. p + p V 4 Gm = Gm V GmV + Gm V 4 if = 0 (0) = p V + p 4 + G m V m G V + GmV + Gm V 4 if V = V () where G n is the transondutane of M 8. Similarly, M 36, M 37, M 39, and the urrent soure m form the seond ompensation iruit, whih is used to ompensate the bias urrent in the ase of duty-yle ontrol voltage V in the range from zero volts to 0.5V. Use the approximate approah, the drain urrent, whih flows through transistors M 36 and M 38, an be desribed approximately, as m G ( ) < < p V Vr if 0 V 0.5V 0 if 0.5V < V < V (3) where G p is the transondutane of the transistor M 36. Let equations (0) and () to be equal; then, we an solve the urrent,, whih is the bias urrent of the ompensation iruit with the ondition of V = V Fig. 5. The approximate linearity approah to find the bias urrent b of the ompensation iruit. Aording to equations (3)-(5) and Fig. 5, a urrent-ompensation iruit, as shown in Fig. 6 is developed. n Fig. 6, M 7, M 8, M 9, and the urrent soure n form the first ompensation iruit, whih is used to ompensate the bias urrent when the duty-yle ontrol voltage V varies between 0.5V and V. Use the approximate approah, the drain urrent of M 8 ( a ) an be desribed approximately, as a 0 n + G n ( V V ) r if 0 < V if 0.5V < 0.5V V V Fig. 6. Current ompensation iruit. n Fig. 6, M 38 and M 39 onstrut a urrent mirror. Assume that the aspet ratios of M 38 and M 39 are equal; then, the drain urrent of these two transistors are equal, i.e. M38 = M39 =. Thus, the drain urrent of M 9 is the sum of a and. M 9 and M 30 also onstrut a urrent mirror. Let M 9 and M 30 have the same aspet ratio; then, M 30 opies the drain urrent of M 9, i.e. M30 = M9 = a +. From equations () and (3) we get = + b a m G n + G n p ( V V ) ( V V ) r r if 0 < V if 0.5V < 0.5V < V < V (4) () n order to ahieve urrent-ompensation purpose, it is neessary to generate the harge urrent p and p to fulfill the

5 An ntegrated Voltage-Mode Boost DC-DC Converter for Portable Eletroni Systems ondition as desribed in equation (5). Transistors M 4 ~M 46 form the urrent p and p generators, whih bias urrent is b, as desribed in equation (4). n Fig. 6, if the transistors M 4 and M 44, M 45 and M 46 are mathed, respetively; then, p and p an be written as = b p + Gmn ( V Vr ) (5) the proposed onverter with the iruit parameters: C =8 nf, C =0.6 nf, R =0 kω, R =6 kω, R f =330 kω, R f =0 kω, L o =0 μh, C o =47 μf, R o =45 Ω, V out =3.6 V, and V g =.5 V, is shown in Fig. 9. The simulation results show that the unit gain frequeny is rad/s and the phase margin is 6 degree. = b p Gmn ( V Vr ) (6) where G mn is the transondutane of M 45. Therefore, we an use urrent mirror to generate p and p for the ring osillator, respetively. n this work, we set bias urrent soures m and n to be the same and equal to. To satisfy the pseudo hyperbola urve urrent ompensation, we an adjust the referene voltages V r =0.5-V, V r =0.75-V, V r =0.5-V, and tune the bias urrent to fulfill the pseudo hyperbola urve urrent-ompensation ondition as desribed in equation (5)... Error amplifier n order to improve stability and dynami response of overall system, the frequeny response of the error amplifier must be ompensated. We an use the error amplifier, as shown in Fig. 7, to generate a ontrolled voltage V for the PWM iruit and ompensate the pole and zero of the DC onverter. Aording to Figs. and 7, the small signal model of the DC onverter an be desribed as shown in Fig. 8. The transfer funtion of this onverter an be written as F () s ( + R C s R C s = V R C s g )( + ) R R f + R f f Vout ( D) (7) Lo + s + LoCos R o Through MATLAB/Simulink simulation, the feedbak-loop frequeny responses of Fig. 7. The error amplifier. Fig. 8. Small signal model of the boost DC onverter. Fig. 9. Feedbak-loop frequeny responses: the upper trae is the loop gain of the boost DC onverter; the bottom trae is the phase margin of the onverter, respetively..3. Non-overlap iruit n order to prevent MOS power transistors (Mp and Mn) of the power onverter onduting simultaneously, a non-overlap driver is required. Fig. 0(a) shows the non-overlap driver and Fig. 0(b) illustrates the output waveform of the

6 龍華科技大學學報第二十四期,007. non-overlap iruit. operated at the swithing frequeny of 500 KHz approximately. Fig. shows the experimental results of the output voltage (V out ), the indutor urrent (i L ), and the swithing lok of the boost onverter at: (a) V out =.5 V and (b) V out =.5 V, respetively, when V g is. V. Fig. 0. The ontrol driving iruit and waveform: (a) non-overlap driving iruit; (b) output waveform of the driver iruit. 3. Experimental results To verify the theoretial analysis, the proposed boost DC-DC onverter had been implemented with a standard 0.35-μm CMOS proess. n the boost onverter, the power lines for the analog and digital parts are separated to redue the digital interferene. The mirograph of the boost onverter with hip area of 0.95 mm is shown in Fig.. (a) (b) Fig.. Steady state experimental results of the proposed onverter at: (a) V g =. V and V out =.5 and (b) V g =. V and V out =.5 V. 3. Line regulation measurement Fig.. Chip mirograph of the onverter 3. Steady-state measurement The boost onverter provides a regulated output voltage that ranges from. to 3.6 V, with a supplied input voltage of. V and a load resistane of Ω. The onverter is To measure the dynami responses, an input voltage V g varies between.8 V and.4 V, alternately is applied to the experimental sheme. Two DC power supplies V g and V g, with a voltage differene of 0.6 V, are supplied to the input of the onverter in omplementary phase. Fig. 3 shows the measurement results of the line regulation. Fig. 3 (a) shows the overall responses of the boost onverter for

7 An ntegrated Voltage-Mode Boost DC-DC Converter for Portable Eletroni Systems the step hanges in the input voltage. Fig. 3(b) and () show the detailed responses of the input voltage step-down and step-up hanges, respetively. The experimental results show that the output voltage variation is less than 5 mv during the supplies input step-down and step-up hange onditions. 3.3 Load regulation measurement (a) As the output load urrent varies, a pulse signal is used to swith the load of the onverter to test the fastest traking speed. When the load of the onverter is swithed between and 6.5 Ω, the loading urrent varies between 50 ma and 00 ma, alternately, with an output voltage of 3.3 V. Fig. 4 shows the measurement results of the load regulation, (a), (b), and () show the overall responses of the boost onverter for the step hanges in loading urrent stephanges, the output voltage responses of the loading urrent step-up, and step-down hange, respetively. The experimental results show that the maximum variation of output voltage V out is 40 mv when the load urrent varies between 50 and 00 ma. 3.4 Effiieny (b) () Fig. 3. Transient response of line regulation: (a) the overall responses of the boost onverter for the step hanges in the input voltage; (b) lose-up of dynamis when V g step-up; () lose-up of the dynamis when V g step-down. n swithing mode DC-DC onverters, the onversion loss is depended on the size of the swithing transistors and the equivalent resistane of the filter elements. For PWM and synhronous retifiation ontrol, ondution loss is dominant at heavy load onditions, but swithing loss is dominant at light load onditions. The effiieny of this work is shown in Fig. 5 with an output voltage of 3.3 V and an input voltage of. V. The maximum effiieny is 9 % at loading urrent to be 80 ma, and its effiieny is kept above 8 % over an output power ranges from 30 to 600 mw. n Fig. 5, the ondution loss is dominant when the loading urrent is larger than 80 ma, and the effiieny dereases with loading urrent inreasing. On the other hand, the swithing loss is dominant when the loading urrent is less than 80 ma, and the effiieny dereases with load urrent dereasing. The overall performanes of the proposed DC onverter are summarized in Table.

8 龍華科技大學學報第二十四期,007. (a) presented. The PWM sheme used in the proposed onverter is a pseudo hyperbola urrent-ompensation ring osillator. Using the on-hip PWM sheme not only redues the external passive omponents of the onverter but also lessens the omplexity of the iruit design. The proposed boost DC-DC onverter an operate with low supply voltage (. V~3.6 V) and features low-power onsumption (600 mw). This boost onverter will be useful in low-voltage and low-power portable systems appliation. (b) () Fig. 4. Load regulation performane: (a) the waveforms of V g and V out ; (b) lose-up of the dynamis when loading urrent step-up; () lose-up of the dynamis when loading urrent step-down. 4. Conlusions A featuring low voltage, new boost DC onverter with on hip CMOS PWM tehnique and power transistors has been Fig. 5. Effiieny at V g =. V and V o =3.3 V. Table. Overall performanes Tehnology TSMC Digital 0.35-μm P4M nput Voltage. V~3.0 V Output Voltage. V~3.6 V Output Current 30 ma~00 ma Swithing Frequeny 300 KHz~.0 MHz Effiieny Max: 9 %; Min: 8% Chip Area Without PAD mm Aknowledgment The authors would like to thank the National Siene Counil for the finanial support by NSC 95--E-6-08 and the Chip mplementation Center for hip fabriation. Referene. Ralph K. and Wentai Liu, Emerging Tehnologies: Design Low Power Digital Systems, Kluwer Aademi

9 An ntegrated Voltage-Mode Boost DC-DC Converter for Portable Eletroni Systems Punlishers, Norwell, Massahusetts, USA, Robert W. Erikson, Fundamental of Power Eletronis, Kluwer Aademi Punlishers, Norwell, Massahusetts, Muhammad H. Rashid, Power Eletronis: Ciruits, Devies, and Appliations, 3e, Pearson Prentie Hall, New Jersey, USA, Donglai Xu, Wendan Xu, and Jianyong Zhang, A Low Power Supply and High Frequeny Driver Design for DC-DC Converter Appliatons, EEE nt. Workshop VLSl Design & Video Teh. Suzhou, China, 8-30 May 005, pp A. Giovanni Beuti, Georgios Papafotiou, and Manfred Morari, Optimal Control of the Boost d-d Converter, Pro. of the 44th EEE Conf. on Deision and Control, and the European Control Conf. Seville, Spain, -5 De. 005, p Mark S. Hooper, Jeff W Hall, and Steve Kenny, A 5MHz Silion CMOS Hierarhial Boost DC-DC Converter Design Using Maromodels for A U Proess, Pro. of the 00 45th Midwest Symp. on Ciruits and Systems, 4-7 Aug. 00, vol., pp Haifei Deng, Nik Sun, Xiaoming Duan, Yan Ma, Alex Q. Huang, and Dan Chen, Design of a monolithi low voltage high effiieny boost DC-DC onverter ASC based on 0.5um CMOS proess, EEE nt. Symp. on Power Semiondutor Devies & Cs, 004, pp Ding Ge and Zhiliang Chen, On-Chip Boost DC-DC Converter in Color OLED Driver & Controller Cs for Mobile Appliation, EEE Pro. of the 6th nt. Conf. on ASC, 4-7 Ot. 005, vol., pp Jiann-Jong Chen, Yeong-Tsair Lin, Hung-Yih Lin, and Wen-Yaw Chung, ntegrated Pulse-width-modulation Ciruit using CMOS Proesses, EEE Pro. of the 35th Annual Power Eletronis Speialists Conf., Aahen, Germany, 004, vol., pp Zheren Lai and Keyue Ma Smedley, A general onstant-frequeny pulse-width modulator and its appliations, EEE Trans. on Ciruits and Systems-: Fundamental Theory and Appliations, vol. 45, no. 4, pp , Siew-Chong Tan, Y.M. Lai, Martin K. H Cheung, and Chi K. Tse, A pulsewidth-modulation based sliding mode ontroller for buk onverters, EEE Pro. of the 35th Annual Power Eletronis Speialists Conf., Aahen, Germany, 004, vol. 5, pp Albert M. Wu, Jinwen Xiao, Dejan Markovi, and S.R. Sanders, Digital PWM ontrol: appliation in voltage regulation modules, EEE Pro. of the 30th Annual Power Eletronis Speialists Conf., Charleston, 999, vol., pp Chung-Hsien Tso and Jiin-Chuan Wu, An integrated digital PWM DC/DC onverter using proportional urrent feedbak, EEE nt. Symp. on Ciruits and Systems, Sydney, Australia, 00, vol. 3, no., pp T. Yokoyama and A. Kawamura, Disturbane observer based fully digital ontrolled PWM inverter for CVCF operation, EEE Trans. on Power Eletronis, vol. 9, no. 5, pp , Sept Vitor Anuniada and Manuel M. Silva, New onstant-frequeny urrent-mode ontrol for power onverters, EEE Trans. on ndustrial Eletronis, vol. 37, no. 4, pp , Aug P. Midya, P. T. Krein and M. F. Greuel, Sensorless Current Mode Control an Observer-Based Tehnique for DC-DC Converters, EEE Trans. on Power Eletronis, vol. 6, no. 4, pp. 5-56, July Mei-Chu Jen, Yeong-Tsair Lin, Jiann- Jong Chen, Dong-Shiuh Wu, and Ho- Cheng Lin, The Design of an ntegrated CMOS Boost DC-DC Converter, Pro. of the 6th Taiwan Power Eletronis Conf. & Exhibition, Chainhua, Taiwan, 9 Sept. 007, pp

10 龍華科技大學學報第二十四期,007. 適用於行動電子系統電壓模式升壓型直流 - 直流轉換器積體電路 鄭美珠 吳東旭 林永裁 林和正 龍華科技大學電子程系台北科技大學電腦與通訊研究所 陳建中 摘要 本文提出嵌入脈波寬度調變電路與功率開關電晶體的電壓模式升壓型直流 - 直流轉換器 使用於轉換器的脈波寬度調變電路, 以虛擬雙曲線電流補償器加以控制, 使其作用週期 (duty yle) 不但可以控制而且振盪頻率可以維持大約為定頻 本文所提出的電路已成功的使用台灣積體電路公司 (TSMC) 的 0.35-μm P4M CMOS 製程技術完成設計與製造, 晶片面積為 0.95 mm, 實際量測結果顯示此升壓型轉換器可正常的操作, 並符合下列的規格 : 輸入電壓範圍為. V 到 3.0 V; 當輸入電壓為. V 時, 其輸出電壓範圍為. V 到 3.6 V; 最大轉換效率為 9 %; 輸出功率介於 30 mw~600 mw 時, 其轉換效率都可維持在 8 % 以上 關鍵詞 : 脈波寬度調變 環型振盪器 電壓模式 升壓型直流 - 直流轉換器