Study Guide for the First Exam
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1 Study Guide or the First Exam Chemistry 838 Fall 005 T V Atkinson Department o Chemistry Michigan State Uniersity East Lansing, MI 4884 The leel o knowledge and detail expected or the exam is that o the lectures. Items marked with * are beyond the scope o this exam but included or general interest. The exact scope o the exam will be deined the week o the exam in order to relect what was actually coered this term. 1. Data Domains 1.1. Be able to discuss the concepts o measurement and control as deined in class. What are the major components o an experiment? What is the low o inormation? 1.. Be able to discuss in general: input transducers, put transducers, data domain conerters, and interaces Be able to discuss data domain maps. You will not be required to create the general map, but be prepared to draw such a map or a gien experimental setup i you are gien the general map and the descriptions o all transducers and data domain conerters inoled.. Oscilloscopes.1. Be able to discuss the CRT including the main components. What is meant by x-axis, y- axis, z-axis?.. Be able to discuss the use o a CRT to produce an x-y plot o two time arying signals, both periodic and ixed length in time. What are Lissajous igures?.3. Be able to discuss the concept o horizontal sweep, i. e. the use o a standard time base or one axis o the CRT..4. What is meant by z-axis blanking? Synchronized time base? Flyback?.5. Be able to discuss triggering: trigger eent; trigger mechanism; time course or x- and z- axes; internal, external, line sources; slope; threshold..6. Be able to discuss multiple traces and alternate and chopped modes..7. Be able to discuss DC and AC coupling. October 11,
2 3. DC Circuit Analysis 3.1. Ohm s Law Be able to state and utilize. 3.. Kircho s Current and Voltage Laws - Be able to state and utilize Simple Deices (symbol, transer unction, and applications; real and ideal): Voltage Sources, Resistors, Conductors, Capacitors, Voltage Sensing deice, 3.4. Be able to sole or the behaior o combinations o two, three or more resistors Theenin s Theorem - Be able to state and discuss. You will NOT be asked to do a deriation os the Theenin Equialent circuit or a gien circuit such as done in class, but you might be asked to discuss that deriation Loading (Current and Voltage) - Be able to discuss the concept and apply to situations such as coered in class. 4. AC Circuit Analysis 4.1. Be able to state and discuss the concepts: periodic and aperiodic signals; the unctional and graphic description o a sine wae; the amplitude, requency, and phase o a sine wae. 4.. Be able to discuss the response o the RC circuit to a step unction, including the graphical and unctional description o the charging and discharging cases Be able to discuss the steady state response o the RC circuit to a sine wae, including the unctional and graphical orms o the puts across the resistor and the capacitor Be able to discuss high pass, low pass, band pass, and notch ilters. Be able to produce a Bode plot or a high pass or low pass irst order RC ilter For what purposes are ilters used? 5. Power Supplies 5.1. Transormer - Be able to identiy, reproduce and/or utilize the name and schematic or simple, multiple secondary windings, and center tapped transormers. Be able to manipulate the oltage/turn ratio relationships and sketch the input and put waeorms. 5.. Rectiier - Be able to identiy, reproduce and/or utilize the name, schematic, and operating characteristics or the hal wae, ull wae/center tapped and ull wae/bridge rectiiers based on the use o "ideal" diodes Filter - Be able to identiy, reproduce and/or utilize the name, schematic, transer unction, and operating characteristics o a simple irst order (RC) low pass ilter. Tuesday, October 11,
3 5.4. Regulator - Be able to identiy, reproduce and/or utilize the name, schematic, and operating characteristics o a series linear regulator and the shunt regulator Diodes - Know the generalized characteristic cure (i s ) or a diode. Be able to identiy and discuss the signiicance o the three operating regions o a diode: aalanche, reerse bias, orward bias. Be able to discuss the common uses o diodes: switching, power, light sensitie, temperature sensitie, zener. 6. Operational Ampliiers 6.1. You will NOT be asked to do any o the deriations done in class. 6.. Be able to identiy and/or reproduce the name, schematic, and transer unction (both algebraic and graphical orms) or each o the operational ampliier conigurations: comparator, ollower, ollower with gain, inerter, summing amp, integrator, dierentiator, dierence, and potentiostat. These conigurations are illustrated in Figure 1. For each o these conigurations, you should also be able to apply the transer unction to problems such as the next problems. Tuesday, October 11,
4 Table 1 - Voltage Input OA Conigurations Coniguration Schematic Transer Function comparator Figure 1-a Is >? Yes: = V oh No: = V ol ollower Figure 1-b = in ollower with gain Figure 1-c inerter Figure 1-d summing amp Figure 1-e Integrator Figure 1- Integrator with Oset Figure 1-g dierentiator Figure 1-h dierence Figure -h potentiostat Figure -i R1 + R = 1 R1 R = 1 R1 = n i= 1 R i R i 1 = dt R C = 1dt R C 1 = R C d 1 dt R = R 1 = 1 ( ) 1 a re R1 R = + re R R R potentiostat Figure -k potentiostat Figure -l a a R R = 1 + R1 R R R = 1 + R1 R 6.3. Figure 1 illustrates 1 dierent OA circuits. Figures -a, -b, and -c illustrate 9 oltage signals as a unction o time. Table contains alues or the arious parameters o these circuits to be used in this problem. Tuesday, October 11,
5 This exercise consists o connecting a gien time arying oltage signal rom the set illustrated in Figure to the input o a gien circuit rom Figure 1 and sketching the resultant signal,, that would appear at the put o that circuit. A blank plot is proided or your conenience right below each input signal. You might want to make copies o the three pages o Figure, since you may want to apply the same signal to more than one coniguration. For the conigurations with multiple inputs, try using one o the time arying signals or one input and a constant oltage or the other. Assume that the OA's ollow the irst order model, i.e. i+ = i- = 0 and eo = A(e+ - e-), and eo is bounded by Vol and Voh. Assume that Vol = -1 and Voh = +1. Assume that all capacitors are discharged at t = 0. [Note: The intention is not or you to necessarily to do all 1*9 permutations. Rather, you should do seeral combinations o one OA coniguration and arious input signals. Then repeat the process or seeral dierent conigurations. Once you know the procedure and i you know the transer unctions o the circuits, you should be able to easily derie the behaior o any o the circuits to time arying signals.] Table Circuit Parameters or OA Conigurations in Figure Circuit a b c d e g h i j k l Parameters = +.0 olts = 10KΩ, = 10KΩ = 10KΩ, R = 0KΩ = 10KΩ, = 10KΩ, R = 10KΩ, = -.0 R in = 1MΩ, C = 0.1μF = 1MΩ, = 1MΩ, C = 0.1μF R = 1MΩ, C 1 = 0.1μF = 10KΩ, R = 0KΩ = 10KΩ, = 10KΩ = 10KΩ, = 10KΩ, R 3 = 0KΩ, R 4 = 15KΩ = 10KΩ, = 10KΩ, R 3 = 0KΩ, R 4 = 15KΩ 6.4. *The input, 1, o a ollower (Figure 1b) is connected directly to common. The put,, is measured to be 37.5 milliolts. The input, 1, is then connected to ground through a MΩ resistor. The put is then measured to be 45.0 milliolts. What is the oset or the OA? What is i+? Tuesday, October 11,
6 OA1.cdr 11-October 11, 005 (a) (b) R (c) (d) R C (e) () C C R (g) Figure 1 - Operational Ampliier Conigurations (h) Tuesday, October 11,
7 OA.cdr 11-October 11, 005 R re (i) R (j) a R R R 3 R 3 (k) a R 4 a (l) R 4 Figure - Operational Ampliier Conigurations (cont.) 6.5. A ollower is to be used to buer a real oltage source rom a real oltage meter. Rs is 3 KΩ. Vs is.5 olts. i+ or the ollower is 10-9 amps. Rm or the meter is 10 KΩ. iol or the ollower OA is 0 milliamp. What would the oltage be at the put o the OA i the meter was not connected? Can the OA drie the meter? Explain What are the primary characteristics o the basic operational ampliier? 6.7. What is the circuit symbol or the operational ampliier? Tuesday, October 11,
8 6.8. Why is one o the inputs called the inerting input? 6.9. What determines the put oltage limits o the OA? What condition exists at the OA inputs when the put is not at limit? What is the circuit and what are the characteristics o the oltage ollower? 6.1. Draw the circuit o a oltage ollower with a gain o 100? Assuming an put limit o ± 1V or the aboe ampliier, what are the input signal limits or linear operation? *I the raw gain o the OA in the aboe ampliier is 10 6, by what actor does the gain deiate rom the expected alue o 100? *I the resistors in the aboe ampliier hae an accuracy o 0.1%, how will this aect the gain accuracy? The gain precision? Deend the statement that the oltage ollower presents a nearly ideal load to a oltage source Design a current ollower that will produce a 1V put or an input current o 10-7 A Deend the statement that the current ollower presents a nearly ideal load to a current source How does an inerting ampliier with a gain o 1 dier rom a oltage ollower? 6.0. Design an inerting ampliier with a gain o What is input resistance o the aboe ampliier? 6.. Design a summing ampliier with an put that is -( ) *What are the main considerations in choosing the resistor alues or the aboe ampliier? 6.4. Draw the circuits or and describe the unction o the integrator and the dierentiator Design an integrator circuit that will produce a sweep signal with an put sweep rate o 10 V per second. 7. Digital Logic Circuits Make truth tables or the AND, OR, and NOT unctions. 7.. Draw the symbols or the AND and OR gates and the NOT circuit and make their tables o states. Tuesday, October 11,
9 7.3. Deend the statement that all logic unctions can be accomplished with a combination o AND, OR, and NOT unctions Deine HI and LO or logic leel signals What is the truth table, symbol, and sign or the exclusie-or unction? 7.6. Why are AND and OR circuits called gates? 7.7. Describe the one unction o a data latch Be able to apply the generic lip lop described in class including symbol, input and put signals, operation, table o states, and timing diagrams Be able to couple an arbitrary number o the generic lip lops and generate the table o states and timing diagrams or the combinations. Analog Signal Processing What are the characteristics o an ideal switch? What are the characteristics o a real mechanical switch? What is bounce? "Bounce" is a concern in which contexts? Why? 7.1. What are the characteristics o a real solid-state switch? What is the time behaior o a real solid-state switch? Describe the switching circuits inoled in making a sweep generator rom a constant oltage source and an OA integrator Design a circuit that will generate a true symmetrical triangular wae based on an OA integrator *Be able to assess the error caused by open and closed switch resistance in signal switching applications Understand the operation o the Monostable Multi-ibrator. You will not hae to reproduce the schematic diagram or the timing diagrams used in the deriation. Be able to reproduce and identiy the symbol used or the 1 Shot or monostable. Be able to describe the timing relationship o the input and put signals o the deice. Be able to qualitatiely describe the relationship o the timing o these signals with the alues o the resistance and capacitance used. Be able to derie the behaior o combinations o monostables to achiee a set o signals with arying timing relationships, i.e. delays, and pulse widths Be able to identiy and/or reproduce the name, schematic, and transer unction or the analog multiplexer. What are the operational constraints that dierentiate the analog multiplexer rom the summing amp? How is this circuit used? Tuesday, October 11,
10 7.18. Be able to discuss the phenomena called cross talk. 8. Time and Frequency Measurement 8.1. Asynchronous binary counters 8.. Asynchronous counters o arbitrary modulus 8.3. Crystal stabilized clock, ariable put and programmable clock 8.4. Time and Frequency measurement Understand, be able to reproduce, and apply the operation o the simple circuit used or time, period, requency, period ratio, and requency ratio measurement. Tuesday, October 11,
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