AP3598A 21 PVCC 15 VCC 9 FS HGATE1 BOOT1 PHASE1 23 LGATE1 16 PGOOD R LG1 3 EN 4 PSI 5 VID 8 VREF HGATE2 18 BOOT2 19 PHASE2 7 REFIN LGATE2 6 REFADJ

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1 APPLICATION NOTE 24 COMPACT DUAL-PHASE SYNCHRONOUS-RECTIFIED BUCK CONTROLLER General Description The is a dual-phase synchronous buck PWM controller with integrated drivers which are optimized or high perormance graphic card and computer applications. The IC is capable o delivering up to 60A output current capability and supporting 2 MOSFET drivers with internal bootstrap diodes. The dynamic output voltage could be implemented by analog method with a switching device and a resistor network. The adjustable current balance is achieved by R DS(ON) current sensing technique. The provides over current protection, input/output under voltage protection, over voltage protection and over temperature protection. Other eatures include adjustable sot start, adjustable operation requency and so on. With aorementioned unctions, the IC adopts U-QFN package. E Board Schematic CC R PG C REF Supply oltage C CC R EN R PSI2 R PSI Frequency Selection R FS 5 CC 9 FS 6 PGOOD 3 EN 4 PSI 5 ID 8 REF 2 PCC HGATE 2 BOOT PHASE LGATE HGATE2 7 8 BOOT2 9 PHASE2 R LG Driver Supply oltage R HG C BT C BT2 C PCC R HG2 Optional Strap PCC G G G D S D S D S D Q Q2 Q3 Q4 C L C C 2 L2 REF R TALERT R TM2 R REF R REF2 R REFADJ C REF 7 REF 6 REFADJ LGATE2 SNS 20 0 G S R R _SNS 4 TALERT# SNS 2 COMP R C3 C4 C5 R2 R3 _SNS R TM External Thermister 3 TSNS THERM/ Opamp Compensation Rev..0 o 5 204

2 Application Inormation Component alue Unit Component alue Unit Component alue Unit C CC 0 µf R TALERT 00 kω C3 0 pf C PCC 0 µf R TM2 TBD kω C4 2.2 nf C 300 µf R TM TBD kω C5.5 nf C µf R HG 0 Ω C 330*3 µf R PG 00 kω C BT 00 nf R 0 Ω R EN 00 kω R LG Note Ω R 0 Ω R FS 33 kω R HG2 0 Ω C REF µf R PSI 00 kω C BT2 00 nf Q R PSI2 0 kω R 2 kω Q2 C REF µf R2 2.2 kω Q3 R REF 4.75 kω R3 560 Ω Q4 R REF kω L 0.36 µh R REFADJ 6.34 kω L µh Table. Component Guide Note : R LG are OCP setting resisters: 5k or lower OCP threshold, I OCP=50m/R DS(ON) 0k or medium OCP threshold, I OCP=250m/R DS(ON) >20k or disabling OCP unction PWM-ID Dynamic oltage Control PWM-ID is a single-wire dynamic voltage control circuit driven by the pulse width modulation method. This circuit reduces the device pin count and enables a wide dynamic voltage range. The PWM-ID duty cycle determines the variable output voltage at REF, as shown in Figure. M is the zero percent duty cycle voltage value. MAX is the one hundred percent duty cycle voltage value. The resolution o each voltage step ( STEP) is determined by the number o available steps (N MAX) and the selection o the dynamic voltage range ( MAX- M). N is the number o steps at a speciic. N/N MAX ratio is equal to the duty cycle. The dynamic voltage ID requency ( SWID) is determined by the unit pulse width (t U) and the available step number N MAX (t ID = t U*N MAX, ID = / t ID). t U is programmable. Figure. Dynamic Output Rev..0 2 o 5 204

3 STEP, N MAX, M, and MAX are variables that determine. N MAX is limited by the unit pulse width and the minimum ID requency. The dynamic voltage output could be implemented by the analog method with a switching device and a resistor network. A buer is used as the switching device to create dynamic output. Resistor network sets the minimum oset voltage. Figure 2 shows the analog circuit diagram or the PWM-ID dynamic voltage control. The buer requires a stable, high precision voltage reerence ( REF) or the linear output. The dynamic range o the circuit is determined by the resistor selection. Resistor R REFADJ and capacitor C REF unction as a ilter or the PWM signal, and will aect the ripple voltage and the slew rate at the output (REF) during voltage transitions. REF CC PWM A Buer OE R REFADJ R REF REF NC C REF R REF2 Figure 2. PWM-ID Analog Circuit Diagram Spec Description Output oltage Equation N MAX: Total available voltage step number N: The step number o the speciic, N/N MAX ratio equals duty cycle MAX: The output voltage o REF at one hundred percent duty cycle M: The output voltage o REF at zero percent duty cycle STEP: The resolution o the voltage step : The output voltage at REF SWID: The dynamic voltage ID requency REF REF R R REF2 REF R REF2 ( R REF R REFADJ ) RREF2 RREFADJ ( R R ) MAX REF2 MAX - M N M N t U N MAX STEP REFADJ Table 2. REF Dynamic Range There will be some ripple voltage at REF due to the nature o the PWM and ilter. The error ampliier at REF will be able to tolerate a reasonable amount o Ripple oltage. Figure 3 shows a dynamic voltage control circuit with the integrated buer. This deines the implementation o the ID and REFADJ unctions. Rev..0 3 o 5 204

4 Controller REF R REF REF STANDBY Block External Control R5 R STANDBY D Q5 G S RREF2 R REFADJ C REF PWM REFADJ ID OE O NC CCBuer A Figure 3. Integrated Buer Circuit Figure 4. The Behavior o the Buer Rev..0 4 o 5 204

5 Parameters Sym Min Typ Max Unit Notes Buer Supply oltage REF Unit Pulse Width t U 27 ns Conigurable Buer Output Rise Time t R 5 ns Buer Output Fall Time t F 5 ns Rising and Falling Edge Delay Δt 0.5 ns Δt= t R-t F Propagation Delay t PD 0 ns t PD=t PHL=t PLH Propagation Delay Error Δt PD 0.5 ns Δt PD=t PHL-t PLH Upper Resister R REF 4.75 kω Lower Resister R REF kω Filter Resister R REFADJ 6.34 kω Boot Mode Resister R BOOT kω Project Speciic Standby Mode Resister R STANDBY.07 kω Filter Capacitor C REF μf Table 3. Electrical Characteristics Figure 5 contains the details o the timing diagram. Ater CC powers up, the controller generates the REF. REF settles at BOOT beore the GPU drives the ID pin. Ater the GPU powers up, BOOT control will be pulled low by sotware. At the same time the ID is driven by a PWM signal, moving REF into the normal operating mode. When the GPU is going to standby, sotware will tri-state ID and BOOT control, and an external control will enable R STANDBY. Figure 5. Time Diagram Standby mode keeps the GPU in a low voltage state (in the range o 0.3) or the quick recovery. As the GPU steps into the standby mode, the resistor R STANDBY and the switch Q6 (parallel to the R REF2 and R BOOT) set the standby voltage. The accuracy o the reerence voltage in the standby mode could be reduced rom the normal operating mode. Reer to Figure 6 or the illustration o the standby voltage. Rev..0 5 o 5 204

6 Figure 6. Illustration or Standby Mode and Adjustable BOOT Setting PWM Compensation The output LC ilter o a step down converter introduces a double pole, which contributes with -40dB/decade gain slope and 80 degrees phase shit in the control loop. A compensation network among COMP, SNS, and should be added. The compensation network is shown in Figure 0. The output LC ilters consist o the output inductors and output capacitors. For two-phase convertor, when assuming that = 2 =, L = L2 = L, the transer unction o the LC ilter is given by: Gain LC s 2 s RESR C (/ 2) L C s R ESR C The poles and zero o the transer unctions are: LC 2 (/ 2) LC ESR 2 R ESR C The LC is the double-pole requency o the two-phase LC ilters, and ESR is the requency o the zero introduced by the ESR o the output capacitors. PHASE L=L PHASE2 L2=L C R ESR Figure 7. The Output LC Filter Rev..0 6 o 5 204

7 Figure 8. Frequency Response o the LC Filters The PWM modulator is shown in Figure 9. The input is the output o the error ampliier and the output is the PHASE node. The transer unction o the PWM modulator is given by: Gain PWM OSC Δ OSC OSC PWM Comparator - + Driver PHASE Output o Error Ampliier Driver Figure 9. The PWM Modulator The compensation network is shown in Figure 0. It provides a close loop transer unction with the highest zero crossover requency and suicient phase margin. The transer unction o error ampliier is given by: Gain AMP COMP //( R2 ) ( s ) { s } sc sc2 R R3 R2 C2 ( R R3) C3 R R3 C C C2 R//( R3 ) s( s ) ( s ) sc3 R2 C C2 R3 C3 The pole and zero requencies o the transer unction are: Z 2 R2 C2 Rev..0 7 o 5 204

8 Z 2 P P 2 2 ( R R3) C3 C C2 2 R2 ( ) C C2 2 R3 C3 C R3 C3 R2 C2 R FB - + COMP REF Figure 0. Compensation Network The closed loop gain o the converter can be written as: Gain LC Gain PWM Gain AMP Figure shows the asymptotic plot o the closed loop converter gain, and the ollowing guidelines will help to design the compensation network. Using the below guidelines will give a compensation similar to the curve plotted. A stable closed loop has a -20dB/decade slope and a phase margin greater than 45 degree.. Choose a value or R, usually between kω and 5kΩ. 2. Select the desired zero crossover requency. (/5 ~ /0) O SW Use the ollowing equation to calculate R2: OSC O R2 R LC 3. Place the irst zero Z beore the output LC ilter double pole requency LC Z LC Calculate the C2 by the equation: Rev..0 8 o 5 204

9 C2 2 R2 LC Set the pole at the ESR zero requency ESR: P ESR Calculate the C by the ollowing equation: C2 C 2 R2 C2 ESR 5. Set the second pole P2 at the hal o the switching requency and also set the second zero Z2 at the output LC ilter double pole LC. The compensation gain should not exceed the error ampliier open loop gain. Check the compensation gain at P2 with the capabilities o the error ampliier. P Z 2 LC SW Combine the two equations will get the ollowing component calculations: R3 R SW 2 LC C3 R3 SW Figure. Converter Gain and Frequency Rev..0 9 o 5 204

10 Output Inductor Selection The duty cycle (D) o a buck converter is the unction o the input voltage and output voltage. Once an output voltage is ixed, it can be written as: D / For two-phase converter, the inductor value (L) determines the sum o the two inductor ripple current, ΔI P-P, and aects the load transient response. Higher inductor value reduces the output capacitors ripple current and induces lower output ripple voltage. The ripple current can be approximated by: 2 I P P SW L Where SW is the switching requency o the regulator. Although the inductor value and requency are increased and the ripple current and voltage are reduced, a tradeo exists between the inductor s ripple current and the regulator load transient response time. A smaller inductor will give the regulator a aster load transient response at the expense o higher ripple current. Increasing the switching requency ( SW) also reduces the ripple current and voltage, but it will increase the switching loss o the MOSFETs and the power dissipation o the converter. The maximum ripple current occurs at the maximum input voltage. A good starting point is to choose the ripple current to be approximately 30% o the maximum output current. Once the inductance value has been chosen, select an inductor that is capable o carrying the required peak current without going into saturation. In some types o inductors, especially core that is made o errite, the ripple current will increase abruptly when it saturates. This results in a larger output ripple voltage. Output Capacitor Selection Output voltage ripple and the transient voltage deviation are actors that have to be taken into consideration when selecting output capacitors. Higher capacitor value and lower ESR reduce the output ripple and the load transient drop. Thereore, selecting high perormance low ESR capacitors is recommended or switching regulator applications. In addition to high requency noise related to MOSFET turn-on and turn-o, the output voltage ripple includes the capacitance voltage drop Δ C and ESR voltage drop Δ ESR caused by the AC peak-to-peak sum o the inductor s current. The ripple voltage o output capacitors can be represented by: C I 8 C PP SW ESR I PP R ESR These two components constitute a large portion o the total output voltage ripple. In some applications, multiple capacitors have to be paralleled to achieve the desired ESR value. I the output o the converter has to support another load with high pulsating current, more capacitors are needed in order to reduce the equivalent ESR and suppress the voltage ripple to a tolerable level. A small decoupling capacitor in parallel or bypassing the noise is also recommended, and the voltage rating o the output capacitors must be considered too. To support a load transient that is aster than the switching requency, more capacitors are needed or reducing the voltage excursion during load step change. For getting same load transient response, the output capacitance o two-phase converter only needs to be around hal o output capacitance o single-phase converter. Another aspect o the capacitor selection is that the total AC current going through the capacitors has to be less than the rated RMS current speciied on the capacitors in order to prevent the capacitor rom overheating. Rev..0 0 o 5 204

11 Input Capacitor Selection Use small ceramic capacitors or high requency decoupling and bulk capacitors to supply the surge current needed each time high-side MOSFET turns on. Place the small ceramic capacitors physically close to the MOSFETs and between the drain o high-side MOSFET and the source o lowside MOSFET. The important parameters or the bulk input capacitor are the voltage rating and the RMS current rating. For reliable operation, select the bulk capacitor with voltage and current ratings above the maximum input voltage and largest RMS current required by the circuit. The capacitor voltage rating should be at least.25 times greater than the maximum input voltage and a voltage rating o.5 times is a conservative guideline. For twophase converter, the RMS current o the bulk input capacitor is roughly calculated as the ollowing equation: I RMS I 2 2D ( 2D) For a through-hole design, several electrolytic capacitors may be needed. For surace mount design, solid tantalum capacitors can be used, but caution must be exercised with regard to the capacitor surge current rating. MOSFET Selection The requires two N-Channel power MOSFETs on each phase. These should be selected based upon R DS(ON), gate supply requirements and thermal management requirements. In high current applications, the MOSFET power dissipation, package selection, and heatsink are the dominant design actors. The power dissipation includes two loss components: conduction loss and switching loss. The conduction losses are the largest component o power dissipation or both the high-side and the low-side MOSFETs. These losses are distributed between the two MOSFETs according to duty actor (see the equations below). Only the high-side MOSFET has switching losses since the low-side MOSFETs body diode or an external Schottky rectiier across the lower MOSFET clamps the switching node beore the synchronous rectiier turns on. These equations assume linear voltage current transitions and do not adequately model power loss due to the reverse-recovery o the low-side MOSFET body diode. The gate-charge losses are dissipated by and don t heat the MOSFETs. However, large gatecharge increases the switching interval t SW, which increases the high-side MOSFET switching losses. Ensure that all MOSFETs are within their maximum junction temperature at high ambient temperature by calculating the temperature rise according to package thermal resistance speciications. A separate heatsink may be necessary depending upon MOSFET power, package type, ambient temperature and air low. For the high-side and low-side MOSFETs, the losses are approximately given by the ollowing equations: Where I is the load current, T C is the temperature dependency o R DS(ON), SW is the switching requency, t SW is the switching interval, D is the duty cycle. Note that both MOSFETs have conduction losses while the high-side MOSFET includes an additional transition loss. The switching interval, t SW, is the unction o the reverse transer capacitance C RSS. The (+T C) term is a actor in the temperature dependency o the R DS(ON) and can be extracted rom the R DS(ON) vs. Temperature curve o the power MOSFET. Rev..0 o 5 204

12 PCB Layout Guidance In any high switching requency converter, a correct layout is important to ensure proper operation o the regulator. With power devices switching at higher requency, the resulting current transient will cause voltage spike across the interconnecting impedance and parasitic circuit elements. As an example, consider the turn-o transition o the PWM MOSFET. Beore turn-o condition, the MOSFET is carrying the ull load current. During turn-o, current stops lowing in the MOSFET and is reewheeling by the low side MOSFET and parasitic diode. Any parasitic inductance o the circuit generates a large voltage spike during the switching interval. In general, using short and wide printed circuit traces should minimize interconnecting impedances and the magnitude o voltage spike. Besides, signal and power grounds are to be kept separating and inally combined using ground plane construction or single point grounding. The best tie-point between the signal ground and the power ground is at the negative side o the output capacitor on each channel, where there is less noise. Noisy traces beneath the IC are not recommended. Figure 2 illustrates the layout, with bold lines indicating high current paths; these traces must be short and wide. Components along the bold lines should be placed close together. Below is a checklist or your layout:. Keep the switching nodes (HGATEx, LGATEx, BOOTx, and PHASEx) away rom sensitive small signal nodes since these nodes are ast moving signals. Thereore, keep traces to these nodes as short as possible and there should be no other weak signal traces in parallel with theses traces on any layer. 2. The signals going through theses traces have both high dv/dt and high di/dt with high peak charging and discharging current. The traces rom the gate drivers to the MOSFETs (HGATEx and LGATEx) should be short and wide. 3. Place the source o the high-side MOSFET and the drain o the low-side MOSFET as close as possible. Minimizing the impedance with wide layout plane between the two pads reduces the voltage bounce o the node. In addition, the large layout plane between the drain o the MOSFETs ( and PHASEx nodes) can get better heat sinking. 4. For experiment result o accurate current sensing, the current sensing components are suggested to place close to the inductor part. To avoid the noise intererence, the current sensing trace should be away rom the noisy switching nodes. 5. Decoupling capacitors, the resistor-divider, and the boot capacitor should be close to their pins. (For example, place the decoupling ceramic capacitor as close as possible to the drain o the high-side MOSFET). The input bulk capacitors should be close to the drain o the high-side MOSFET, and the output bulk capacitors should be close to the loads. 6. The input capacitor s ground should be close to the grounds o the output capacitors and the low-side MOSFET. 7. Locate the resistor-divider close to the REF and REF pins to minimize the high impedance trace. In addition, SNS pin traces can t be close to the switching signal traces (HGATEx, LGATEx, BOOTx, and PHASEx). Rev..0 2 o 5 204

13 PCB Layout Guidance (Cont.) Figure 2. The Layout o Rev..0 3 o 5 204

14 PCB Layout Example Top Layer Bottom Layer CC Ldayer Ground Layer Rev..0 4 o 5 204

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