WELDING POWER SUPPLY WITH IMPROVED POWER QUALITY

Transcription

1 OL., NO. 6, AUGUST 7 ISSN Asian Rsarch Publishg Ntwork (ARPN). All rights rsrvd. WELDING POWER SUPPLY WITH IMPROED POWER QUALITY Srividya A. S., S. Malathi and J. Jayachandran Dpartmnt o Elctrical and Elctronics Engrg, SASTRA Univrsity, India ABSTRACT A switchd mod powr supply or Manual Mtal Arc Wldg (MMAW) is proposd this papr. This is don as a mparativ study, usg two dirnt nvrtrs at th ront nd - namly, Zta nvrtr and Canonical Switchg Cll nvrtr. Both th nvrtrs oprat disntuous ductor currnt mod (DICM) to acmplish hrnt Powr Factor Corrction (PFC). This mod o opration rducs th tricacy o ntrol and provids nsidrabl -voltag rgulation. A puls width modulatd (PWM) isolatd ull bridg - nvrtr is usd at th load sid, or both th dsigns to provid high rquncy isolation. A closd loop ntrol is bg nvisagd to rporat voltag rgulation at th output and to provid ovr currnt protction, so that th dsigns ar suitabl or th tndd application. Th dsigns hav bn simulatd and th rsults obtad show how ths two dsigns satisy th rquirmnt o th powr supply or arc wldg procss. Th prormanc o th two powr supplis hav bn valuatd on th basis o powr supply currnt, dynamic charactristics, powr actor and voltag rgulation. Kywords: cll nvrtr, canonical switchg, voltag rgulation, puls width modulation.. INTRODUCTION Wldg is on o th most important procss manuacturg dustris. Thr ar svral wldg tchniqus, among which, arc wldg is th most mmonly usd abrication procsss. Svral dustris lik th automotiv, nstruction, chmical, powr gnration tc immnsly dpnd on this procss and a major amount o lctrical powr is nsumd by ths powr supplis. Thr ar two major orms o arc wldg powr supply - on with output, and anothr with output. A powr supply has currnt and voltag at a stady polarity. This givs a stabl arc and a smooth wld mparison to th powr supply with an ac output. An ac output powr supply dos not hav a stady polarity voltag or currnt, which is suitabl only or alumium wldg []. Th quality o th wld ssntially rlis on th powr supply dployd. Th powr supplis or th Wldg procss can b dsignd usg svral nigurations o circuits. A gnral Arc Wldg Powr Supply (AWPS) mploys an unntrolld diod bridg rctiir, which is traild by a larg -lk capacitor, at th ront nd. Th powr quality dics wr masurd or th nvntional powr supply (powr actor, total harmonic distortion o th put currnt) and it was obsrvd that th xistg powr supplis hav a low powr actor (PF) and larg harmonic currnts. This causs crasd losss th utility sid. Subsqunt works ld to dvlopmnt o Powr Factor Corrction basd AWPS with bttr powr quality [], [3]. Th Wldg Powr Supplis must yild a low valu o THD and a high PF as pr IEC 6-3- and IEEE standards [4]. As ar as th AWPS is ncrnd, ast dynamic rspons and short circuit/ovr currnt protction ar th most mandatory aturs. Th AWPS is dsignd basd on it ovrcurrnt rspons, arc stability, tc. For satisactory wld prormanc, a wldg powr supply with a nstant arc lngth, nstant output voltag and currnt is chosn, as mntiond abov [5]. Howvr, th ormost atur o th wldg powr supply is to provid output voltag rgulation and to limit th output currnt, so as to provid a high quality wld. Svral topologis can b usd or dsigng a powr supply or wldg application. A powr supply dsignd with a boost nvrtr has crta drawbacks, lik high currnt at start-up. It also has not output currnt limitg capability. Th ky actors o wldg powr supply ar not mplid. A buck nvrtr is also proposd [6], but aga hr, th capacitors usd ar o larg valu. Th switchs usd ths nvntional nvrtrs ar switchd at a high rquncy, causg voltag strss across th switch and also crass switchg losss. Morovr, it dos not match th high rquncy mmutation currnt. This drawback hamprs th us o powr supplis dsignd basd on hal/ull bridg vrtrs. Nxt up, buck-boost nvrtrs or bttr prormanc than th abov mntiond nvrtrs. arious sgl stag isolatd PFC nigurations can b mpard with two stag nvrtrs. Among th svral topologis, th Zta and CSC or bttr powr actor rrction. Th abov mntiond problms ar takn car o th proposd niguration. In cas th ductor is dsignd to oprat ntuously, i.., Contuous Conduction Mod (CCM) as prsntd [7], an additional put currnt snsg is rquird to imbib powr actor rrction. Morovr, opratg th nvrtrs DICM mod has radicatd th xtra currnt snsg atur, which adds to th mplxity o th dsign. To or a wid rang o opration, th DICM is ound to b suitabl by usg rducd numbr o mponnts and snsg circuitry tc. Furthr, a dback circuitry has bn rporatd to handl ovrcurrnt th powr supply. This hlps achivg an improvd wld quality. In short, th nvrtr can b usd to ntrol svral paramtrs, lik th wldg currnt, voltag, triggr puls duty cycl, limit o ovrload currnt, and so on. Th prormanc o th two nvrtrs has bn vriid by modllg th dsign MATLAB/Simulk nvironmnt. Th simulatd rsults ar ound to nirm 475

2 OL., NO. 6, AUGUST 7 ISSN Asian Rsarch Publishg Ntwork (ARPN). All rights rsrvd. th practical usability o th nvrtr, with th various powr quality actors, normg to th standards.. ZETA CONERTER BASED AWPS CIRCUIT CONFIGURATION DBR Filtr Sz Zta Convrtr Cz Lz is D D3 L z Cb Sz Do Lo Io Ro s D4 D C + d Lz Dz Cb Sz N N N3 Do Lo Co Io z Gatg pulss to Sz Sz Currnt Controllr Io PWM Gnrator Control unit or Zta Convrtr oltag Controllr z r PWM Gnrator Cm Ioc Comparattor Cv Ir oltag Controllr o o Control unit or Full Bridg Convrtr r Figur-. Schmatic o Zta nvrtr basd AWPS. A Diod Bridg Rctiir (DBR) with a LC iltr is nnctd to th put sid o a non-isolatd Zta nvrtr. This ntas two ductors L z and L z, an trmdiat capacitor C, a high rquncy switch S z and a diod D z. Th voltag obtad at th nvrtr is trmatd at th isolatd nvrtr, ntag two capacitors o qual valu, two transistor switchs and a high rquncy transormr (HFT). Th voltag output rom th HFT is nnctd to LC iltrs bor it trmatd to lctrical load. Th AC mas put voltag is rctiid usg th diod bridg rctiir as dicatd th abov igur. Th DC voltag is nnctd to a LC iltr circuit to narrow down th rippls. Th PFC Zta nvrtr rcivs th iltrd DC voltag, which rgulats th obtad DC output voltag and maks th circuit to draw a susoidal currnt rom th AC mas at unity powr actor. Th thr dirnt opratg nditions - DCM nditions (put ductor opratg DCM, capacitor opratg DCM and th output ductor opratg DCM) ar analyzd to ix th bst opratg mod or th PFC nvrtr at th ront-nd. Whn th output ductor is opratg DCM, it is obsrvd that th THD obtad is lowst. Th DC output voltag so obtad rom th Zta nvrtr is nnctd to th isolatd nvrtr to achiv a DC voltag at th output. Two transistor switchs prsnt th isolatd nvrtr ar opratd at a high rquncy, so that an AC voltag is obtad, which is thn givn to th high rquncy transormr (HFT). A ull wav bridg niguration is nigurd or bst r utilization. LC Filtrs ar providd ach output wdg to ras th rippls prsnt th output voltag and output currnt. Th isolatd nvrtr is opratd CCM, to rduc th mponnt strsss. OPERATING PRINCIPLE To undrstand th whol opration o th powr supply, th dirnt Disntuous Conduction Mods (DCM)o oprations ar dlibratd, i.., th put ductor (L ) opratg DCM, th trmdiat capacitor (C ) opratg DCM and th output ductor (L ) opratg DCM. Ipv + pv Q n G i L L C + c Figur-. Zta nvrtr. Th Zta nvrtr is analysd or Disntuous Conduction Mod all th thr mponnts (put ductor L, trmdiat capacitor C and output ductor L). Th nvrtr has bttr prormanc whn th ductor L has disntuous currnt mpard to that whn th rst two mponnts hav disntuous currnt. Th circuit is analysd this scnario and is xplad blow. Th opration o th PFC nvrtr with output ductor workg DCM. Th wavorms o th various mponnts o th Zta nvrtr durg th Dz Zta Convrtr L + c C + out 4753

3 OL., NO. 6, AUGUST 7 ISSN Asian Rsarch Publishg Ntwork (ARPN). All rights rsrvd. output ductor opratg DCM ar dicatd or on switchg cycl. b. Slction o th valu o output ductor Th critical ductanc valu stimatd by, i Lz Gatg pulss Sz ON Sz OFF i Lz L z m ( D( t)) T I DT R D( t) T I d T P (53.) 5 S 3 3 (3) L z m. 5mH (.44 7) 3 Cz i Lz Sz on Output Inductor DCM Sz o Figur-3. Wavorms o various mponnts. (L z DCM). Cz i Lz pak whr and I ar th output voltag and currnt o th PFC Zta nvrtr, rspctivly. Th valu o th ductor is stimatd to b.5 mh and th valu is also proportional to th rms valu o supply voltag. Mimum valu o th output ductor or DCM opration =.7 mh Mimum valu o th output ductor or CCM opration = 5.75 mh DESIGN Th dsign o th circuit is basd on th switch on and switch o priod, i.., chang th ductor currnt this phas. Th charactristics o th transistor switchs and th diods ar nsidrd to b idal. Th transistor switchg rquncy is much highr than th AC powr l rquncy. Duty ratio o th PFC Zta nvrtr is givn by, D( t). () whr, D(t) is th duty ratio o th Zta nvrtr, is th output voltag o th Zta nvrtr and is th put voltag rom AC powr ls. a. Slction o th valu o put ductor Th critical ductanc valu is givn by L zm D( t) T T i i.4475 S 3 L z m 4. 6mH () (.44 7) 3 whr D(t) is th duty ratio, and I ar th put voltag and currnt drawn rspctivly, rom th AC mas supply and T is th total switchg tim on switchg cycl. Th valu o th ductor is stimatd to b.9 mh and is proportional to th rms valu o AC supply voltag. Mimum valu o ductor or DCM opration =. mh Mimum valu o ductor or CCM opration = 4.6 mh c. Slction o th valu o trmdiat capacitor Th valu o th capacitor or CCM opration is givn by, D( t) TR C c ( T ( t)) P TP t ( ) ( ( )) 5S 35 C.68F.3(3 7(.44)) (3 7(.44)) whr Δ is th prmissibl rippl th voltag across th trmdiat capacitor, P is th put powr and C is th voltag across th trmdiat capacitor. Th valu o th capacitor is stimatd to b.68 µf. Hnc, th practical valu o th Capacitor valu slctd =.66 µf. d. Slction o th output capacitor Th workg o th output capacitor is l with th opration o th put capacitor o th isolatd nvrtr. Th valu o th output capacitor is slctd a mannr so as to radicat th snd ordr harmonic voltag. I Ch For a 9 rippl, th valu stimatd = 4 µf. (5). Dsign o iltr Th iltr is important kpg th harmonic distortion at th AC put mas powr supply at a low (4) 4754

4 OL., NO. 6, AUGUST 7 ISSN Asian Rsarch Publishg Ntwork (ARPN). All rights rsrvd. valu. Th valu o th ductor and capacitor nstitutg th ilr sction, ar calculatd as, C I tan p max p (6) whr θ is assumd as or matag a high powr actor, p and I p ar th pak put voltag and put currnt. Th maximum valu o capacitor is stimatd as.4 µf. Ld 4 c C d Hr c is th cut-o rquncy. Th valu o th sam is slctd such that it is much mor than th AC powr supply l rquncy ( = 5Hz) and lss than th transistor switchg rquncy ( s = khz). Cut-o rquncy is nsidrd as khz. Th rrspondg valu o ductor is stimatd to b 3. mh. Th transistor switchs prsnt at th primary sid o th HFT ar opratd at 6 khz. CONTROL Thr ar two sl-rgulatg ntrollrs providd to ntrol th output voltags o th Zta nvrtr and th isolatd nvrtr. Th ront-nd (Zta) nvrtr is ntrolld usg th voltag ollowr approach and th back nd (isolatd) nvrtr uss th avrag currnt ntrol tchniqu. a. Control o th PFC nvrtr Th ntrol circuit o th ront-nd nvrtr producs pulss acrdanc with th output voltag rror. Th rror is th dirnc voltag btwn th dsird lvl o voltag and th masurd voltag. Th voltag rror at an stant n is givn by th xprssion, ( n) ( n) (7) r (8) Th voltag rror is supplid to th proportional-tgral (PI) ntrollr to produc a ntrolld output voltag ( ). ( n) ( n ) k ( n) ( n ) k ( n) (9) p whr k p and k i ar th proportional ga and tgral ga to b st or th PI ntrollr. Th output signal rom th PI ntrollr is thn mpard to a high-rquncy saw-tooth signal (S t) to produc th PWM pulss rquird to triggr th transistor switchs. Whn S t<, thn S = ON, ls S = OFF, S rprsnts th switchg signal output rom th PWM gnrator, to triggr or th transistor switch. I th output i voltag varis, th output voltag also changs to adjust th duty cycl. Thus, th on and o tim (width) o PWM pulss changs suitably to mata th output DC voltag at a nstant valu. b. Control o th isolatd nvrtr To ntrol th output voltags o th isolatd nvrtr, avrag currnt ntrol mthod is usd. For ntrol, th output voltag obtad o is masurd and mpard to a rrnc voltag r, to gnrat a voltag rror which is th put to th PI ntrollr. Th output o th PI ntrollr is mpard to a saw-tooth wav signal to produc th switchg pulss to mak both th transistor switchs on and o altrnatly ach hal cycl o on PWM priod with suict dad tim to avoid shoot-through. Th width o th pulss changs as pr th voltag rror output o th mparator. By modiyg th duty cycl o th PWM pulss, th ntrol o th isolatd nvrtr is abl to rspond to othr output voltag variations. Th stimatd valus o all th mponnts ar tabulatd Tabl-. Tabl-. Spciications or Zta nvrtr basd Awps. Componnt Calculatd valu Slctd valu Inductor, L z 4.6 mh 5 mh Inductor, L z.5 mh.7 mh Capacitor, C z.6 µf 66 nf Capacitor, C b, C b 63 µf 66 µf SIMULATION RESULTS o ltag ( ) o ltag ( ) o ltag ( ) Supply oltag Rctiid oltag Tim (sc) 5-5 Filtr Output oltag Figur-4. Input voltag -, rctiid voltag and th iltrd put voltag. Intrmdiat Output oltag Tim (sc) Figur-5. oltag at th primary sid o HFT. 4755

5 OL., NO. 6, AUGUST 7 ISSN Asian Rsarch Publishg Ntwork (ARPN). All rights rsrvd Output oltag Tim (sc) Mag (% o Fundamntal) 3 Fundamntal (5Hz) = 56.9, THD= 5.37% Frquncy (Hz) Figur-6. Load voltag Figur-9. Input currnt THD % Output Currnt Tim (Sc) Figur-7. Load currnt - 75 A. Input Powr Factor Tim (sc) OPERATION Th opratg prcipl o th nvrtrs has bn laboratly xplad this sction. Crta assumptions hav bn mad to xpla th workg o th wldg powr supply: a) all smductor dvics hav bn nsidrd idal; b) th capacitors C bo and C o wr o larg valu to mata nstant output voltags and o without any rippl or on switchg priod; c) as th switchg rquncy ( s) >> th l rquncy (), th supply voltag has bn nsidrd nstant or on switchg rquncy cycl. 3. CSC CONERTER BASED AWPS Figur-8. Input powr actor -.7. S S Do Lo Io N N S3 S4 N3 Do DBR Filtr is s D D4 D3 D L C d Sb Lb Db Cb b S S3 S S4 N Do3 N N3 Do4 Co Ro Gatg pulss to S S S3 S4 Control unit or Full Bridg Convrtr Control unit or CSC Convrtr ma PWM Gnrator oltag Controllr b b b * S S3 S S4 N Do5 N N3 Do6 Lo ma PWM Gnrator Cm Comparattor Ioc Cv Currnt Controllr oltag Controllr Isc * Io Io o * Figur-. Schmatic o CSC nvrtr basd AWPS. 4756

6 OL., NO. 6, AUGUST 7 ISSN Asian Rsarch Publishg Ntwork (ARPN). All rights rsrvd. MODES OF OPERATION OF CSC CONERTER s s s D D4 D D4 D D4 D3 D (a) Mod-I D3 D (b) Mod-II D3 D L L C L C C Sb (c) Mod-III Isolatd Full bridg nvrtr Figur-. Opratg mods o CSC nvrtr. Th CSC nvrtr oprats a similar mannr as that o a standard Cuk nvrtr, though th lattr uss two ductors as mpard to on th ormr. Th opratg mods hav bn shown Figur-. Th put to th CSC nvrtr is givn rom th supply through th Diod Bridg Rctiir. Whn th CSC nvrtr oprats DICM, thr trmdiat opratg mods ar dscribd or vry switchg cycl, which volvs th chargg/dischargg o th capacitors/ductor, du to th turn on and o o th switch and th diod. This is discussd dtail: Mod I: In this mod, th switch S c is on and th diod D c is rvrs biasd stat. Durg this priod, th ductor L c is chargd through both th supply and th capacitor C c. This is shown Figur-a. This causs th capacitor C c to discharg through th ductor Lb and th -lk capacitor Cb, which lads to ras voltag across th capacitor C c. Hnc, th capacitor valu should Inductor Lb Chargg Sb Capacitor Dischargg Lb Lb Inductor Lb Dischargg Sb Db Cb Capacitor Cb Chargg Capacitor Chargg Lb Inductor Lb Dischargg Db Cb Isolatd Full bridg nvrtr Capacitor Cb Chargg Capacitor Chargg Db Cb Isolatd Full bridg nvrtr Capacitor Cb Dischargg b larg as to mata a ntuous voltag durg this trval. Mod II: This mod bgs whn th switch is turnd o and th diod is orward biasd. Hr, th nrgy stord th ductor L c is transrrd to th capacitor C c and th -lk capacitor C. Ths capacitors start chargg and th voltags across thm starts crasg. Howvr, th ductor currnt rass. This stag is shown Figur-b. Mod III: Th DICM mod o opration o th nvrtr starts this mod, whn th ductor currnt i L bms zro. Th capacitor kps chargg through th supply. Th currnt to th nvrtr is givn by th lk capacitor, as th diod is rvrs biasd. This is shown Figur-c. This mplts on switchg cycl. Th ductor currnt rmas zro until th switch is turnd on to ntu th switchg squnc. MODES OF OPERATION OF FULL BRIDGE CONERTER Th isolatd ull bridg nvrtr is d by th ntrolld output o th CSC nvrtr. It is dsignd as a buck nvrtr, as it is rquird to stp down th -lk voltag to a rquird lvl. To rduc th switchg dvic ratg and to xtnd th rang o output powr ratg, thr FB nvrtrs ar nnctd paralll. Th FB nvrtrs oprat Contuous Conduction Mod. Th opratg mods ar xplad. Mod I: In this mod, th switchs S and S4 ar triggrd and th -lk capacitor voltag appars across th primary wdg o th high-rquncy transormr (HFT). Th diods nnctd to th irst hal o th sndary wdg ar orward biasd. Th ductors nnctd at th output (L o and L o) start storg nrgy, causg th ductor currnt to cras. Howvr, th output iltr capacitor C o dischargs through th load. Mod II: This mod is bgs whn all th switchs S, S, S3 and S4 ar turnd o and all th diods nnctd on th sndary wdg o th transormr act as rwhlg diods. Th nrgy th ductors is dischargd to th output capacitor C o and th load. This causs th currnt o th ductor to ras larly. Mod III: This mod is similar to Mod I, switch pair S and S3 is triggrd to shit th nrgy to th load. Aga, th diods Do, Do3 and Do5 rma rvrs biasd and th output capacitor Co dischargs through th load. Mod I: Mods II and I ar analogous as wll. Non o th switch pairs nduct and all th output rctiir diods rwhl th nrgy pild up th ductors. Th output capacitor C o is chargd by th nrgy rlasd by th ductors. This mod cass whn th switchs S and S4 ar triggrd aga and th opration rpats succssiv switchg cycls. 4757

7 OL., NO. 6, AUGUST 7 ISSN Asian Rsarch Publishg Ntwork (ARPN). All rights rsrvd. DESIGN OF CSC CONERTER BASED AWPS Th AWPS has bn simulatd or a powr ratg o.5kw. It has bn sn that th powr supply is highly ctiv or wldg purposs. Th switchg rquncy o both th ront nd and isolatd nvrtrs is much highr than th l rquncy. Hnc, th supply voltag is supposd to b a nstant durg on switchg cycl. A) Dsign o put iltr Th output obtad at th DBR is givn to th iltr circuit nsistg o an ductor and capacitor. This smoothns th put currnt harmonics o highr ordr. Th iltr mponnts hav bn dsignd to obta lowr harmonic ntnt th currnt. Th capacitanc valu is calculatd as, C I tan p max () p whr p and I p ar th pak ac put voltag and currnt, rspctivly, and is th undamntal rquncy. Θ is assumd as, so as to atta high powr actor. Th maximum valu o th capacitanc is approximatd to.4 µf. Th ductor is also dsignd to obta a lowr harmonic ntnt th put currnt, whos valu is stimatd as, () C L 4 c D M K a (4) whr 36 c M.57 (5) 3 m and K a is th nduction paramtr. For DICM opration, K a (6) ( M s t ) Th nduction paramtr or th CSC nvrtr to oprat Disntuous Conduction Mod is, K a.7 (7) t 9 ( M ) Th valu o duty ratio D cn or th CSC nvrtr is obtad by substitutg ths valus (4). D cn=.7 A. Dsign o put ductors (Lc): Th ductor th CSC nvrtr is dsignd to hav disntuous ductor currnt vry switchg cycl. Th nomal valu o L c is, whr c is th cut-o rquncy (hr, assumd as 3 khz). L cn d D I sc cn d H (8) B) Dsign o CSC nvrtr Th CSC nvrtr is tndd to supply a lk voltag o 36 at a switchg rquncy o 3 khz. Th ductor L has bn discussd to b opratg DICM, so th currnt is disntuous durg a switchg priod. Howvr, th capacitor voltag C c rmas ntuous, unlik th ductor. Th put supply voltag ( s) bg assumd as, th rctiid output o DBR ( r) is stimatd as, whr sc is th switchg rquncy o th CSC nvrtr. Th valu o th ductor L must b lss than th critical valu or propr opration o th ductor Disntuous Conduction Mod. B. Dsign o capacitor (Cc): This capacitor is dsignd such that th voltag across it is ntuous throughout a switchg priod. Th voltag rippl limit that is prmittd is assumd to b % o Cc. s () r 98 () Dbn Pi Dbn R sb b sb F (9) Th output voltag c o th CSC nvrtr is xprssd by, D c c (3) r Dc C. Dsign o DC-Lk capacitor (C): Th valu o this capacitor rlis on th voltag rippl Δ th -lk voltag. Assumg th output voltag rippl to b 5% o th -lk voltag, th capacitor valu is calculatd as, whr Dc is th duty ratio o th switch Sc. Th duty ratio is chosn at an optimal valu or Disntuous Opratg Mod, which is givn by, C b Po L F () 4758

8 OL., NO. 6, AUGUST 7 ISSN Asian Rsarch Publishg Ntwork (ARPN). All rights rsrvd. whr L is th l rquncy, and Δ is th output voltag rippl. Th capacitor valu is chosn as 94µF to rduc output voltag rippl. C) Dsign o ull bridg buck nvrtr Full bridg nvrtrs ar usd th snd stag o th AWPS. Sc th rquird voltag rquird at th output is much lss than that obtad at th CSC nvrtr, th ull bridg nvrtr is a buck nvrtr, nnctd a modular mannr. Hnc, th dvics usd ach o thm ar o lowr powr ratg. Th put to this ull bridg buck nvrtr is th output o th CSC nvrtr. This snd stag achivs isolation by opratg at a switchg rquncy o khz and it signiis th rgular wldg powr supply. For simpl xplanation, a sgl modul o th FB nvrtr is nsidrd hr or analysis. A. Dsign o turns ratio o HFT: Th nt chang th ductor currnt ovr on switchg cycl is zro, or an isolatd ull bridg buck nvrtr. Th ratio o put to output voltag is givn by, N t ON toff d o () o N Ts Ts whr T s=/ s dicatd th switchg priod o th FB nvrtr. For th ratd output voltag o, th duty ratio is calculatd by, D o o d N N. () Th FB buck nvrtr oprats CCM. Thus th turns ratio is calculatd to obta an output voltag o 6, by rorganizg th abov quation. N N D o d (3) B. Dsign o output ductors (Lo and Lo): Th nvrtr th snd stag o th powr supply is dsignd to oprat CCM. Thus th currnts through ths ductors must b ntuous on switchg cycl. To satisy this ndition, th ductor valus must b larg nough to mata ntuous currnt. Th allowd rippl th currnt Δi Lo, is % o I o. Hnc, th output ductor valus ar xprssd by, L o (.5 D ) 6 (.5.4) ( i ) 5 o s Lo H (4) C. Dsign o output capacitor (Co): This capacitor is dlibratd to allviat th rippls th output voltag, which can b calculatd by, ( D ) o o. (5) 3 s Lo Co Assumg th output voltag rippl to b %, th valu o capacitor is givn by, o ( D ) 6 (.4) Co 8 L ( ) s o o 5F (6) Th abov calculatd valus or th dsign o th powr supply, along with th mponnt rquirmnt is tabulatd Tabl-. Tabl-. Dsign spciications or th proposd wldg powr supply. Convrtr CSC Convrtr FB Buck Convrtr Calculatd Optd Componnt valu valu Inductor, L 45.89µH 9µH Capacitor, C.67µF.66µF DC-lk capacitor 736.8µF 94µF Turns ratio, N /N Output Inductors, L o and L o µh 5µH Output Capacitor, C o 5µF 7µF CONTROL OF THE WELDING POWER SUPPLY Th powr supply or wldg application is suitably dsignd with two sparat ntrollrs or ach nvrtr. Hr, a voltag ollowr approach is implmntd or th irst nvrtr, i.., th ront nd CSC nvrtr, so as to achiv nar unity powr actor at th utility sid. For th snd stag nvrtr howvr, a dual-loop ntrol schm is implmntd. A ncis dscription o both th ntrol stratgis is dscribd. a) Control o th CSC nvrtr Th CSC nvrtr is dsignd to oprat DICM; th voltag ollowr mthod is usd. Th DICM opration o th ductor th CSC nvrtr hrntly hlps achivg powr actor rrction by mployg a voltag dback ntrol loop. This rgulats th -lk voltag spit o output currnt and output voltag variations. Hr, th -lk voltag is takn as dback and is mpard to a rrnc voltag cr. Th rror voltag producd c at any stant is xprssd as, c ( n) ( n) ( n) (7) cr c Subsquntly, this rror to d to a proportional and tgral (PI) ntrollr to gt a ntrolld output voltag. 4759

9 OL., NO. 6, AUGUST 7 ISSN Asian Rsarch Publishg Ntwork (ARPN). All rights rsrvd. ( n) ( n ) k { ( n) ( n )} k ( n) (8) pv c whr k pv and k iv dicat th proportional and tgral gas o th PI ntrollr rspctivly. Thratr, th output o th PI voltag ntrollr is mpard to a high rquncy saw-tooth wavorm to driv th triggr pulss or th switch th CSC nvrtr. I th magnitud o th saw tooth wav is lss than th magnitud o th ntrolld output voltag at any stant, thn th switch S c will b turnd on; and i th magnitud o th saw tooth wav is gratr than th magnitud o th ntrolld output voltag, thn th switch S c will b turnd o. b) Control o th FB buck nvrtr This ull bridg Buck nvrtr is anticipatd to dlivr a nstant output voltag. As an adjunct unction, th nvrtr should also hav currnt limitg unction durg ovrload nditions, so as to guarant a high-quality wld ovr a wid rang o voltag variation. This is on o th most dispnsabl critrions, which must b rporatd th dsign o powr supply or wldg purposs. A dual loop ntrol schm is adoptd hr. In addition to trackg th output voltag, th output currnt is also trackd. Th voltag loop is usd to ntrol th output voltag, whras th currnt loop limits th output load currnt durg ovrload nditions. Th output voltag o is masurd and thn mpard to a rrnc voltag r to gnrat an rror signal,. This rror signal is thn d to th PI ntrollr, as don th ntrol o CSC nvrtr, to susta th output voltag at th rquird valu. Th output o th PI voltag ntrollr is givn by, C ( k) C ( k ) k ' pv c { ( k) ( k )} k iv ' iv c ( k) (9) whr k pv and k iv ar th proportional and tgral gas o th voltag ntrollr, rspctivly. In th snd loop, th output currnt I o is takn as dback signal and mpard to a currnt limit I lim. It mpriss o a PI ntrollr, which procsss th rror signal to n th output currnt with limits. C ( k) C ( k ) k i i ' pi { I ( k) I ( k )} k ' ii I ( k) (3) whr k pi and k ii rprsnt th proportional and tgral ga nstants o th currnt ntrollr, rspctivly. Thratr, th mparator mpars th outputs o both th currnt and voltag ntrollrs, and th signal with th lowr amplitud is d to th puls widthmodulatd gnrator. It producs th gatg pulss rquird to triggr th dvics and hnc th duty cycl o th switchs rrspond to th changs th output voltag and currnt. SIMULATION RESULTS o ltag ( ) o ltag ( ) o ltag ( ) oltag () Supply oltag Rctiid oltag Filtr Output oltag Tim (sc) Figur-. Supply voltag -, Rctiid voltag atr DBR, Filtrd output voltag Output oltag o CSC nvrtr Tim (sc) Figur-3. oltag o th CSC nvrtr Tim (Sc) Output oltag Figur-4. Load voltag Tim (Sc).5 Output Currnt Figur-5. Load currnt - 75 A Tim (Sc) M ag (% o F undam ntal) 3 Powr Factor Figur-6. Input powr actor -.9. Fundamntal (5Hz) = 55.98, THD= 4.8% 5 5 Frquncy (Hz) Figur-7. Input currnt THD = 4.%. 476

10 OL., NO. 6, AUGUST 7 ISSN Asian Rsarch Publishg Ntwork (ARPN). All rights rsrvd. 4. ALIDATION OF THE AWPS WITH SIMULATION RESULTS Tabl-3. Comparison o prormancs o th dsignd wldg powr supplis. Paramtr Zta basd AWPS CSC basd AWPS Input oltag Output oltag Output Currnt Input Powr Factor.75.9 Input Currnt THD 5.37% 4.% A. Stady stat prormanc Th wldg powr supply is ratd at supply voltag. Th rrspondg output voltag, output currnt is shown th Figurs 4, 5. Th transitional rsults - lik th CSC nvrtr voltag and th currnt is prsntd Figur-3. Th output voltag is rgulatd to 45, whil th voltag is rtad at 3. Th voltag ollowr approach matas a susoidal put currnt, which is phas with th put voltag. Th CSC ductor workg DICM and th ntuous voltag across th trmdiat capacitor is shown. B. Comparativ analysis A mparativ study was mad by simulatg both th dsignd nvrtrs and th rsults hav bn prsntd Tabl-3. Clarly, rom th tabulation, th Zta nvrtr has a low powr actor. Th powr actor can b improvisd by modiyg th niguration, but th CSC nvrtr provids satisactory opration without any kd o modiication. Th itial st and siz o th Zta nvrtr is quit high mpard to th CSC nvrtr AWPS. On th basis o th obsrvd rsults, it can b nirmd that th dsignd can b validatd or th wldg application and th CSC nvrtr basd AWPS achivs a bttr prormanc than th nvntional wldg powr supplis and th Zta nvrtr basd AWPS and can b usd as a asibl solution or AWPS. wldg can b rplacd with th CSC nvrtr basd powr supply. REFERENCES [] K. Wman. 3. Wldg Procss Handbook. Cambridg, MA, USA: Woodhad. pp [] B. Sgh, S. Sgh, A. Chandra, and K. Al-Haddad.. Comprhnsiv study o sgl phas AC-DC powr actor rrctd nvrtrs with high rquncy isolation. IEEE Trans. Ind. Inormat. 7(4): [3] J.-M. Wang and S.-T. Wu. 5. A novl vrtr or arc wldg machs. IEEE Trans. Ind. Elctron. 6(3): [4] 4. Limits or Harmonic Emissions. Intrnational Elctro Tchnical Commission Standard [5] Q. F. Tng, W. Z. Zhang, J. G. Zhu, and Y.G. Guo.. Modlg o arc wldg powr supply. Proc. Int. Con. Appl. Suprnd. Elctromagn. Dvics. pp [6] K. Mahmoodi, M. Jaari and Z. Malkjamshidi.. Opration o a Fuzzy ntrolld hal-bridg DCnvrtr as a wldg currnt-sourc. Indonsian J. Elct. Eng. (): 7-4. [7] D. Murthy-Bllur and M. K. Kazimirczuk.. Isolatd two-transistor Zta nvrtr with rducd transistor voltag strss. IEEE Trans. rcuits Syst. I, Rg. Paprs. 58(): CONCLUSIONS Two dirnt nigurations hav bn simulatd MATLAB/Simulk or th rquirmnt o a powr actor rrctd powr supply or wldg application. Th irst niguration is on with a Zta Convrtr th ront nd. It was ound to giv apprciabl prormanc mparison with th nvntional wldg powr suppl. Th distortion th put currnt has drastically rasd, along with a good put powr actor. Th prormanc was still improvd with anothr niguration, namly a Canonical Switchg Cll nvrtr. This uss on ductor unlik th ormr and has bn ound to b prormg bttr. Th rsults obtad rom th simulation prov th sam. Bttr powr quality is attad-with powr quality dics with spciid limits. Thus th nvntional powr supply or 476