Efficient loop-back testing of on-chip ADCs and DACs

Transcription

1 Efficint loop-back tsting of on-chip ADCs and DACs Hak-soo Yu, Jacob A. Abraham, Sungba Hwang, Computr Enginring Rsarch Cntr Th Univrsity of Txas at Austin Austin, TX 787, USA Jongjin Roh Elctrical and Computr Enginring Hanyang Univrsity Kora Abstract This papr prsnts an fficint approach to tsting on-chip Analog to Digital Convrtrs (ADCs) and Digital to Analog Convrtrs (DACs) in loop-back mod. On-chip digital signal procssing units can b usd to gnrat stimuli. With this mthodology, go/no-go tsts as wll as charactrization of th individual ADCs and DACs ar possibl. Th proposd approach is simpl and ovrcoms th low paramtric fault covrag of convntional loop-back tsts. Simulations on a Matlab modl of loopbackd convrtrs ar prsntd to validat th fasibility of th mthod. I. INTRODUCTION Th grat dmand for mixd-signal dvics from th tlcommunications, mbddd systms and multi-mdia markts has incrasd th importanc of rsarch into costffctiv tsts for mixd-signal dvics. Howvr, thr ar many limiting factors to tsting analog parts in an fficint fashion. Ths includ th larg numbr of tsts and long tst tims for som analog circuit spcifications, as wll as th high cost of analog tst quipmnt. Anothr svr problm is th lack of asy accssibility to analog moduls on a mixd-signal chip. Analog to Digital Convrtrs (ADCs) and Digital to Analog Convrtrs (DACs) ar common moduls on many mixdsignal chips, sinc thy provid th intrfac btwn th outsid (analog) world and th digital circuit on th chip. In addition, many of th mixd-signal built-in slf-tst (BIST) schms [, ] rquir th us of both ADCs and DACs. Thus, tsting ADCs and DACs bcoms a crucial part of th ovrall tst stratgy. Thr ar many ways of implmnting tsts for ADCs and DACs. On of thm is to tst ADCs and DACs dirctly (th convntional mthod for discrt parts). Th mthod applis input signals and input cods to ADCs and DACs, rspctivly, and th outputs of ths dvics ar masurd by voltmtrs and oscilloscops. Various computations ar prformd on th masurd data to obtain th static and dynamic charactristics of th convrtrs. Whil this mthod provids accurat rsults, it rquirs long tst tims, xpnsiv tst quipmnt and dirct accssibility to th moduls. In ordr to rduc ths high tst costs, a Hybrid Built-In Slf-Tst (HBIST) tchniqu was introducd []. This mthod russ th xisting on-chip hardwar and signatur compaction schms which ar usd in digital BIST (Fig. ). Th loopback tst schm usd in transmission lins has also bn proposd as a solution to th problm []. Th approach has bn shown to b ffctiv in dtcting catastrophic faults. Howvr, losss in paramtric fault covrag may b xpctd du to psudo-random inputs that ar diffrnt from th tst inputs for ADC and DAC spcifications. Fig. shows anothr approach to tsting ADCs and DACs []. In this approach a squntial tst mthod is mployd, in fact, this mthod is similar to th convntional mthod mntiond abov. Whil on can xpct bttr fault covrag for catastrophic and paramtric faults than HBIST, a long tst tim is still xpctd. In this papr, w propos a simpl and fficint tst mthod for on-chip ADCs and DACs that xploits loop-back tst, and uss th xisting digital procssing units to gnrat input stimuli. Th particular tst stratgy largly dpnds on th typ of circuitry undr tst. Du to th dmand for simplicity and tolranc to paramtr variations in analog componnts, ovrsampling ADCs and DACs has gaind popularity. Thrfor, w focus on ovrsampling on-chip ADCs and DACs as th targt of our nw approach. Th organization of this papr is as follows. W rviw loop-back tst mthods in Sction. Th basic concpts of our mthod ar xplaind in Sction. Sction discusss th modling of th loop-backd convrtrs with Matlab and th initial simulation with SIMULINK. Th quations xtractd from this initial simulation ar usd to charactriz th convrtrs. Comparison of th solutions from th charactrizd quations and xhaustiv simulation on Matlab modl with SIMULINK ar prsntd to validat th fasibility of our mthod in th following sction. drawn in th last sction. Finally, conclusions ar II. REVIEW OF ON-CHIP ADC AND DAC TEST In communication systms, loop-back mods ar gnrally providd for th tst of th transmittr and rcivr circuitry []. Th output of a transmittr is usually connctd dirctly to th input of a rcivr. This mthod has bn applid to tst and diagnostic solutions for microprocssor and Digital Signal Procssor (DSP) basd boards. Th inputs and outputs of ach lmnt in ths boards can b tstd without conncting any othr componnts through th loop-back tst []. Whil loopback tsts hav bn dvlopd for componnts on a chip using

2 Stimulus gnration Signal Gnrator DAC Smoothing Filtr digital switch Analog Output analog PCM Rgistr Digital Filtr PCM LFSR DAC ADC LFSR Nyquist clock Rgistr Othr circuitry Digital Procssing Unit digital High spd clock Digital Filtr (c) multiplxr digital Signatur compaction ADC Analog Input High spd clock Figur. Th various tst st-up for ADCs and DACs Nyquist clock Dmod th on-chip ADCs and DACs [5, 6], loop-back tsts for th onchip ADCs and DACs thmslvs hav rarly bn attmptd du to obstacls such as fault masking and low fault covrag. Fault masking occurs bcaus som faults in th DAC can b maskd by othr faults in th ADC. Fig. (c) shows th ovrall block diagram of th loop-back path from th input of an ovrsampling DAC to th output of an ovrsampling ADC. Th bhavior of ach lmnt can mask or cancl out th faulty bhaviors of othr lmnts. To prvnt this, th circuits should b implmntd in such a way as to rduc th possibility of fault masking. Intrnal monitoring nods nd to b usd or suitabl tst vctors nd to b dvlopd in ordr to dtct fault masking. Input stimulus gnration can also b on of th difficultis in loop-back tsting. Two kinds of loop-back mods can b considrd for tsting ovrsampling convrtrs on a chip. On is analog loop-back, which loops th output of DAC back into th input of ADC. Th othr on is digital loop-back, which loops th output of ADC back into th input of DAC [5, 6]. Input stimuli can b gnratd ithr from xtrnal instrumnts or from DSP. Most mixd-signal dvics ar dvlopd basd on DSP, which can mulat high cost xtrnal signal gnrators using DACs. Thrfor, DSP-basd tsting of mixd-signal dvics is prfrrd [7]. In loop-back mod, th fact that ADCs and DACs ar tstd at th sam tim should b considrd in th gnration of th input stimulus. Mod III. LOOP BACK WITH MONITORING Th main focus of th proposd mthodology is to xtract ADC and DAC charactristics from th loop-backd output rsponss. Both th input stimulus and th loop-backd output rsponss ar digital. In analog loop-back mod, in which th output of th DAC is connctd to th input of th ADC, thr is no dirct way to monitor th loop-backd analog bhaviors. Furthrmor, th final digital outputs of th ADC do not provid much information on th individual loop-backd convrtrs. This rsults in fault masking and low fault covrag. In addition, this maks charactrizing th ADC and th DAC vry difficult. In fact, monitoring intrnal nods can provid mor information than monitoring th final digital outputs of th ADC. Thus w add th monitoring of intrnal nods to th convntional loop-backd schm. Th intrnal nods provid usful data which can b usd to split th loop-backd output rsponss of th individual units. Not that th outputs of th intrnal nod nd to b digital bit strams in ordr to prform DSP-basd tsting. Dtails of th slction of intrnal nods and th tst tchniqus rlatd to thos nods ar xplaind blow. A. Intrnal nod slction Th slction of intrnal nods dpnds on th typ of convrtr and th spcifics of its circuitry. In th cas of ovrsampling convrtrs, spctral sparation btwn th input signal and th nois introducd by quantization is possibl. As mntiond arlir, th final digital outputs of th ADC do not provid much information on th individual loop-backd convrtrs. Howvr, th spctral dnsity of th digital bit stram of th ADC bfor digital filtring shows th frquncy rspons which can b split into individual ADC/DAC charactristics. Whil th in-band charactristic shows both ADC and DAC charactristics, th out-of-band charactristic shows mainly th ADC charactristic du to filtring of th out-ofband nois by th low-pass filtr in th DAC, as can b sn in Fig.. PSD Y(f)LB Low pass filtr In band Out of band Frquncy Powr Spctral Dnsity nd k n Frquncy k: th ordr of bin n: sub bin of nth ordr Figur. Th frquncy rspons of a slctd intrnal nod and frquncy binning Whil convntional convrtrs ar gnrally tstd by comparing th valus of corrsponding inputs and outputs of a sampl, ovrsampling convrtrs ar tstd by calculating th RMS valus of modulation nois and its powr spctral dn- rd st

3 w t w w sity []. In th cas of a scond ordr convrtr, th powr spctral dnsity can b xprssd as follows. "!# $ %& ' (*)+-,/.5 6 )A! ;BC! +-,.:8D 6 87:9<; E % *F8 <GC! H I BF!JK$ I L ' M8NDO PQ N *! (*)+-,. 6 )F!8;BC! +-,5.:8 6 V WJX Hr, STF stands for th signal transfr function and NTF stands for th nois transfr function. YZ. is RAS5T U is th lvl spacing. For two-lvl quantization (+V, -V) is. []\ is th amplitud of a sin wav and^a\ is th fundamntal frquncy. Th incoming signal of a digital modulator and th outgoing signal of an analog modulator ar sampld at th sampling frquncy^ù _baac d. Equation is th powr spctral dnsity function of a constant input cod gnratd by DSP, and Equation is th powr spctral dnsity function of on-ton sin input cod gnratd by th DSP. Th powr spctral dnsity of th ADC, bfor digital filtring th outof-band frquncy, primarily shows th charactristics of th ADC. Th powr spctral dnsity within th in-band frquncy shows th charactristics of both th ADC and th DAC. In our proposd mthod, th ADC charactristics which obtaind in th out-of-band frquncy ar usd to xtract th charactristics of th DAC. Thus, mor rrors in th DAC charactristic than th ADC charactristic ar xpctd. B. Extraction of dynamic charactristics from frquncy binning In ordr to us th proposd tchniqu, collcting th frquncy rsponss of randomly gnratd fault-fr and faulty sampls is ncssary. Each frquncy rspons is classifid into a crtain group according to its dynamic charactristics such as signal-to-nois ratio (SNR). Ths classifid rsults ar usd to bnchmark convrtrs to b tstd. If w tak vry frquncy into account for its classification, a larg mmory is rquird to stor th boundaris of ach group. Sinc this is not practical, splitting th frquncy rsponss by som frquncy span is introducd to rduc th rquird siz of mmory. Th numbr of bins is dtrmind by th bin ordr (n) as shown in Fig.. %f, ;hgì j,:kl jm9i;*7 6on () Th frquncy rsponss in ach bin ar intgratd as Equation. Gpjm9I; nq () () -r-s touhv -r& s K I () whr ^x is th frquncy boundary of th y*z{ bin. Th manipulation of nar bins( H}D~m ) is prformd. Ths }D~m s ar classifid into an ADC or a DAC group according to thir frquncy. jm9i; n ƒ jm9i; n ƒ q- r = s q- r <j q> Gpjm9I; nq>! j q> Gpjm9I; nq> ˆ (5) q = r = s q = r <j q = Gpjm9I; nq =! j q = Gpjm9I; nq = ˆ (6) In ordr to obtain JŠŒ ` ˆŽ valus corrsponding to th ADC group, simulation of a stand-alon ADC is ncssary. By prforming th mntiond procdurs with sampls, th JŠ ˆŽ of th ADC group can b xprssd as a function of C}D~mB ˆŽ and classifid into on of th groups ( " ˆŽ ) which ar boundd by thir pr-dtrmind SNR rang JŠ. Th numbr of Q}D~m ˆŽ in th group~ is dfind as for ADC. Œ / jm9i; n œ5 m /žž5ž Ÿjm9I; n < (7) Th rang of }D~mB ˆŽ ( h ) in a group is dtrmind by th minimum and th maximum Q}D~m valus of th group. & M G I >š$g$&8 <9 PQ >H < (8) Th ŠŒ ˆŽŸ and C}D~mB ˆŽ valus of a group ar avragd and usd to build ŠŒ ˆŽŸ quations as a function of }o~ B ˆŽŸ. Th quations rlatd to ths calculations ar as follows. «ª r I Ÿjm9I; n& <ì & (9) ` 8 <9% & ª r ` 8 I Ÿjm9I; n <ì & () & < Ÿjm9I; jm9i; h!²± () ± Œ ` &8 <9 P () Thn, JŠ Ž ˆ can b xprssd as a function of JŠŒ ˆŽ, JŠŒ `³F, and }o~ ŽŸ ˆ. JŠŒ `³F is obtaind by simulation of loop-backd convrtrs. Using ths valus, µ]}o~ ŽŸ ˆ is dfind as follows. jm9i; nb Ÿjm9I; n & L ¹ & () whr º is a wight constant which is obtaind by huristic xprimnts. Th rmaining quations for JŠŒ `Ž ˆ ar th sam xcpt that }D~mB ˆŽ is rplacd by µ]}d~mbž ˆ >š$g B <9% Œ D jm9<; nb& œ5 m /žž5ž jm9<; nb& < () >š$g B <9% & M GC < >š$g :P < >š$g (5) ª r jm9i; nb <ì & ª r & 8B&8 I jm9i; (6) & (7)

4 Ä Y Y & B jm9i; B >š$g jm9i; B h!²± (8) ±Œ & P jm9i;b <9% (9) With ths quations, th go/no-go tst of loop-backd convrtrs is possibl. In addition, th SNRs of th DAC and ADC can b xtractd. IV. MODEL FOR LOOP-BACKED CONVERTERS Th sampls can b obtaind by simulation or ral masurmnts. Currntly th sampls ar gnratd by injcting paramtric faults into a Matlab modl of th loop-backd systm. In fact, th Matlab modl with SIMULINK [] can b simulatd xhaustivly. In ordr to obtain good bnchmark data, an accurat modl is a prrquisit. Considring that an ovrsampling modulator is typically implmntd using switchdcapacitors, th modl should includ th prformanc paramtrs of th building blocks and non-idalitis, such as sampling jittr,y*dkc» nois, and oprational amplifir paramtrs[9, 8]. Oprational amplifir paramtrs includ nois, finit gain, finit bandwidth, slw-rat, saturation voltag, tc. Th charactristics of nois in modulators dpnds largly on frquncy as illustratd in Fig.. Th modl can b built using quation-basd approachs [9, 8, ]. Th dtails on th modl will b dscribd blow. Powr Sprctral Dnsity flickr nois(pink) Quantization nois Truncation nois (Purpl) Sampling Jittr Thrmal nois Shot nois (Whit) R R inn inp n R Noislss Op Amp,5Ê ÌË ( Í ;& () Î &ÐÏ "!,/Ê IÑ Í Í () Fig. shows a typical op-amp circuit for nois analysis. Th RMS nois voltag including thrmal nois and flickr nois can b xprssd as Equation [].,5ÒmÓ & Ë Ô `± +-( 8 = M!, =Õ M = I /Ö n /Ø; DÙ! Ô `± ;& () whr ÚHŠŒÛ is th quivalnt nois bandwidth, [Ü_ÝÆ Y]Þ Z È/c Y is th nois gain, R ß is th whit voltag nois spcification, ^à ¾"á is th voltag nois cornr frquncy, and ^ â and ^ ³ ar th highst and th lowst frquncy. Intgrator non-idalitis such as DC gain, bandwidth, and slw rat can b modld by using Equation. Slw rat is dfind as ã ä ^TEå-æLç*è, whr ^ T åoæ is th maximum sin wav frquncy without distortion of th intgrator output and çè is a pak voltag. If th slw rat is gratr than th th chang of th intgrator output to a sampling priodd, th output of th intgrator is xprssd as Equation. é (! ëê NÌì œbp n ( 8,>í Ê"îï œbp,/ðî:ï h! é ( 8 () YDóˆô is th DC gain, õ is th intgrator lak- Z5 Å:ø is th tim constant of th intgrator, and ^ ù is whr ñq\ò_ ag,ö _ th unit gain frquncy. Th ffct of output distortion causd by slwing can b stimatd though circuit simulation, and b addd to Equation. A saturation ffct in th intgrator can b modld by insrting its modl insid th fdback loop of th intgrator. Frquncy X z MSB truncator Rconstruction filtr Lowpass filtr z Figur. Noiss in ¼ modulators and Op amp nois modl A. Nois and non-idality modls Th ffct of clock jittr on a switch-capacitor modulator by an amount ½ is xprssd in () whn a sinusoidal signal with amplitud A and is applid [9].! O &À 6?* / n O*ÁÂoà 6?* / n OŸÄ () Switching nois in a switchd-capacitor circuit is associatd with thrmal nois. Thr will typically b two switchd input capacitors and a switch rsistor ( ) in th switchd-capacitor circuit, such as a sampling capacitor (» U ) and a fdback capacitor (»EÅ ). Th nois causd by switching activitis, including thrmal nois, can b xprssd as Equation whr Æ%Ç:È is th Gaussian probability function, y is th Boltzmann constant, andd is th absolut tmpratur []. Th nois is suprimposd on th input signal É8Æ%Ç:È as xprssd in Equation [8]. Anti alias filtr sampling jittr, thrmal nois, and op amp nois modl intgrator th first Intgrator Truncation nois modl intgrator th scond Intgrator Comparator Figur. Th Matlab modl of loop-backd E¼ modulators B. Modl for loop-backd modulators Nois and non-idal bhavior can b modld in Matlab as shown in Fig. 5 [8]. In this sub-sction, it will b xplaind about th block diagram of th loop-backd convrtr, which is modld from th digital modulator ã to th analog ¾Lú modulator. Both modulators ar ordr. Th input signals from th linar intrpolatr ar summd with th fdback Y

5 signal from th truncatr of th digital modulator. Ths signals go through th nois shaping loop, ar filtrd by a rconstruction filtr which liminats th truncation nois of th modulator, and smoothd by a continuous-tim low pass filtr. Th nonlinaritis causd by slwing or signal-corrlatd sttling in a rconstruction filtr can b modld by using th valus from circuit simulation. This modl can b insrtd btwn th rconstruction filtr and th continuous-tim low pass filtr. Th filtrd signal is furthr filtrd by th othr low pass filtr, and th r-filtrd signal is th input signal to th analog modulator. This input signal and th comparator output, that is, from th -bit DAC, ar convolvd with th clock jittr and suprimposd with th switching nois. For a ã ¾Lú ordr analog modulator, only th first intgrator is modld with th non-idalitis sinc th distortion is mainly causd by th first intgrator. Th rrors introducd by th scond intgrator ar attnuatd by th nois shaping loop. Fig. shows th ovrall modl including th nois modls in modulators. convrtrs. Fault-fr and faulty sampls ar gnratd by injcting paramtric faults into th modl. Th xtraction of quation paramtrs starts with þ}d~m from powr spctral dnsity of frquncy rsponss as shown in Fig. 6. þ}d~m is calculatd from th powr spctral dnsity data as shown in Fig. 7. }o~ B ˆŽŸ is obtaind by Equation 6 basd on th calculatd þ}d~m. If nd ordr frquncy binning is applid to th Q}D~m calculation, Ð}D~m s ar rquird. Fig. 8 shows th SNR valu distribution according to }D~m ˆŽ. Th ŠŒ ˆŽŸ distribution charactristic to }o~ ˆŽŸ shows picwis linarity. In ordr to xprss ŠŒ ˆŽŸ as a function of }D~m ˆŽ, a pr-dtrmind SNR rang, JŠ, is st to 5 db. This JŠŒ dtrmins th Q}D~mB ˆŽ boundary of th groups ( " s). digital DSM Input_a thrmal nois modl Input_b Output(Thrmal nois includd) analog DSM Input Random Numbr Zro Ordr Hold K Output(opamp nois includd) loop backd DSM Frquncy [Hz] Input slw rat modl z Saturation Output(slw rat includd) Figur 6. PSD of a digital DSM, analog DSM and a loop-backd DSM alfa PSD of a nd Ordr Sigma Dlta Modulator DAC 5 IInput du/dt Figur 5. Th Matlab modl of noiss in ¼ modulators K Jittr V. SIMULATION RESULTS Output(jittr includd) ã ¾"ú Th loop-backd convrtrs with ordr modulators ar modld, which is xplaind in th prvious sction, and simulatd using Matlab with SIMULINK. Th modld convrtrs hav audio bandwidths (BW= y Hz) and thir ovrsampling ratio (OSR) is 56. Th sampling frquncy (^ U ) is,6 y ãpû Hz, which can b calculatd by Û ü û ý J. A y Hz singl-ton sin wav digitizd to 6-bit cods is usd ã ¾Lú as an input stimulus to th digital modulator. ordr frquncy binning is usd to xtract ADC/DAC dynamic charactristics from th powr spctral dnsity calculatd by prforming an FFT on th frquncy rsponss of loop-backd PSD [db] A B C D A B C D E F G H Figur 7. Gpjm9<; and Ÿjm9I; xtraction 5 6 Frquncy [Hz] E F G H ADC With this xtractd data, th paramtrs of th JŠ ˆŽ quation paramtrs in Equation ar obtaind. Through similar procdurs, th JŠ Ž ˆ valu distribution according

6 to µ]}d~m, which is xprssd in trms of JŠŒ ` ˆŽ, JŠŒ ³F, and Q}D~mBŽ ˆ, is obtaind as shown in Fig. 8. Th JŠŒ `Ž ˆ distribution charactristic to µ }D~mBŽ ˆ also shows picwis linarity. With th sam ŠŒ, JŠŒ `Ž ˆ can b xprssd as a function of µ]}d~m. Th JŠŒ `Ž ˆ quation paramtrs in Equation 8 ar obtaind through a similar procdur to that for th ADC. Fig. 9 and show comparisons btwn SNR from th xtractd quations and from th simulation. As xpctd, thr is som dviation btwn th two valus. If w st th maximum accptabl valu of dviation in Fig. 9 (c,d) to 5, which is a JŠŒ rang, 5 db, all ADC sampls ar within th rang. Howvr, % of DAC sampls ar out of rang. As shown in Fig. 9 (c,d), dviation of JŠ Ž ˆ is wors than JŠŒ ` ˆŽ. This rsults from fact that th calculation of ŠŒ ŽŸ ˆ dpnds on th ŠŒ ˆŽŸ which alrady has som rrors. In fact, th accuracy of th proposd mthod dpnds on th numbr of sampls, binning ordr, and JŠŒ. If th numbr of sampls is largr, binning ordr is highr, or JŠŒ is smallr, thn th tst is mor accurat. ADC SNR[dB] Dviation SD=.7dB Ybin x (c) Ybin x 5 DAC SNR[dB] Zbin x 5 SD=.dB (d) Zbin x 5 Figur 9.` (calculatd) vs.& (simulatd) and th SNR dviation in convrtr charactristic xtraction Dviation 8 ADC SNR[dB] SNR group rang 85 5dB Ybin x 5 DAC SNR[dB] SNR group rang 5dB Zbin x 5 Figur 8. ADC SNR as a function of Ÿjm9I;* and DAC SNR as a function of jm9i; VI. CONCLUSIONS W prsntd a simpl and fficint approach to tsting onchip ADCs and DACs. This approach xploits loop-back tsts and uss th xisting digital procssing units to gnrat input stimuli. Th proposd mthod xtracts DAC and DAC prformanc charactristics from th ovrall frquncy rsponss of th loop-backd convrtrs and provids go/no-go tsts and dynamic charactrization. Rsults of dtaild simulations show that th SNR valus calculatd from th xtractd quations hav rrors db (about bit in rsolution). W plan to xtnd this approach to tsting othr typs of convrtrs. ACKNOWLEDGEMENTS This rsarch ffort was supportd in part by Subcontract No. SA7JB from UC Brkly undr prim Contract 98- DT-66 from Microlctronic Advancd Rsarch Corporation (MARCO). REFERENCES [] M.J. Ohltz, Hybrid Built in Slf Tst(HBIST) for mixd analoqu/digital ICs, Proc. Europan Dsign and Tst Confrnc, pp. 7-6, 99. [] M. F. Tonr and G. W. Robrts, A BIST schm for an SNR tst of a sigma-dlta ADC, Proc. IEEE Intrnational Tst Confrnc, pp. 85-8, 99. [] M.S. Hutmakr and D.K. L, An architctur for slf-tst of a wirlss communication systm using sampld IQ modulation and boundary scan, IEEE communications Magazin, Vol. 7, Issus 6, pp. 98-, Jun 999. [] B. Frnton, Using Microprocssor and DSP dbug intrfacs for manufacturing functional tst and diagnosis, Etronix confrnc, Fb.. [5] TLCAD55, Dual Channl Codc W/Hybrid Op Amps, Spakr Drivr and Microphon Intrfac, Txas Instrumnts, [6] T858B, Quad Programmabl Codc, Agr Systms Inc., Kÿ [7] M. Mahony, DSP-Basd Tsting of Analog and Mixd-Signal Circuits, Nw York:IEEE Computr Socity Prss, 987. [8] S. Brigati, Ø. Modling sigma-dlta modulator non-idalitis in SIMULINK, Procdings of ISCAS 99, Vol., pp. 8-87, 999. [9] B. E. Bosr, B. A. Wooly, Th Dsign of Sigma-Dlta Modulation Analog-to-Digital Convrtrs, IEEE J. Solid Stat Circuits, Vol., pp. 98-8, 988. [] MATLAB and SIMULINK Usr s Guid, Th MathWorks, Inc., [] Nois Analysis in Oprational Amplifir Circuits Txas Instrumnts application rport, SLVAA, 999. [] S. R. Norsworthy, R. Schrir, and G.C. Tms, Dlta-Sigma Data convrtrs:thory, Dsign and Simulaiton, IEEE prss, Piscataway, NJ, 997. [] J. C. Candy and G. C. Tms, Ovrsampling ¼ data convrtrs:thory, dsign and simulaiton, IEEE prss, 99.