Serially Controlled, Triple 3x2 Audio/Video Crosspoint Switches

Transcription

1 9-496; Rev ; 6/99 Serially ontrolled, Triple 3x udio/video rosspoint Switches General Description The serial-interface, programmable, triple 3x audio/video crosspoint switches are ideal for multimedia applications. The devices include three crosspoint switch matrices, each containing three inputs and two outputs. To improve off-isolation, each switch matrix has a shunt input and each output is selectively programmable for clickless or regular-mode operation. selectable set of internal resistive voltage dividers supplies D bias for each output when using -coupled inputs. To improve crosstalk, the voltage dividers include four externally accessible bypass points. The feature 35Ω max on-resistance, 7Ω on-resistance matching between channels, 5Ω on-resistance flatness, and.7% total harmonic distortion (THD). dditionally, they feature off-isolation of -85dB at khz and -7dB at Hz, with crosstalk of -85dB at khz and -55dB at Hz. The X4548 uses a -wire I -compatible serial interface, while the X4549 uses a 3-wire SPI /QSPI /IRWIRE compatible serial interface. These parts are available in 36-pin SSP packages and are specified for the extended (-4 to +85 ) operating range. Set-Top Boxes P ultimedia Boards Video onferencing Systems High-End udio Systems Security Systems PRT X4548EX X4549EX pplications rdering Information TEP. RNGE -4 to to +85 PIN-PKGE 36 SSP 36 SSP Features Selectable Soft-Switching ode for lickless udio peration Ω Typical n-resistance (+5V Supply) 5Ω Typical n-resistance atching Between hannels Ω Typical n-resistance Flatness udio Performance -85dB ff-isolation at khz -85dB rosstalk at khz.7% THD with 6Ω Load Video Performance -7dB ff-isolation at Hz -55dB rosstalk at Hz Serial Interface -Wire I -ompatible (X4548) 3-Wire SPI/QSPI/IRWIRE-ompatible (X4549) Single-Supply peration from +.7V to +5.5V TP VIEW N BISH N S N3 V+ N NB S N Pin onfiguration X4548 X BISL ID GND 3 3 ID 9 B 8 ID 7 NB 6 ID3 SB 5 B N3 3 4 ID4 Functional Diagram appears at end of data sheet. N3B 4 3 BISH GND 5 BISL GND 6 V+ SPI and QSPI are trademarks of otorola, Inc. IRWIRE is a trademark of National Semiconductor orp. I is a trademark of Philips orp. SD (DIN) 7 (S) SL (SLK) 8 9 (DUT) ( ) RE FR X4549 SSP axim Integrated Products For free samples & the latest literature: or phone For small orders, phone

2 Serially ontrolled, Triple 3x udio/video rosspoint Switches BSLUTE XIU RTINGS V+ to GND...-.3V to +6V N, S_, ID_, BYP,, BISL, BISL, BISH, BISH, DUT to GND (Note )...-.3V to (V+ +.3V) S,,, SD, SL, DIN, SLK to GND...-.3V to +6V ontinuous urrent into ny Terminal...±m Peak urrent, N, S_, (pulsed at ms, % duty cycle max)...±4m ontinuous Power Dissipation (T = +7 ) 36-Pin SSP (derate.8mw/ above +7 )...94mW perating Temperature Range...-4 to+85 Storage Temperature Range to+5 Lead Temperature (soldering, sec)...+3 Note : Signals on N, S_, or exceeding V+ or GND are clamped by internal diodes. Limit forward diode current to maximum rating. Stresses beyond those listed under bsolute aximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELETRIL HRTERISTIS Single +5V Supply (V+ = +5V ±5%, T = T IN to T X, unless otherwise noted. Typical values are at T = +5.) (Note ) PRETER SYBL NDITINS IN TYP X UNITS NLG SWITHES V N, nalog Signal Range (Note 3) V, V+ V V S _ I = 4m, T = n-resistance R N V N or V S_ = 3V, V+ = 4.75V T = T IN to T X 45 to N or S_ n-resistance atch Between hannels (Note 4) to N or S_ n-resistance Flatness (Note 5) N or S_ ff-leakage urrent (Note 6) ff-leakage urrent (Note 6) I = 4m, T = R N V N or V S_ = 3V, V+ = 4.75V T = T IN to T X 8 I = 4m; T = +5 5 R FLT V+ = 4.75V; V N or V S_ = V, V, 3V T = T IN to T X 7 V N or V S_ = 4.5V, T = I N (FF) V; V = V, 4.5V; V+ = 5.5V T = T IN to T X - I (FF) V N or V S_ = 4.5V, V; V = V, 4.5V; V+ = 5.5V T = +5 T = T IN to T X Ω Ω Ω n n n-leakage urrent (Note 6) I (N) V N or V S_ = 4.5V, V, or floating; V = 4.5V, V; V+ = 5.5V T = +5 T = T IN to T X n UDI PERFRNE Total Harmonic Distortion plus Noise THD+N f IN = khz, V N or V S_ = V RS +.5V D R L = 6Ω R L =kω.7.6 % ff-isolation (Note 7) V IS() V N = V RS, f IN = khz, R L = 6Ω, S _ = GND, shunt switch on or off -85 db hannel-to-hannel rosstalk V T() V N = V RS, f IN = khz, R L = R S = 6Ω -85 db

3 Serially ontrolled, Triple 3x udio/video rosspoint Switches ELETRIL HRTERISTIS Single +5V Supply (continued) (V+ = +5V ±5%, T = T IN to T X, unless otherwise noted. Typical values are at T = +5.) (Note ) PRETER SYBL NDITINS IN TYP X UNITS VIDE PERFRNE V N or V S_ = V RS, Shunt switch on ff-isolation (Note 7) V IS(V) f IN = Hz, R L = 5Ω, -7 db R S =5Ω, S_ = GND Shunt switch off -6 V hannel-to-hannel rosstalk V N or V S_ =.5V RS, R S = 5Ω, T(V) -55 db f IN = Hz, R L = 5Ω, -3dB Bandwidth BW R S = 5Ω, R L = 5Ω 5 Hz ff-apacitance FF(N) f = Hz pf DYNI TIING WITH LIKLESS DE DISBLED (Note 8, Figure ) Turn-n Time t NSD V N or V S_ =.5V, T = +5 4 R L = 5kΩ, L = 35pF T = T IN to T X 5 ns V N or V S_ =.5V, T = +5 Turn-ff Time t FFSD R L = 3Ω, ns L = 35pF T = T IN to T X 5 Break-Before-ake Time t BB V N or V S_ =.5V 5 ns DYNI TIING WITH LIKLESS DE ENBLED (Note 8, Figure ) V Turn-n Time t N or V S_ =.5V, R L = 5kΩ, L = 35pF, NSE ms T = +5 V Turn-ff Time t N or V S_ =.5V, R L = 3Ω, L = 35pF, FFSE 3 ms T = +5 BIS NETWRKS Bias Network Resistance R BIS kω PWER SUPPLIES Supply Voltage Range V V Supply urrent (Note 9) I+ ll logic inputs = GND or V+ 6 µ ELETRIL HRTERISTIS Single +3V Supply (V+ = +3V ±%, T = T IN to T X, unless otherwise noted. Typical values are at T = +5.) (Note ) PRETER NLG SWITHES nalog Signal Range (Note 3) n-resistance to N or S_ n-resistance atch Between hannels (Note 4) to N or S_ n-resistance Flatness (Note 5) SYBL V N, V, V S _ R N R N R FLT I = 4m, V N or V S_ = V, V+ =.7V I = 4m, V N or V S_ = V, V+ =.7V I = 4m; V+ =.7V; V N = V,.5V, V NDITINS T = +5 T = T IN to T X T = +5 T = T IN to T X T = +5 T = T IN to T X IN TYP X V UNITS V Ω Ω Ω 3

4 Serially ontrolled, Triple 3x udio/video rosspoint Switches ELETRIL HRTERISTIS Single +3V Supply (continued) (V+ = +3V ±%, T = T IN to T X, unless otherwise noted. Typical values are at T = +5.) (Note ) PRETER N or S_ ff-leakage urrent (Notes 6, ) _ ff-leakage urrent (Notes 6, ) _ n-leakage urrent (Notes 6, ) UDI PERFRNE Total Harmonic Distortion plus Noise SYBL THD+N NDITINS f IN = khz, V N R L = 6Ω or V S_ =.5V D +.5V RS R L = Ω V N =.5V RS, f IN = khz, R L = 6Ω, S = GND, shunt switch on or off ff-isolation (Note 7) V IS() -85 db V hannel-to-hannel rosstalk V N =.5V RS, f IN = khz, T() -85 db R L = 6kΩ, R S = 6Ω VIDE PERFRNE I N (FF) V N or V S_ = 3V,.5V; V =.5V, 3V; V+ = 3.6V I (FF) V N or V S_ = 3V,.5V; V =.5V, 3V; V+ = 3.6V I (N) V N or V S_ =.5V, 3V, or floating; V =.5V, 3V; V+ = 3.6V ff-isolation (Note 7) V IS(V).5V RS, f IN = Hz, V N or V S _ = R L = 5Ω, R S = 5Ω hannel-to-hannel rosstalk V T(V) V N or V S_ =.5V RS, R S = 5Ω, f IN = Hz, R L = 5Ω T = +5 T = T IN to T X IN TYP X. UNITS % -55 db -3dB Bandwidth BW R S = 5Ω, R L = 5Ω Hz ff-apacitance FF(N) f = Hz pf Turn-n Time t NSD V N or V S_ =.5V, R L = 5kΩ, L = 35pF T = +5 T = T IN to T X T = +5 T = T IN to T X T = +5 T = T IN to T X Shunt switch on -7 Shunt switch off DYNI TIING WITH LIKLESS DE DISBLED (Notes 8 and, Figure ) n n n db ns Turn-ff Time t FFSD V N or V S_ =.5V, R L = 3Ω, L = 35pF T = +5 T = T IN to T X 35 Break-Before-ake Time t BB V N or V S_ =.5V ns DYNI TIING WITH LIKLESS DE ENBLED (Notes 8 and, Figure ) Turn-n Time t NSE V N or V S_ =.5V, R L = 5kΩ, L = 35pF ms Turn-ff Time t FFSE V N or V S_ =.5V, R L = 3Ω, L = 35pF 3 ms BIS NETWRK Bias Network Resistance R BIS kω 5 ns 4

5 Serially ontrolled, Triple 3x udio/video rosspoint Switches I/ INTERFE HRTERISTIS (V+ = +.7V to +5.5V, T = T IN to T X, unless otherwise noted. Typical values are at T = +5.) PRETER Input Low Voltage Input High Voltage Input Hysteresis Input Leakage urrent Input apacitance DUT utput High Voltage SYBL DIGITL INPUTS (SLK, DIN, S, SL, SD,, ) DIGITL UTPUTS (DUT, SD) utput Low Voltage V IL V IH V HYST I LEK IN V L V H V+ = 5V V+ = 3V f = Hz NDITINS Digital inputs = GND or V+ IN TYP X V+ = 3V.6 V+ = 5V I SINK = 6m I SURE =.5m V UNITS V V V µ pf V V -WIRE TIING HRTERISTIS (Figure 3) (V+ = +.7V to +5.5V, f SL = khz, T = T IN to T X, unless otherwise noted.) Data Hold Time PRETER SL lock Frequency Bus-Free Time between Stop and Start ondition Hold Time fter Start ondition Pulse Width of Suppressed Spike (Note 3) STP ondition Setup Time Data Setup Time lock Low Period lock High Period SL/SD Rise Time (Note ) SL/SD Fall Time (Note ) SYBL f SL t BUF t HD:ST t SU:ST t HD:DT t SU:DT t LW t HIGH t R t F V+ = 4.75V to 5.5V V+ =.7V to 5.5V NDITINS IN TYP X b 3 +. b 3 UNITS khz µs µs ns µs µs ns µs µs ns ns 5

6 Serially ontrolled, Triple 3x udio/video rosspoint Switches 3-WIRE TIING HRTERISTIS (Figure 5) (V+ = +.7V to +5.5V, T = T IN to T X, unless otherwise noted.) PRETER SYBL NDITINS IN TYP X UNITS V+ = 4.75V to 5.5V perating Frequency f P V+ =.7V to 5.5V. DIN to SLK Setup t DS ns DIN to SLK Hold t DH ns SLK Fall to utput Data Valid t D LD = 5pF ns S to SLK Rise Setup t SS ns S to SLK Rise Hold t SH ns S Pulse Width High t SW 4 ns SLK Pulse Width High t H ns SLK Pulse Width Low t L Rise Time (SLK, DIN, S) t R µs Fall Time (SLK, DIN, S) t F µs Note : The algebraic convention is used in this data sheet; the most negative value is shown in the minimum column. Note 3: Guaranteed by design. Not subject to production testing. Note 4: R N = R N(X) - R N(IN). Note 5: Resistance flatness is defined as the difference between the maximum and minimum on-resistance values, as measured over the specified analog signal range. Note 6: Leakage parameters are % tested at maximum rated temperature and guaranteed by correlation at T = +5. Note 7: ff-isolation = log (V _ / V N ), V _ = output, V N = input to off switch. Note 8: ll timing is measured from the clock s falling edge preceding the K signal for -wire and from the rising edge of S for 3-wire. Turn-off time is defined at the output of the switch for a.5v change, tested with a 3Ω load to ground. Turn-on time is defined at the output of the switch for a.5v change and measured with a 5kΩ load resistor to GND. ll timing is shown with respect to % V+ and 7% V+, unless otherwise noted. Note 9: Supply current can be as high as m per switch during switch transitions in the clickless mode, corresponding to a 48m total supply transient current requirement. Note : Leakage testing is guaranteed by testing with a +5.5V supply. Note : b = capacitance of one bus line in pf. Tested with b = 4pF. Note : Typical values are for X4548 devices. Hz ns (V+ = +5V, T = +5, unless otherwise noted.) RDS (N) (Ω) N-RESISTNE vs. V V+ =.7V V+ = 3.3V V+ = 5.V V (V) X4548 toc RDS (N) (Ω) N-RESISTNE vs. V ND TEPERTURE V (V) Typical perating haracteristics T = +85 T = +7 T = +5 T = -4 X4548 toc LEKGE URRRENT (p),. LEKGE URRENT vs. TEPERTURE _N N_FF TEPERTURE ( ) _FF X4548 toc3 6

7 Serially ontrolled, Triple 3x udio/video rosspoint Switches Typical perating haracteristics (continued) (V+ = +5V, T = +5, unless otherwise noted.) SUPPLY URRENT (µ) SUPPLY URRENT vs. TEPERTURE TEPERTURE ( ) X4548 toc4 Q (p) HRGE INJETIN vs. V V+ = 3.3V V V+ = 5V X4548 toc5 THD+N (%) TTL HRNI DISTRTIN PLUS NISE vs. FREQUENY 6Ω IN ND UT SIGNL = V RS..,, FREQUENY (Hz) X4548 toc6 LSS (db) VIDE FREQUENY HRTERISTIS LL-HSTILE RSSTLK FF-ISLTIN (WITH SHUNT) RSSTLK.5 FREQUENY (Hz) FF-ISLTIN (WITHUT SHUNT) X4548 toc7 LSS (db) UDI FREQUENY HRTERISTIS 6Ω IN ND UT k k k FREQUENY (Hz) FF-ISLTIN RSSTLK X4548 toc8 LSS (db) VIDE FREQUENY RESPNSE Ω IN ND UT. FREQUENY (Hz) X4548 toc9 LSS (db) UDI FREQUENY RESPNSE R IN = R UT = 5Ω -. k k k FREQUENY (Hz) X4548toc 7

8 Serially ontrolled, Triple 3x udio/video rosspoint Switches Typical perating haracteristics (continued) (V+ = +5V, T = +5, unless otherwise noted.) TIE (ns) N/FF TIE vs. TEPERTURE (HRD DE) TURN-N TIE, V+ = 3V TURN-N TIE, V+ = 5V TURN-FF TIE, V+ = 3V TURN-FF TIE, V+ = 5V TEPERTURE ( ) X4548 toc V (V/div) RISE TIE (SFT DE) µs/div X4548toc FLL TIE (SFT DE) TURN-N TIE (HRD DE) X4548toc3 V S (5V/div) X4548toc4 V (V/div) V (V/div) µs/div 5ns/div TURN-FF TIE (HRD DE) N/FF TIES (SFT DE) V S (5V/div) X4548toc5 V S (5V/div) TURN-FF TIE X4548 toc6 V (V/div) V (V/div) 5ns/div V (V/div) TURN-N TIE TIE (ms) 8

9 Serially ontrolled, Triple 3x udio/video rosspoint Switches PIN X4548 X , 6, NE N BISH N S N3 V+ N NB S Input to rosspoint Input to rosspoint Input 3 to rosspoint Positive Supply Voltage. Supply range is.7v to 5.5V. Input to rosspoint Input to rosspoint B FUNTIN Pin Description High Side of Bias Network for rosspoint. Use to give the outputs a D bias when inputs are -coupled (refer to the Using the Internal Bias Resistors section). Shunt Input to rosspoint. Use for shunt capacitor of ground connection to improve off-isolation, or as an additional input to switch matrix. Shunt Input to rosspoint. Use for shunt capacitor of ground connection to improve off-isolation, or as an additional input to switch matrix. N Input to rosspoint NB Input to rosspoint B SB Shunt Input to rosspoint B. Use for shunt capacitor of ground connection to improve off-isolation, or as an additional input to switch matrix B. 3 3 N3 Input 3 to rosspoint 4 4 N3B Input 3 to rosspoint B 5, 6, 3 5, 6, 3 GND Ground 7 SD -Wire Serial-Interface Data Input. Data is clocked in on SL s rising edge. 7 DIN 3-Wire Serial-Interface Data Input. Data is clocked in on SLK s rising edge. 8 SL -Wire Serial-Interface lock Input 8 SLK 3-Wire Serial-Interface lock Input 9 LSB+ of -Wire Serial-Interface ddress Field 9 DUT Data utput of 3-Wire Serial-Interface. Input data is clocked on SLK s falling edge delayed by 4 clock cycles. DUT remains active when S is high. LSB of -Wire Serial-Interface ddress Field S hip Select of 3-Wire Serial Interface. Logic low on S enables serial data to be clocked in to device. Programming commands are executed on S s rising edge. BISL Low Side of Bias Network for rosspoint and B. Use to give the and B outputs a D bias when inputs are -coupled (refer to the Using the Internal Bias Resistors section). 3 3 BISH High Side of Bias Network for rosspoint and B. Use to give the and B outputs a D bias when inputs are -coupled (refer to the Using the Internal Bias Resistors section). 4 4 ID4 udio Bypass for S and SB Inputs 5 5 B utput of rosspoint B 9

10 Serially ontrolled, Triple 3x udio/video rosspoint Switches PIN X4548 X NE ID3 ID B ID ID5 udio Bypass for IN3 and IN3B Inputs utput of rosspoint udio Bypass for IN and INB Inputs utput of rosspoint B udio Bypass for IN and INB Inputs utput of rosspoint utput of rosspoint Video Bypass for ll Inputs to rosspoint utput of rosspoint Pin Description (continued) FUNTIN BISL High Side of Bias Network for rosspoint. Use to give the outputs a D bias when inputs are -coupled (refer to the Using the Internal Bias Resistors section). X4548 X4549 3V SL 5% KNWLEDGE BIT t R > ns t F > ns V+ nf -WIRE V UT t N +.5V V N N V+ _ V UT V UT t FF V UT -.5V µp R 3 DEDER/ NTRLLER SERIL INTERFE R L 3Ω L 35pF S 3V 5% GND 3-WIRE V UT t N.9 V UT L INLUDES FIXTURE ND STRY PITNE. V UT = V [R L / (R L + R N )] V UT t FF. V UT Figure. Switching Times

11 Serially ontrolled, Triple 3x udio/video rosspoint Switches SIGNL GENERTR V+ nf R S /3 N_ GND Figure a. ff-isolation DEDER/ ENDER X4548 X4549 S_ V+/ R L NLYZER NLYZER R L V+/ µf R S V IN k k V UT k V IN R S k SIGNL GENERTR k SIGNL GENERTR k V UT X4548 X4549 Figure c. ll-hostile rosstalk Detailed Description The are serial-interface, programmable, triple 3x audio/video crosspoint switches. Each device contains two crosspoint switches with a common bypass network and another crosspoint switch with its own bypass network. The switches are independently controlled through the on-chip serial interface. The X4548 uses a -wire I -compatible serial communications protocol, while the X4549 uses a 3-wire SPI/QSPI/IRWIRE-compatible serial communications protocol. k Figure b. rosstalk X4548 X4549 k These Is include twelve selectable bias-resistor networks (one for each input) for use with -coupled input signals. They operate from a single supply of +.7V to +5.5V and are optimized for use in the audio frequency range to khz and at video frequencies to Hz. They feature 35Ω max on-resistance, 7Ω onresistance matching between channels, 5Ω on-resistance flatness, and as low as.7% total harmonic distortion.

12 Serially ontrolled, Triple 3x udio/video rosspoint Switches Table. ommand-byte Format BIT lickless ode Bias B B REGISTER udio off-isolation is -85dB at khz, crosstalk is -85dB at khz, and video off-isolation is -6dB at Hz. The S, SB, and S (shunt) inputs further improve off-isolation, allowing for the addition of external shunt capacitors to connect the outputs to grounds. When using the bias resistors, ID_ inputs improve crosstalk by providing an ground at the common bias points. Resistance from the bias points to the inputs allows signals to pass through the device and improve crosstalk performance (refer to the Functional Diagram). These devices feature a clickless operation mode for noiseless audio switching. Use the serial interface to select the clickless or standardswitching mode for each individual output. Table. Data-Byte Format (,,, 3, 4, 5 = ) BIT D7 D6 D5 D4 D3 D D D Don t care Don t care Don t care Don t care DESRIPTIN ontrols the switch connected to S_; = close switch, = open switch. ontrols the switch connected to N3_; = close switch, = open switch. ontrols the switch connected to N_; = close switch, = open switch. ontrols the switch connected to N_; = close switch, = open switch. PWER-UP DEFULT STTE pplications Information The are divided into five functional blocks: the control-logic block, three switch-matrix blocks, and the bias-resistor block (see Functional Diagram). The control-logic block accepts commands through the serial interface and uses those commands to control the four remaining blocks. SL SD SRT 7 7 D7 K K D K STP Figure 3. -Wire Serial-Interface Timing Diagram ( WriteByte ) SL SD SRT 7 7 D5 K K D8 K D7 D K STP Figure 4. -Wire Serial-Interface Timing Diagram ( WriteWord )

13 Serially ontrolled, Triple 3x udio/video rosspoint Switches ommand-byte and Data-Byte Programming The devices are programmed with a command byte and a data byte or data word ( bytes). Each bit of the command byte selects one of the functional blocks to be controlled by the subsequent data byte (word). The data byte (word) sets the state of the selected block(s). For the three switch-matrix blocks, the data byte sets the switch state. For the bias-resistor block, the data word SL SD controls which bias network is active (see Functional Diagram). logic in any bit position of the data byte makes that function active, while a logic makes it inactive. Tables 4 describe the command byte and the corresponding data byte. If more than one bit of the command byte is set, the data byte programs all of the corresponding blocks. This operation is useful, for instance, to simultaneously set all switch matrices to B D E F G H I J t LW t HIGH t SU:ST t HD:ST t SU:DT t HD:DT tsu:st t BUF = STRT NDITIN B = SB F DDRESS BYTE = LSB F DDRESS BYTE D = KNWLEDGE LKED INT STER E = SB F ND BYTE F = LSB F ND BYTE G = KNWLEDGE LKED INT STER H = SB F DT BYTE/WRD I = LSB F DT BYTE/WRD J = KNWLEDGE LKED INT STER Figure 5. -Wire Serial-Interface Timing Details Table 3. Bias Data-Byte (6 = ) BIT DESRIPTIN D5 Don t care D4 Don t care D3 Don t care D Don t care D ontrols S bias resistors; = connect bias resistors, = disconnect bias resistors. D ontrols N3 bias resistors; = connect bias resistors, = disconnect bias resistors. D9 ontrols N bias resistors; = connect bias resistors, = disconnect bias resistors. D8 ontrols N bias resistors; = connect bias resistors, = disconnect bias resistors. D7 ontrols SB bias resistors; = connect bias resistors, = disconnect bias resistors. D6 ontrols S bias resistors; = connect bias resistors, = disconnect bias resistors. D5 ontrols N3B bias resistors; = connect bias resistors, = disconnect bias resistors. D4 ontrols N3 bias resistors; = connect bias resistors, = disconnect bias resistors. D3 ontrols NB bias resistors; = connect bias resistors, = disconnect bias resistors. D ontrols N bias resistors; = connect bias resistors, = disconnect bias resistors. D ontrols NB bias resistors; = connect bias resistors, = disconnect bias resistors. D ontrols N bias resistors; = connect bias resistors, = disconnect bias resistors. PWER-UP DEFULT STTE 3

14 Serially ontrolled, Triple 3x udio/video rosspoint Switches Table 4. lickless ode Format (7 = ) BIT DESRIPTIN PWER-UP DEFULT STTE D7 Don t care D6 Don t care D5 ontrols clickless mode; = enables clickless mode, = disables clickless mode. D4 ontrols clickless mode; = enables clickless mode, = disables clickless mode. D3 ontrols B clickless mode; = enables clickless mode, = disables clickless mode. D ontrols B clickless mode; = enables clickless mode, = disables clickless mode. D ontrols clickless mode; = enables clickless mode, = disables clickless mode. D ontrols clickless mode; = enables clickless mode, = disables clickless mode. Table 5. WriteByte Protocol S R T 7 6 DDRESS BYTE ND BYTE DT BYTE K L I K B I S B B D7 D6 D5 D4 K D3 D D D K S T P SRT = Start ondition K = cknowledge ondition STP = Stop ondition Table 6. WriteWord Protocol S R T DDRESS BYTE ND BYTE DT WRD D5 D4 D3 D D D D9 D8 D7 D6 D5 D4 D3 D D D K L I K B I S B B K K SRT = Start ondition K = cknowledge ondition STP = Stop ondition K S T P Table 7. SPI Protocol 7 L I K ND BYTE B I S B B DT WRD D5 D4 D3 D D D D9 D8 D7 D6 D5 D4 D3 D D D SRT = Start ondition K = cknowledge ondition STP = Stop ondition 4

15 Serially ontrolled, Triple 3x udio/video rosspoint Switches S SLK DIN 7 ND BYTE Figure 6. 3-Wire Serial-Interface ommunication S t SS t H t SH t L SLK D5 DT BYTE D 4 t SH t DS t DH DIN t DV t D t TR DUT Figure 7. 3-Wire Serial-Interface Timing Details the same configuration. ny block that is not selected in the command byte remains unchanged. -Wire Serial Interface The X4548 uses a -wire I -compatible serial interface. The registers and the lickless ode register use the WriteByte protocol, which consists of an address byte, followed by a command byte, followed by a data byte (Table 5). The Bias register uses the WriteWord protocol, which consists of an address byte, followed by a command byte, followed by a data word (Table 6). To address a given chip, the and bits in the address byte must duplicate the values present at the and pins of that chip. The rest of the address bits must match those shown in Tables 5 and 6. The command and data-byte details are described in the ommand-byte and Data-Byte Programming section. The -wire serial interface requires only two I/ lines of a standard microprocessor port. Figures 3, 4, and 5 detail the timing diagram for signals on the -wire bus, while Tables 5 and 6 detail the format of the signals. The X4548 is a receive-only device and must be controlled by the bus master device. bus master device communicates by transmitting the address byte of the slave device over the bus and then transmitting the desired information. Each transmission consists of a start condition, a command byte, a data byte or word, and finally a stop condition. The slave device acknowledges the recognition of its address by pulling the SD line low for one clock period after the address byte is transmitted. The slave device also issues a similar acknowledgment after the command byte and again after each data byte. Start and Stop onditions The bus master signals the beginning of a transmission with a start condition by transitioning SD from high to low while SL is high. When the master has finished communicating with the slave, it issues a stop condition by transitioning SD from low to high while SL is high. The bus is then free for another transmission. 5

16 Serially ontrolled, Triple 3x udio/video rosspoint Switches Slave ddress (ddress Byte) The X4548 uses an 8-bit slave address. To select a slave address, connect and to V+ or GND. The X4548 has four possible slave addresses, thus a maximum of four of these devices may share the same -bit address bus. The slave devices on the X4548 monitor the serial bus continuously, waiting for a start condition followed by an address byte. When a slave device recognizes its address, it acknowledges that it is ready for further communication by pulling the SD line low for one clock period. 3-Wire Serial Interface The X wire serial interface is SPI/QSPI/ IRWIRE-compatible. n active-low chip-select (S) input enables the device to receive data for the serial input (DIN). Data is clocked in on the rising edge of the serial-clock (SLK) signal. total of 4 bits is needed in each write cycle. Segmented write cycles are allowed (three 8-bit-wide transfers) if S remains low. The first bit clock into the X4549 is the command byte s SB, and the last bit clocked in is the data byte s LSB. When programming the registers and the lickless ode register, the last eight bits of the data word are don t care. While shifting data, the device remains in its original configuration. fter all 4 bits are clocked into the input shift register, a rising edge on S latches the data into the X4549 internal registers, initiating the device s change of state. Figures 6 and 7 and Table 7 show the details of the 3-wire protocol, as it applies to the X4549. DUT is the shift register s output. Data at DUT is simply the input data delayed by 4 clock cycles, with data appearing synchronous with SLK s falling edge. Transitions at DIN and SLK have no effect when S is high, and DUT holds the last bit in the shift register. Daisy-haining To program several X4549s, daisy-chain the devices by connecting DUT of the first device to DIN of the second, and so on. The S pins of all devices are connected together, and data is shifted through the X4549 in series. Twenty-four bits of data per device are required for proper programming of all devices. When S is brought high, all devices are updated simultaneously. ddressable Serial Interface To program several X4549s individually using a single processor, connect the DIN pins of each X4549 together and control S on each X4549 separately. To select a particular device, drive the corresponding S low, clock in the 4-bit command, then drive S high to execute the command. Typically only one X4549 is addressed at a time. Improving ff-isolation To improve off-isolation, connect the S_ input to ground either directly (D ground) or through capacitors ( ground). losing S_ then effectively grounds the unused outputs. Using the Internal Bias Resistors Use the internal bias-resistor networks to give the switch outputs a D bias when the switch terminals are -coupled. Programming the switches that connect the bias resistors to the inputs is accomplished via bit 6 of the command byte. onnect _BISH and _BISL inputs to D levels (for example, V+ and GND), and activate the switch connecting the appropriate outputs. This applies a voltage midway between _BISH and _BISL to the input (refer to Tables and 4, and the Functional Diagram). To improve crosstalk when using the bias resistors, connect the ID_ inputs to ground through capacitors. lickless Switching udible switching transients ( clicks ) are eliminated in this mode of operation. When an output is configured as clickless, the gate signal of the switches connected to the output are controlled with slow-moving voltages. s a result, the output slew rates are significantly reduced. Program clickless operation via bit 7 of the command byte (refer to Tables and 4, and the Functional Diagram). Each operating switch may draw m during a transition. When another command is given while a switch is changing state in the soft mode, the will complete the previous command in the hard mode. To avoid this situation, do not issue a second command until the transition of the switch is complete. Power-Up State The feature a preset power-up state. Refer to Tables, 3, and 4 to determine the power-up state of the devices. Bypass apacitors The have five bypass pins for the internal bias resistor networks (ID_). The equivalent impedance at these pins is kω. To improve crosstalk performance, bypass ID_ pins with µf. For lowest cost, standard aluminum electrolytic capacitors in parallel with.µf ceramic chip capacitors perform well in audio applications. For computer audio applications, a single µf capacitor is sufficient. For telecom voice applications, a.µf capacitor is adequate. For video applications, bypass ID_ with.µf in parallel with pf. This provides a low impedance across the entire video bandwidth. 6

17 Serially ontrolled, Triple 3x udio/video rosspoint Switches N N N3 S NB NB N3B SB SWITH TRIX SWITH TRIX B Functional Diagram X4548 X B B N N N S 4 SWITH TRIX 9 (DUT) (S) V+ 6, GND 5, 6, 3 NTRL LGI 8 7 SL (SLK) SD (DIN) BISH BISH 3 BIS RESISTR NETWRK 36 BISL BISL ID ID ID ID5 ID4 ( ) RE FR X4549 7

18 Serially ontrolled, Triple 3x udio/video rosspoint Switches Package Information SSP.EPS hip Information TRNSISTR UNT: 77 SUBSTRTE IS INTERNLLY NNETED T V+. 8

19 Serially ontrolled, Triple 3x udio/video rosspoint Switches NTES 9

20 Serially ontrolled, Triple 3x udio/video rosspoint Switches NTES axim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a axim product. No circuit patent licenses are implied. axim reserves the right to change the circuitry and specifications without notice at any time. axim Integrated Products, San Gabriel Drive, Sunnyvale, axim Integrated Products Printed US is a registered trademark of axim Integrated Products.