Resonant Clock Circuits for Energy Recovery Power Reductions
|
|
|
- Hubert Park
- 6 years ago
- Views:
Transcription
1 Resonant Clock Circuits for Energy Recovery Power Reductions Riadul Islam Ignatius Bezzam SCHOOL OF ENGINEERING
2 CLOCKING CHALLENGE Synchronous operation needs low clock skew across chip High Performance Processors limit skew to 7-8ps across 21-64mm 2 Global Clock Power 24% in AMD Pile Driver Design (10W)* Clock Distribution Network (CDN) a critical chip component *V. S. Sathe, et al, Resonant Clock Design for Power-Efficient High-Volume x86-64 Microprocessor, AMD & U of M Ann Arbor
3 A Commercially Viable VLSI Power Saving Milestone Publications 1) ISSCC 2012 / SESSION 3 / PROCESSORS / 3.7 Resonant Clock Design for a Power-Efficient High-Volume x86-64 Microprocessor Visvesh Sathe1, Srikanth Arekapudi2, Charles Ouyang2, Marios Papaefthymiou3,4, Alexander Ishii3, Samuel Naffziger1 1AMD, Fort Collins, CO 2AMD, Sunnyvale, CA 3Cyclos Semiconductor, Berkeley, CA 4University of Michigan, Ann Arbor, MI 2) IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 48, NO. 1, JANUARY 2013 Resonant-Clock Design for a Power-Efficient, High-Volume x86-64 Microprocessor Visvesh S. Sathe, Member, IEEE, Srikanth Arekapudi, Member, IEEE, Alexander Ishii, Member, IEEE, Charles Ouyang, Member, IEEE, Marios C. Papaefthymiou, Senior Member, IEEE, and Samuel Naffziger, Senior Member, IEEE
4
5 Project Goals Review Design of clock tree to drive 500pF of load cap Power = 1mW (fcv 2 1GHz,1pF,1V Power = 0.5Watt for 500pF total load (25% of x86) Compare power with and w/o LC resonance Power Savings Variation with changes in Frequency Temperature Voltage Can we break the fcv 2 barrier? How to improve savings and DVS performance
6 Clock Distribution Network (CDN) IBM Bench-Marks: ISPD2010 Clock Synthesis CDN Grid/Mesh to meet skew spec Total Clock Load (C Load ) adds up to Nano Farads IBM 90nm Cell Base Band Processor ~ 2nF C Load AMD 32nm Pile Driver x86 core ~ 1 nf C load per core INTEL 45nM Processor 64mm2 : ~ 8nF C Load Need Large Amount of Power
7 Savings & Barriers Clocking Power Components (Sinks of Power) CDN Power = 24 Watts for 4GHz /1V Local Buffer Power = 1mW for 1GHz /1V (x 1000) Reducing Power Reduce Each of the Terms a : Don t use (Clock gating) or Shut down (Power Gating) C : Smaller Transistor & Loads ( Technology Scaling) V 2 : Dynamic Voltage Scaling (low swing designs) f : Run only as fast as needed (Freqency Scaling ACPI) Combination of above : DVFS (Dynamic Voltage & Frequency Scaling) Can we break the f CV 2 barrier? YES with Resonance P = a C V dd 2 f Recycle instead of throwing away Adiabatic charge/discharge is lossless/heatless
8 CMOS Dynamic Power Consumption with Large Capacitive Loads Switching Model Total Energy From Source (E in ) CV 2 dd V DD Energy Equations Energy Stored in Capacitor (E C ) ½ CV dd 2 Pull-up S1 OUT Pull-Down ½ CV dd 2 S2 ½ CV dd 2 C Power Consumed at Frequency f P = a C V dd 2 f a Activity Factor (High for Clocks that switch every cycle) Reducing Power Reduce Each of the Terms
9 CDN with Energy Saving Resonance VDD Clock Driver L L PullUp S1 Resonance ON/OFF VOUT S3 C V LB C V LB C PullDown S2 C L C L V LB C L V LB C V LB =Vdd/2 Turn S3 off at non-resonance Frequencies
10 Efficiency = ( Pc-Pr)/Pc Design Sizing in 45nM Transistor W and Inductor L for 1GHz, 1pF Simulated Efficiencies (%) vs. Frequency (GHz) 50% 40% 30% 20% 10% 0% -10% -20% -30% Frequency (GHz) 10X_Room 10X_HOT 5x_hot 5x_room
11
12
13 Improvement #1 Problem#1: Less savings from uniform placements ROCKS Clock Synthesis with Improved Inductor size & Placements
14 ROCKS Clock Synthesis Simulation Results : 45nm IBM Freq: 1GHz With resonant 07_rocks_test.py results: Buffers 18 Wires 185 Est_Power mw Act_Power mw Ambient Skew _grid_test_hspice.py results: Buffers 21 Wires 369 Est_Power mw Act_Power mw Ambient Skew Power saving: 7.93 mw %Saving with LC resonance = 45%
15 Improvement # 2
16 A Wide Frequency Resonant Driver VDD VDD PullUp S1 VOUT Resonance ON/OFF S3 Refresh S1 VOUT PullDown S2 C L Store/Recover Close for T ON S2 i L L C v c Vdd/2 a) Conventional Driver with Resonant Option Vdd/2 (b) Wide Freq Range Resonant Driver
17 Power Savings Simulation Results with Parasitics 40% 30% 20% 45nM 0.5V 45nm 1V 10% 32nm 1V AMD CDN [3] 0% Frequency (GHz ) 4. Xuchu Hu and Matthew R. Guthaus, Distributed LC Resonant Clock Grid Synthesis, IEEE Transactions On Circuits And Systems. 2012, in press. 17
18 18 References 1. S. C. Chan, P. J. Restle, T. J. Bucelot, J.S. Liberty, S. Weitzel, J. M. Keaty, B. Flachs, R. Volant, P. Kapusta, and J. S. Zimmerman, A Resonant Global Clock Distribution for the Cell Broadband Engine Processor, IEEE Journal Of Solid- State Circuits, Vol. 44, No. 1 pp.64-72, January V. S. Sathe, S. Arekapudi, C. Ouyang, M. C. Papaefthymiou, A. Ishii and S. Naffzinger, Resonant Clock Design for Power-Efficient High-Volume x86-64 Microprocessor, IEEE Solid State Circuits Conference, 2012, vol. 55, pp Xuchu Hu and Matthew R. Guthaus, Distributed LC Resonant Clock Grid Synthesis, IEEE Transactions On Circuits And Systems. 2012, in press. 4. Advanced Configuration and Power Interface (ACPI) is an open industry specification co-developed by Hewlett-Packard, Intel, Microsoft, Phoenix, and Toshiba:
19 Questions? SCHOOL OF ENGINEERING
Resonant Clock Design for a Power-efficient, High-volume. x86-64 Microprocessor
Resonant Clock Design for a Power-efficient, High-volume x86-64 Microprocessor Visvesh Sathe 1, Srikanth Arekapudi 2, Alexander Ishii 3, Charles Ouyang 2, Marios Papaefthymiou 3,4, Samuel Naffziger 1 1
Wide operating frequency resonant clock and data circuits forswitching power reductions
DOI 10.1007/s10470-014-0447-1 Wide operating frequency resonant clock and data circuits forswitching power reductions Ignatius Bezzam Shoba Krishnan C. Mathiazhagan Tezaswi Raja Franco Maloberti Received:
An Enhanced Design Methodology for Resonant Clock. Trees
An Enhanced Design Methodology for Resonant Clock Trees Somayyeh Rahimian, Vasilis Pavlidis, Xifan Tang, and Giovanni De Micheli Abstract Clock distribution networks consume a considerable portion of the
Resonant-Clock Design for a Power-Efficient, High-Volume x86-64 Microprocessor
140 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 48, NO. 1, JANUARY 2013 Resonant-Clock Design for a Power-Efficient, High-Volume x86-64 Microprocessor Visvesh S. Sathe, Member, IEEE, Srikanth Arekapudi,
CURRENTLY, near/sub-threshold circuits have been
536 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 49, NO. 2, FEBRUARY 2014 Intermittent Resonant Clocking Enabling Power Reduction at Any Clock Frequency for Near/Sub-Threshold Logic Circuits Hiroshi Fuketa,
VOLTAGE scaling is one of the most effective methods for
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 45, NO. 4, APRIL 2010 793 187 MHz Subthreshold-Supply Charge-Recovery FIR Wei-Hsiang Ma, Student Member, IEEE, Jerry C. Kao, Student Member, IEEE, Visvesh S.
An Active Decoupling Capacitance Circuit for Inductive Noise Suppression in Power Supply Networks
An Active Decoupling Capacitance Circuit for Inductive Noise Suppression in Power Supply Networks Sanjay Pant, David Blaauw University of Michigan, Ann Arbor, MI Abstract The placement of on-die decoupling
Fully Integrated Switched-Capacitor DC-DC Conversion
Fully Integrated Switched-Capacitor DC-DC Conversion Elad Alon In collaboration with Hanh-Phuc Le, Seth Sanders Berkeley Wireless Research Center University of California, Berkeley Multi-Core Chips Are
Course Content. Course Content. Course Format. Low Power VLSI System Design Lecture 1: Introduction. Course focus
Course Content Low Power VLSI System Design Lecture 1: Introduction Prof. R. Iris Bahar E September 6, 2017 Course focus low power and thermal-aware design digital design, from devices to architecture
Energy-Recovery CMOS Design
Energy-Recovery CMOS Design Jay Moon, Bill Athas * Univ of Southern California * Apple Computer, Inc. jsmoon@usc.edu / athas@apple.com March 05, 2001 UCLA EE215B jsmoon@usc.edu / athas@apple.com 1 Outline
Deep Trench Capacitors for Switched Capacitor Voltage Converters
Deep Trench Capacitors for Switched Capacitor Voltage Converters Jae-sun Seo, Albert Young, Robert Montoye, Leland Chang IBM T. J. Watson Research Center 3 rd International Workshop for Power Supply on
Energy Efficient Design of Logic Circuits Using Adiabatic Process
Energy Efficient Design of Logic Circuits Using Adiabatic Process E. Chitra 1,N. Hemavathi 2, Vinod Ganesan 3 1 Dept. of ECE,SRM University, Chennai, India, chitra.e@ktr.srmuniv.ac.in 2 Dept. of ECE, SRM
Switched-Capacitor Converters: Big & Small. Michael Seeman Ph.D. 2009, UC Berkeley SCV-PELS April 21, 2010
Switched-Capacitor Converters: Big & Small Michael Seeman Ph.D. 2009, UC Berkeley SCV-PELS April 21, 2010 Outline Problem & motivation Applications for SC converters Switched-capacitor fundamentals Power
Towards An Efficient Low Frequency Energy Recovery Dynamic Logic
. Towards An Efficient Low Frequency Energy Recovery Dynamic Logic Submitted in partial fulfillment of the requirements for the Computer Science and Engineering Preliminary Examination by Sujay S. Phadke
Boost Logic : A High Speed Energy Recovery Circuit Family
Boost Logic : A High Speed Energy Recovery Circuit Family Visvesh S. Sathe, Marios C. Papaefthymiou Department of EECS, University of Michigan Ann Arbor, USA vssathe,marios @eecs.umich.edu Conrad H. Ziesler
Microcontroller Systems. ELET 3232 Topic 13: Load Analysis
Microcontroller Systems ELET 3232 Topic 13: Load Analysis 1 Objective To understand hardware constraints on embedded systems Define: Noise Margins Load Currents and Fanout Capacitive Loads Transmission
POWER minimization has become a primary concern in
38 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 1, JANUARY 2007 Energy-Efficient GHz-Class Charge-Recovery Logic Visvesh S. Sathe, Member, IEEE, Juang-Ying Chueh, Member, IEEE, and Marios C. Papaefthymiou,
REPORT DOCUMENTATION PAGE
REPORT DOCUMENTATION PAGE Form Approved OMB NO. 0704-0188 Public Reporting burden for this collection of information is estimated to average 1 hour per response, including the time for reviewing instructions,
Interconnect/Via CONCORDIA VLSI DESIGN LAB
Interconnect/Via 1 Delay of Devices and Interconnect 2 Reduction of the feature size Increase in the influence of the interconnect delay on system performance Skew The difference in the arrival times of
Power Spring /7/05 L11 Power 1
Power 6.884 Spring 2005 3/7/05 L11 Power 1 Lab 2 Results Pareto-Optimal Points 6.884 Spring 2005 3/7/05 L11 Power 2 Standard Projects Two basic design projects Processor variants (based on lab1&2 testrigs)
An Efficient D-Flip Flop using Current Mode Signaling Scheme
IJSTE - International Journal of Science Technology & Engineering Volume 3 Issue 02 August 2016 ISSN (online): 2349-784X An Efficient D-Flip Flop using Current Mode Signaling Scheme Sheona Varghese PG
Quadrature GPS Receiver Front-End in 0.13μm CMOS: The QLMV cell
1 Quadrature GPS Receiver Front-End in 0.13μm CMOS: The QLMV cell Yee-Huan Ng, Po-Chia Lai, and Jia Ruan Abstract This paper presents a GPS receiver front end design that is based on the single-stage quadrature
Hot Topics and Cool Ideas in Scaled CMOS Analog Design
Engineering Insights 2006 Hot Topics and Cool Ideas in Scaled CMOS Analog Design C. Patrick Yue ECE, UCSB October 27, 2006 Slide 1 Our Research Focus High-speed analog and RF circuits Device modeling,
Low-Power VLSI. Seong-Ook Jung VLSI SYSTEM LAB, YONSEI University School of Electrical & Electronic Engineering
Low-Power VLSI Seong-Ook Jung 2013. 5. 27. sjung@yonsei.ac.kr VLSI SYSTEM LAB, YONSEI University School of Electrical & Electronic Engineering Contents 1. Introduction 2. Power classification & Power performance
Optimization of Digitally Controlled Oscillator with Low Power
IOSR Journal of VLSI and Signal Processing (IOSR-JVSP) Volume 5, Issue 6, Ver. I (Nov -Dec. 2015), PP 52-57 e-issn: 2319 4200, p-issn No. : 2319 4197 www.iosrjournals.org Optimization of Digitally Controlled
CPE/EE 427, CPE 527 VLSI Design I: Homeworks 3 & 4
CPE/EE 427, CPE 527 VLSI Design I: Homeworks 3 & 4 1 2 3 4 5 6 7 8 9 10 Sum 30 10 25 10 30 40 10 15 15 15 200 1. (30 points) Misc, Short questions (a) (2 points) Postponing the introduction of signals
The Road to Integrated Power Conversion via the Switched Capacitor Approach. Prof. Seth Sanders EECS Department, UC Berkeley
The Road to Integrated Power Conversion via the Switched Capacitor Approach Prof. Seth Sanders EECS Department, UC Berkeley 1 Integrated Power Integration has benefits: Reduce passives -> save board real
EE434 ASIC & Digital Systems. Partha Pande School of EECS Washington State University
EE434 ASIC & Digital Systems Partha Pande School of EECS Washington State University pande@eecs.wsu.edu Lecture 11 Physical Design Issues Interconnect Scaling Effects Dense multilayer metal increases coupling
Low-Power Clock Distribution Using a Current-Pulsed Clocked Flip-Flop
Low-Power Clock Distribution Using a Current-Pulsed Clocked Flip-Flop M.Shivaranjani 1 B.H. Leena 2 1) M. Shivaranjani, M.Tech (VLSI), Malla Reddy Engineering College, Hyderabad, India 2 B.H. Leena, Associate
Interconnect-Power Dissipation in a Microprocessor
4/2/2004 Interconnect-Power Dissipation in a Microprocessor N. Magen, A. Kolodny, U. Weiser, N. Shamir Intel corporation Technion - Israel Institute of Technology 4/2/2004 2 Interconnect-Power Definition
Integrated Power Management with Switched-Capacitor DC-DC Converters
Integrated Power Management with Switched-Capacitor DC-DC Converters Hanh-Phuc Le, Michael Seeman, Vincent Ng., Mervin John Prof. Seth Sanders and Prof. Elad Alon UC Berkeley, California p.1 Integration
High and Low Speed Output Buffer Design with Reduced Switching Noise for USB Applications
High and Low Speed Output Buffer Design with Reduced Switching Noise for USB Applications HWANG-CHERNG CHOW, C. HUANG and HSING-CHUNG LIANG Department of Electronics Engineering, Chang Gung University
International Journal of Scientific & Engineering Research, Volume 4, Issue 5, May ISSN
International Journal of Scientific & Engineering Research, Volume 4, Issue 5, May-2013 2190 Biquad Infinite Impulse Response Filter Using High Efficiency Charge Recovery Logic K.Surya 1, K.Chinnusamy
EDA Challenges for Low Power Design. Anand Iyer, Cadence Design Systems
EDA Challenges for Low Power Design Anand Iyer, Cadence Design Systems Agenda Introduction ti LP techniques in detail Challenges to low power techniques Guidelines for choosing various techniques Why is
SCALING power supply has become popular in lowpower
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS, VOL. 59, NO. 1, JANUARY 2012 55 Design of a Subthreshold-Supply Bootstrapped CMOS Inverter Based on an Active Leakage-Current Reduction Technique
A Solution to Simplify 60A Multiphase Designs By John Lambert & Chris Bull, International Rectifier, USA
A Solution to Simplify 60A Multiphase Designs By John Lambert & Chris Bull, International Rectifier, USA As presented at PCIM 2001 Today s servers and high-end desktop computer CPUs require peak currents
RECYCLING CLOCK NETWORK ENERGY IN HIGH-PERFORMANCE DIGITAL DESIGNS USING ON-CHIP DC-DC CONVERTERS
RECYCLING CLOCK NETWORK ENERGY IN HIGH-PERFORMANCE DIGITAL DESIGNS USING ON-CHIP DC-DC CONVERTERS by Mehdi Alimadadi M.A.Sc., University of British Columbia, 2000 B.A.Sc., Iran University of Science and
An Efficient Design of CMOS based Differential LC and VCO for ISM and WI-FI Band of Applications
IJSTE - International Journal of Science Technology & Engineering Volume 2 Issue 10 April 2016 ISSN (online): 2349-784X An Efficient Design of CMOS based Differential LC and VCO for ISM and WI-FI Band
19. Design for Low Power
19. Design for Low Power Jacob Abraham Department of Electrical and Computer Engineering The University of Texas at Austin VLSI Design Fall 2017 November 8, 2017 ECE Department, University of Texas at
CHARGE-RECOVERY circuitry has the potential to reduce
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 20, NO. 6, JUNE 2012 977 Energy-Efficient Low-Latency 600 MHz FIR With High-Overdrive Charge-Recovery Logic Jerry C. Kao, Student
A 60GHz CMOS Power Amplifier Using Varactor Cross-Coupling Neutralization with Adaptive Bias
A 6GHz CMOS Power Amplifier Using Varactor Cross-Coupling Neutralization with Adaptive Bias Ryo Minami,Kota Matsushita, Hiroki Asada, Kenichi Okada,and Akira Tokyo Institute of Technology, Japan Outline
CHAPTER 5 DESIGN AND ANALYSIS OF COMPLEMENTARY PASS- TRANSISTOR WITH ASYNCHRONOUS ADIABATIC LOGIC CIRCUITS
70 CHAPTER 5 DESIGN AND ANALYSIS OF COMPLEMENTARY PASS- TRANSISTOR WITH ASYNCHRONOUS ADIABATIC LOGIC CIRCUITS A novel approach of full adder and multipliers circuits using Complementary Pass Transistor
Lecture 16. Complementary metal oxide semiconductor (CMOS) CMOS 1-1
Lecture 16 Complementary metal oxide semiconductor (CMOS) CMOS 1-1 Outline Complementary metal oxide semiconductor (CMOS) Inverting circuit Properties Operating points Propagation delay Power dissipation
Lecture 18 SOI Design Power Distribution. Midterm project reports due tomorrow. Please post links on your project web page
EE241 - Spring 2004 Advanced Digital Integrated Circuits Borivoje Nikolic Lecture 18 SOI Design Power Distribution Announcements Midterm project reports due tomorrow Please post links on your project web
A Switched Decoupling Capacitor Circuit for On-Chip Supply Resonance Damping
A Switched Decoupling Capacitor Circuit for On-Chip Supply Resonance Damping Jie Gu, Hanyong Eom and Chris H. Kim Department of Electrical and Computer Engineering University of Minnesota, Minneapolis
Low Power VLSI Circuit Synthesis: Introduction and Course Outline
Low Power VLSI Circuit Synthesis: Introduction and Course Outline Ajit Pal Professor Department of Computer Science and Engineering Indian Institute of Technology Kharagpur INDIA -721302 Agenda Why Low
Performance Evaluation of Digital CMOS Circuits Using Complementary Pass Transistor Network
ISSN (Online) : 2319-8753 ISSN (Print) : 2347-671 International Journal of Innovative Research in Science, Engineering and Technology Volume 3, Special Issue 3, March 214 214 International Conference on
EECS 141: SPRING 98 FINAL
University of California College of Engineering Department of Electrical Engineering and Computer Science J. M. Rabaey 511 Cory Hall TuTh3:3-5pm e141@eecs EECS 141: SPRING 98 FINAL For all problems, you
Lecture 23: PLLs. Office hour on Monday moved to 1-2pm and 3:30-4pm Final exam next Wednesday, in class
EE241 - Spring 2013 Advanced Digital Integrated Circuits Lecture 23: PLLs Announcements Office hour on Monday moved to 1-2pm and 3:30-4pm Final exam next Wednesday, in class Open book open notes Project
Low Power Design Part I Introduction and VHDL design. Ricardo Santos LSCAD/FACOM/UFMS
Low Power Design Part I Introduction and VHDL design Ricardo Santos ricardo@facom.ufms.br LSCAD/FACOM/UFMS Motivation for Low Power Design Low power design is important from three different reasons Device
DESIGN AND SIMULATION OF A HIGH PERFORMANCE CMOS VOLTAGE DOUBLERS USING CHARGE REUSE TECHNIQUE
Journal of Engineering Science and Technology Vol. 12, No. 12 (2017) 3344-3357 School of Engineering, Taylor s University DESIGN AND SIMULATION OF A HIGH PERFORMANCE CMOS VOLTAGE DOUBLERS USING CHARGE
Tiago Reimann Cliff Sze Ricardo Reis. Gate Sizing and Threshold Voltage Assignment for High Performance Microprocessor Designs
Tiago Reimann Cliff Sze Ricardo Reis Gate Sizing and Threshold Voltage Assignment for High Performance Microprocessor Designs A grain of rice has the price of more than a 100 thousand transistors Source:
CS250 VLSI Systems Design. Lecture 3: Physical Realities: Beneath the Digital Abstraction, Part 1: Timing
CS250 VLSI Systems Design Lecture 3: Physical Realities: Beneath the Digital Abstraction, Part 1: Timing Fall 2010 Krste Asanovic, John Wawrzynek with John Lazzaro and Yunsup Lee (TA) What do Computer
Implementation of Power Clock Generation Method for Pass-Transistor Adiabatic Logic 4:1 MUX
Implementation of Power Clock Generation Method for Pass-Transistor Adiabatic Logic 4:1 MUX Prafull Shripal Kumbhar Electronics & Telecommunication Department Dr. J. J. Magdum College of Engineering, Jaysingpur
Technology Timeline. Transistors ICs (General) SRAMs & DRAMs Microprocessors SPLDs CPLDs ASICs. FPGAs. The Design Warrior s Guide to.
FPGAs 1 CMPE 415 Technology Timeline 1945 1950 1955 1960 1965 1970 1975 1980 1985 1990 1995 2000 Transistors ICs (General) SRAMs & DRAMs Microprocessors SPLDs CPLDs ASICs FPGAs The Design Warrior s Guide
Physical Design of Digital Integrated Circuits (EN0291 S40) Sherief Reda Division of Engineering, Brown University Fall 2006
Physical Design of Digital Integrated Circuits (EN0291 S40) Sherief Reda Division of Engineering, Brown University Fall 2006 Lecture 01: the big picture Course objective Brief tour of IC physical design
Low-Power Digital CMOS Design: A Survey
Low-Power Digital CMOS Design: A Survey Krister Landernäs June 4, 2005 Department of Computer Science and Electronics, Mälardalen University Abstract The aim of this document is to provide the reader with
EE241 - Spring 2004 Advanced Digital Integrated Circuits. Announcements. Borivoje Nikolic. Lecture 15 Low-Power Design: Supply Voltage Scaling
EE241 - Spring 2004 Advanced Digital Integrated Circuits Borivoje Nikolic Lecture 15 Low-Power Design: Supply Voltage Scaling Announcements Homework #2 due today Midterm project reports due next Thursday
FEASIBILITY OF OPTICAL CLOCK DISTRIBUTION FOR FUTURE CMOS TECHNOLOGY NODES
6 Vol.11(1) March 1 FEASIBILITY OF OPTICAL CLOCK DISTRIBUTION FOR FUTURE CMOS TECHNOLOGY NODES P.J. Venter 1 and M. du Plessis 1 and Carl and Emily Fuchs Institute for Microelectronics, Dept. of Electrical,
Improved Two Phase Clocked Adiabatic Static CMOS Logic Circuit
Available online www.ejaet.com European Journal of Advances in Engineering and Technology, 2017, 4 (5): 319-325 Research Article ISSN: 2394-658X Improved Two Phase Clocked Adiabatic Static CMOS Logic Circuit
Design of the Power Delivery System for Next Generation Gigahertz Packages
Design of the Power Delivery System for Next Generation Gigahertz Packages Madhavan Swaminathan Professor School of Electrical and Computer Engg. Packaging Research Center madhavan.swaminathan@ece.gatech.edu
IMPLEMENTATION OF ADIABATIC DYNAMIC LOGIC IN BIT FULL ADDER
Technology and Innovation for Sustainable Development Conference (TISD2006) Faculty of Engineering, Khon Kaen University, Thailand 25-26 January 2006 IMPLEMENTATION OF ADIABATIC DYNAMIC LOGIC IN BIT FULL
A design of 16-bit adiabatic Microprocessor core
194 A design of 16-bit adiabatic Microprocessor core Youngjoon Shin, Hanseung Lee, Yong Moon, and Chanho Lee Abstract A 16-bit adiabatic low-power Microprocessor core is designed. The processor consists
Design of Wide Tuning Range and Low Power Dissipation of VCRO in 50nm CMOS Technology
Design of Wide Tuning Range and Low Power Dissipation of VCRO in 50nm CMOS Technology Gagandeep Singh 1, Mandeep Singh Angurana 2 PG Student, Dept. Of Microelectronics, BMS College of Engineering, Sri
ECEN689: Special Topics in High-Speed Links Circuits and Systems Spring 2012
ECEN689: Special Topics in High-Speed Links Circuits and Systems Spring 2012 Lecture 5: Termination, TX Driver, & Multiplexer Circuits Sam Palermo Analog & Mixed-Signal Center Texas A&M University Announcements
DYNAMIC VOLTAGE FREQUENCY SCALING (DVFS) FOR MICROPROCESSORS POWER AND ENERGY REDUCTION
DYNAMIC VOLTAGE FREQUENCY SCALING (DVFS) FOR MICROPROCESSORS POWER AND ENERGY REDUCTION Diary R. Suleiman Muhammed A. Ibrahim Ibrahim I. Hamarash e-mail: diariy@engineer.com e-mail: ibrahimm@itu.edu.tr
Low Power Parallel Prefix Adder Design Using Two Phase Adiabatic Logic
Journal of Electrical and Electronic Engineering 2015; 3(6): 181-186 Published online December 7, 2015 (http://www.sciencepublishinggroup.com/j/jeee) doi: 10.11648/j.jeee.20150306.11 ISSN: 2329-1613 (Print);
ADIABATIC LOGIC FOR LOW POWER DIGITAL DESIGN
ADIABATIC LOGIC FOR LOW POWER DIGITAL DESIGN Mr. Sunil Jadhav 1, Prof. Sachin Borse 2 1 Student (M.E. Digital Signal Processing), Late G. N. Sapkal College of Engineering, Nashik,jsunile@gmail.com 2 Professor
High efficiency DC-DC Buck converter architecture suitable for embedded applications using switched capacitor
International Journal of Engineering Science Invention ISSN (Online): 2319 6734, ISSN (Print): 2319 6726 Volume 2 Issue 4 ǁ April. 2013 ǁ PP.15-19 High efficiency DC-DC Buck converter architecture suitable
Low-Voltage, 1.8kHz PWM Output Temperature Sensors
19-266; Rev 1; 1/3 Low-Voltage, 1.8kHz PWM Output Temperature General Description The are high-accuracy, low-power temperature sensors with a single-wire output. The convert the ambient temperature into
LOW POWER VLSI TECHNIQUES FOR PORTABLE DEVICES Sandeep Singh 1, Neeraj Gupta 2, Rashmi Gupta 2
LOW POWER VLSI TECHNIQUES FOR PORTABLE DEVICES Sandeep Singh 1, Neeraj Gupta 2, Rashmi Gupta 2 1 M.Tech Student, Amity School of Engineering & Technology, India 2 Assistant Professor, Amity School of Engineering
EE 42/100 Lecture 23: CMOS Transistors and Logic Gates. Rev A 4/15/2012 (10:39 AM) Prof. Ali M. Niknejad
A. M. Niknejad University of California, Berkeley EE 100 / 42 Lecture 23 p. 1/16 EE 42/100 Lecture 23: CMOS Transistors and Logic Gates ELECTRONICS Rev A 4/15/2012 (10:39 AM) Prof. Ali M. Niknejad University
Energy Recycling from Multi-GHz Clocks using Fully Integrated Switching Converters
Energy Recycling from Multi-GHz Clocks using Fully Integrated Switching Converters M. Alimadadi, S. Sheikhaei, G. Lemieux, S. Mirabbasi, W. Dunford, P. Palmer University of British Columbia, Vancouver,
Lecture 13: Interconnects in CMOS Technology
Lecture 13: Interconnects in CMOS Technology Mark McDermott Electrical and Computer Engineering The University of Texas at Austin 10/18/18 VLSI-1 Class Notes Introduction Chips are mostly made of wires
A 5.99 GHZ INDUCTOR-LESS CURRENT CONTROLLED OSCILLATOR FOR HIGH SPEED COMMUNICATIONS
A 5.99 GHZ INDUCTOR-LESS CURRENT CONTROLLED OSCILLATOR FOR HIGH SPEED COMMUNICATIONS Chakaravarty D Rajagopal 1, Prof Dr.Othman Sidek 2 1,2 University Of Science Malaysia, 14300 NibongTebal, Penang. Malaysia
Clock-Powered CMOS: A Hybrid Adiabatic Logic Style for Energy-Efficient Computing
Clock-Powered CMOS: A Hybrid Adiabatic Logic Style for Energy-Efficient Computing Nestoras Tzartzanis and Bill Athas nestoras@isiedu, athas@isiedu http://wwwisiedu/acmos Information Sciences Institute
Power-Area trade-off for Different CMOS Design Technologies
Power-Area trade-off for Different CMOS Design Technologies Priyadarshini.V Department of ECE Sri Vishnu Engineering College for Women, Bhimavaram dpriya69@gmail.com Prof.G.R.L.V.N.Srinivasa Raju Head
Module 4 : Propagation Delays in MOS Lecture 19 : Analyzing Delay for various Logic Circuits
Module 4 : Propagation Delays in MOS Lecture 19 : Analyzing Delay for various Logic Circuits Objectives In this lecture you will learn the following Ratioed Logic Pass Transistor Logic Dynamic Logic Circuits
International Journal of Engineering Trends and Technology (IJETT) Volume 45 Number 5 - March 2017
Performance Evaluation in Adiabatic Logic Circuits for Low Power VLSI Design Tabassum Ara #1, Amrita Khera #2, # PG Student [VLSI], Dept. of ECE, Trinity stitute of Technology and Research, Bhopal, RGPV
Comparative Analysis of Conventional CMOS and Adiabatic Logic Gates
MIT International Journal of Electronics and Communication Engineering, Vol. 4, No. 1, January 014, pp. 39 43 39 Comparative Analysis of Conventional CMOS and Adiabatic Logic Gates Amit Saxena Department
An Optimal Design of Ring Oscillator and Differential LC using 45 nm CMOS Technology
IJIRST International Journal for Innovative Research in Science & Technology Volume 2 Issue 10 March 2016 ISSN (online): 2349-6010 An Optimal Design of Ring Oscillator and Differential LC using 45 nm CMOS
On Chip Active Decoupling Capacitors for Supply Noise Reduction for Power Gating and Dynamic Dual Vdd Circuits in Digital VLSI
ELEN 689 606 Techniques for Layout Synthesis and Simulation in EDA Project Report On Chip Active Decoupling Capacitors for Supply Noise Reduction for Power Gating and Dynamic Dual Vdd Circuits in Digital
Noise Aware Decoupling Capacitors for Multi-Voltage Power Distribution Systems
Noise Aware Decoupling Capacitors for Multi-Voltage Power Distribution Systems Mikhail Popovich and Eby G. Friedman Department of Electrical and Computer Engineering University of Rochester, Rochester,
TO ENABLE an energy-efficient operation of many-core
1654 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS, VOL. 65, NO. 11, NOVEMBER 2018 2/3 and 1/2 Reconfigurable Switched Capacitor DC DC Converter With 92.9% Efficiency at 62 mw/mm 2 Using
A 10Gb/s 10mm On-Chip Serial Link in 65nm CMOS Featuring a Half-Rate Time-Based Decision Feedback Equalizer
A 10Gb/s 10mm On-Chip Serial Link in 65nm CMOS Featuring a Half-Rate Time-Based Decision Feedback Equalizer Po-Wei Chiu, Somnath Kundu, Qianying Tang, and Chris H. Kim University of Minnesota, Minneapolis,
Lecture 07 Modeling and Optimization of VLSI Interconnects (ECG 415/615 Introduction to VLSI System Design)
Lecture 07 Modeling and Optimization of VLSI Interconnects (ECG 415/615 Introduction to VLSI System Design) Dr. Yingtao Jiang Department of Electrical and Computer Engineering University of Nevada Las
A Low Phase Noise LC VCO for 6GHz
A Low Phase Noise LC VCO for 6GHz Mostafa Yargholi 1, Abbas Nasri 2 Department of Electrical Engineering, University of Zanjan, Zanjan, Iran 1 yargholi@znu.ac.ir, 2 abbas.nasri@znu.ac.ir, Abstract: This
EE 434 ASIC and Digital Systems. Prof. Dae Hyun Kim School of Electrical Engineering and Computer Science Washington State University.
EE 434 ASIC and Digital Systems Prof. Dae Hyun Kim School of Electrical Engineering and Computer Science Washington State University Preliminaries VLSI Design System Specification Functional Design RTL
20 GHz Low Power QVCO and De-skew Techniques in 0.13µm Digital CMOS. Masum Hossain & Tony Chan Carusone University of Toronto
20 GHz Low Power QVCO and De-skew Techniques in 0.13µm Digital CMOS Masum Hossain & Tony Chan Carusone University of Toronto masum@eecg.utoronto.ca Motivation Data Rx3 Rx2 D-FF D-FF Rx1 D-FF Clock Clock
Short-Circuit Power Reduction by Using High-Threshold Transistors
J. Low Power Electron. Appl. 2012, 2, 69-78; doi:10.3390/jlpea2010069 OPEN ACCESS Journal of Low Power Electronics and Applications ISSN 2079-9268 www.mdpi.com/journal/jlpea/ Article Short-Circuit Power
Performance Analysis of Different Adiabatic Logic Families
Performance Analysis of Different Adiabatic Logic Families 1 Anitha.K, 2 Dr.Meena Srinivasan 1 PG Scholar, 2 Associate Professor Electronics and Communication Engineering Government College of Technology,
IN the face of shrinking feature size, one of the major
1 An Analysis of Injection Locked Clocking with Ring Oscillators Suchit Bhattarai and Rachel Nancollas Abstract In the recent years, injection locked clocking (ILC has been proposed as a solution to the
Low Power Techniques for SoC Design: basic concepts and techniques
Low Power Techniques for SoC Design: basic concepts and techniques Estagiário de Docência M.Sc. Vinícius dos Santos Livramento Prof. Dr. Luiz Cláudio Villar dos Santos Embedded Systems - INE 5439 Federal
EE E6930 Advanced Digital Integrated Circuits. Spring, 2002 Lecture 7. Clocked and self-resetting logic I
EE E6930 Advanced Digital Integrated Circuits Spring, 2002 Lecture 7. Clocked and self-resetting logic I References CBF, Chapter 8 DP, Section 4.3.3.1-4.3.3.4 Bernstein, High-speed CMOS design styles,
EECS 427 Lecture 22: Low and Multiple-Vdd Design
EECS 427 Lecture 22: Low and Multiple-Vdd Design Reading: 11.7.1 EECS 427 W07 Lecture 22 1 Last Time Low power ALUs Glitch power Clock gating Bus recoding The low power design space Dynamic vs static EECS
A High-Speed Variation-Tolerant Interconnect Technique for Sub-Threshold Circuits Using Capacitive Boosting
A High-Speed Variation-Tolerant Interconnect Technique for Sub-Threshold Circuits Using Capacitive Boosting Jonggab Kil Intel Corporation 1900 Prairie City Road Folsom, CA 95630 +1-916-356-9968 jonggab.kil@intel.com
Design and Analysis of Energy Efficient MOS Digital Library Cell Based on Charge Recovery Logic
ISSN (e): 2250 3005 Volume, 08 Issue, 9 Sepetember 2018 International Journal of Computational Engineering Research (IJCER) Design and Analysis of Energy Efficient MOS Digital Library Cell Based on Charge
Comparison of adiabatic and Conventional CMOS
Comparison of adiabatic and Conventional CMOS Gurpreet Kaur M.Tech Scholar(ECE), Narinder Sharma HOD (EEE) Amritsar college of Engineering and Technology, Amritsar Abstract:-The Power dissipation in conventional
EMI Reduction on an Automotive Microcontroller
EMI Reduction on an Automotive Microcontroller Design Automation Conference, July 26 th -31 st, 2009 Patrice JOUBERT DORIOL 1, Yamarita VILLAVICENCIO 2, Cristiano FORZAN 1, Mario ROTIGNI 1, Giovanni GRAZIOSI
A GSM Band Low-Power LNA 1. LNA Schematic
A GSM Band Low-Power LNA 1. LNA Schematic Fig1.1 Schematic of the Designed LNA 2. Design Summary Specification Required Simulation Results Peak S21 (Gain) > 10dB >11 db 3dB Bandwidth > 200MHz (