Effective On-chip Inductance Modeling for Multiple Signal Lines and Application on Repeater Insertion

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1 Effective On-chip Inductance Modeling for Multiple Signal Lines and Application on Repeater Insertion Yu Cao, Xuejue Huang, Norman Chang', Shen Lin', 0. Sam Nakagawa', Weize Xie', and Chenming Hu EECS Department, University of California, at Berkeley, Berkeley, CA 94720, USA 'Hewlett-Packard Laboratories, Palo Alto, CA 94303, USA Abstract A new approach to handle the inductance effect on multiple signal lines is presented. The worst case switching pattern is first identijied. Then a numerical approach is used to model the effective loop inductance (Leg) for multiple lines. Based on look-up table for Leg, an equivalent single line model can be generated to decouple a specific signal line from the others to per$orm static timing analysis. Compared to the use of fill RLC netlist for multiple lines, this approach greatly improves the computation eficiency and maintains accuracy for timing and signal integrity analysis. Applications to repeater insertion in the critical path chains are demonstrated. For a single line, the RLC model minimizes delay with fewer number of repeaters than RC model. However, for multiple lines, wejnd that same number of repeaters is inserted for optimal delay according to both the RC and RLC multiple line models. 1. Introduction As VLSI design enters Deep-Sub-Micron (DSM) era, scaled feature sizes, an increased number of metal layers, and larger chip dimensions have helped to achieve faster, more complex, and more powerful design 113. Chip operation frequency nowadays is pushed into Gigahertz region with much shorter signal rise time. To accommodate this technology trend, designers must be more careful in handling interconnect delay and cross-talk noise, especially in critical path timing analysis, to reach higher clock frequency. In design automation, interconnect is usually modeled as a resistance-capacitance netlist for timing and noise prediction [2-41, because line inductance is negligible under low clock frequency. When the clock frequency approaches one Gigahertz, the impedance contributed by line inductance (wl) will be comparable to the line resistance [5-61. The inclusion of inductance not only slows down the signal delay, but also causes voltage overshoot and reduces rise time, which can introduce large crosstalk noise on neighboring lines [7j. With increasing chip size and the number of data bits, many long global lines run in parallel in the same layer. Besides metal-to-ground capacitance (C,) and selfinductance (L.q), coupling capacitance (C,) and mutual inductance (L,) are also important for correct delay and noise estimation. In the RC line model, the orthogonal layer can approximately be treated as a ground plane for capacitance coupling simulation [7]. Since C, drops quickly with increasing spacing, the nearest neighboring lines (first neighbors) will see the most of the charge excited by the aggressor. Other farther neighboring lines (second and the higher order neighbors) contribute minimally to capacitance coupling. In this sense, capacitance coupling is a 'short range' effect, and we only need to include the first neighbors into delay and noise calculation. Fig. la shows the dominant 'charge sharing' path for capacitance coupling (C,+ C,). The 1' neighbors shield most of the capacitance coupling from higher order neighbors. 1'' neighbors Aggressor I \ / b. Three major paths for inductive current return: (1) +cc; (2) exx; (3) +C,ec&,. Figure 1. Short range capacitance coupling vs. long range inductance coupling /01$ IEEE 185

2 In contrast to the RC case, inductance coupling excites an induced current that needs to find a return path to form the current loop. Unfortunately, with the receiver s gate capacitance (C,.,,,,,,,) loaded at the end of wire, there is no DC path for the return current directly back to the ground. The orthogonal layer cannot be the ground plane anymore because L, is zero for two perpendicular lines. The retum current must go through C,, C,, or Crecrever of the co-planar signal lines until it goes back to AC ground or hits the power and ground lines, which can shield further coupling, as shown in Fig. 1 b. Because the loop impedances of each of these paths are comparable, there is no dominant route for inductive current return. Furthermore, all higher neighbors should be taken into consideration because the mutual inductance Lm decays slowly with increasing spacing [8-91. Therefore, inductance coupling is a long range issue and the full inductance matrix is necessary for a correct RLC model representation [lo]. Because of the long range coupling characteristics of inductance coupling, accurate estimation of delay and noise for RLC lines is usually a time consuming task. For example, if there are N signal lines, we must include NC,, (N+l)C,, and a (N+2)x(N+2) partial inductance (L,T and Lm) matrix into simulation for correct results. For this reason, a full partial inductance representation is physically accurate but computationally costly. Particularly in determining the operating frequency of a chip, current EDA tools usually check a specific single line chain on critical path and examine the worst-case delay for repeater insertion and timing optimization. Since the operating frequency affects the entire chip and must be checked globally, use of a full netlist would be very computationally intensive. For this purpose, it would be preferable to develop an algorithm to reduce the multiple line condition to a single line model. This equivalent single line model should be able to take the neighboring line effects into account for delay estimation while greatly improving efficiency. In the conventional RC line model, due to short-range capacitance coupling, this simplification is realized by introducing a switch factor to effectively model first order coupling capacitances. The specific line can then be decoupled from the others by using an effective capacitance Ce~(C,+2qC,), as shown in Fig. 2a. Depending on the switching pattern, q is between (0, 2) for a step input or {-1, 3) for a ramp input [ll]. However, for the RLC line model, all neighboring lines between the same powerlground lines should be included, thus increasing the decoupling complexity. In the following sections, we will first introduce the effective loop inductance (Le8) concept to simplify the multiple RLC line problem into a single RL,f&,ff model as shown in Fig. 2b, and then explain a practical approach to model 15, which can handle the extra delay and noise caused by inductance. Applications to repeater insertion and critical path delay optimization will also be discussed. 5 a. Decoupling in RC line model c, f L, L=//=LCdw. I, S, A! ~drnt,, we,,,,,, tn,j b. Decoupling in RLC line model Figure 2. Simplification of multiple lines into single line improves simulation efficiency. 2. Effective Loop Inductance Modeling 2.1. Effective Loop Inductance Lefl Partial inductances L, and L, can accurately model the RLC line behavior, but they involve too many elements for simulation. With the knowledge that the induced current forms a loop and that all the inductance effects can be reflected by the loop RLC elements response, a loop inductance (Ll0,,J can be used to simplify the problem [7]. Using the correct L/<,,,,, value to replace L,5, we can then isolate the target line out for further analysis. Therefore, an accurate 4, model is essential for efficient timing analysis. For the multiple line-only case, RaphaelTM RI3 can directly simulate the value of L,,,, [12, 131. However in realistic design with a receiver gate loading the line end, there is no DC path for short connection. Simple L,,,op estimation from RI3 can cause a large error [14]. Fig. 3 shows an example of two identical 3mm coupling RLC lines. We use 0.18pm A1 interconnect technology in this example and in all following simulations. One line is excited by a loops rising time ramp input while the other is quiet. To match the output waveform, the actual Llc,(,p value is more than 500% of the simple RI3 result. 1.2 Real LjoOp Value: SPICE L1~+0.25nWmm Width/Spacing=l pm 0.2 Thickness=l.5pm Time (ps) Figure 3. Simple loop inductance model (L,mp=L,,+L;2Lm) underestimates inductance. / 186

3 Complicating the picture above, there are actually a number of paths for current retum in the multiple parallel line condition, as Fig. 1 b shows. Each path has a comparable loop impedance and contributes a part of the total retum current. Thus, if we wrap all these paths into a single line model, the loop inductance should be an effective loop inductance (Le.) to equivalently count all the loops' contributions. L, thus depends on a number of variables: line width w, line length 1, line spacing s, the number of signal lines between power/ground N, driver strength wdrrver, receiver strength wrrcelver, and signal rise time before the driver t,,,. For such a large number of variables, we need to make some fairly realistic assumptions to simply the L, modeling work:. All the signal lines are parallel to each other and have the same dimensions, spacing and drivedreceiver sizes. This assumption is usually met for global lines.. Wire thickness is a technology dependent parameter and it is fixed for the corresponding metal layer. 8 The ratio of the power/ground line width of the signal line width is fixed. Their spacing is the same. 8 Signal delay is defined as the delay between the input point of source drivers and the end of the segment it drives (i.e. the input point of the sink receivers). The central signal line is selected as the worst delay and noise line on critical path due to symmetry.. A non-inverting drivedreceiver is used and the total width of NMOS and PMOS in the final stage inverter is used to represent the drivedreceiver strength. 9 Cen and 7 are maintained the same as RC decoupling case for two reasons: 1) Such a delay estimation is neither too optimistic nor too pessimistic. 2) It is fair for RC/RLC comparison and addresses the extra delay and noise purely due to the inclusion of Lefl 2.2. Worst Case Input Vector In addition to geometrical variables, the input vector for multiple signal lines also significantly affects delay and noise amplitude on central signal lines. If the simple RC model is applied, it is known that the opposite switching pattem of the 1'' neighbors to the victim line generates the worst delay and the largest noise. The reason is that when two lines switch in opposite directions, the effective coupling capacitance between them is largest [l 11. Since the higher order neighbor coupling is negligible is the RC case, only considering the 1" neighbors' switching pattem is enough. With the inclusion of the long-range inductance coupling, the complete switching pattem is necessary for worst case estimation. Based on symmetry, there are two candidates for the worst case input vector, as shown in Fig. 4. Induced Return Current Victim Switching Current + 4 t + 4 Pattern (1) a. Switching pattern 1: capacitance coupling favorable t + t + t Pattern(2) b. Switching pattern 2: inductance coupling favorable Figure 4. Worst case input vector candidates ( f : switch up; 4 : switch down) The first is when all the neighboring lines switch oppositely (Fig. 4a). It sometimes generates the largest noise to slow down the central victim delay, especially when the lines are RC dominant [7]. But considering that the induced current actually runs in the same direction as the main switching current on the victim line, it can actually helps victim operation (Fig. 4a). We may prefer that all the higher order neighbors, which are purely inductance coupling to the victim, switch in the same direction as the victim to suppress victim switching and that only 1" neighbors, in which capacitance coupling mostly dominates, switch oppositely. This is the second candidate, as shown in Fig. 4b. The first candidate is capacitancecoupling-prone and the second is inductance-couplingprone. The worst case pattern depends on the applied technology and RLC parameters. In a more thorough investigation, we sweep all seven variables (w, I, s, N, w,ir,,,, wrrcrivrr, frl,c) over a wide range for metal layer 6 (m6), metal layer 5 (m5) and metal layer 4 (m4) and reach such conclusions: For top level interconnects (m6, m5, m4), about 80% worst cases are generated by the second switching pattern, i.e. 1" neighbors opposite-switching and all the other higher order neighbors switching the same as victim, as shown in Fig. 5. This implies a large inductive effect on current 0.18pm technology global lines. We would choose the second input vector as our worst case switching pattern.. Receiver capacitance is negligible compared to line coupling capacitance. Thus, we can fix wrecriver at a reasonable value (about 40pm) and focus on the other six variables. 187

4 m4 m5 m6 Figure 5. Over a wide range of (w, s, /, N, w,,,~, w,-,,,, frj, switching pattern 2 dominates worst case delay and noise Numerical Approach for Le,-, Modeling The decoupling of multiple lines with Leg speeds up simulation despite the large number of variables and nonmonochromic output waveform. To guarantee the accuracy of delay analysis for further applications, we take a numerical approach to generate a look-up table for L, first to perform critical path timing analysis. The methodology and simulation flow are shown in Fig. 6. up-table for crosstalk noise is also generated at this step. Our work targets at top level global wires, i.e. m6, m5 and m4, since inductance effects are significant. Before application to critical path analysis with this Le8 table, some observations are worth highlighting: Long range inductance coupling: A:; Fig. 7 shows, for various sizing global lines, effective loop inductance Leff goes up almost linearly with the number of signal lines. As equal spacing is assumed, coupling line spacing is proportional to the number of lines between them. So the linearly increasing of inductance demonstrates that mutual inductance drops slowly for higher order neighboring lines. Thus, their effects cannot be ignored, especially for larger lines, as shown in Fig. 7b.. Inductance coupling saturation: For smaller global lines, such as the lpm line in Fig. 7a, extra number of neighbors can saturate mutual inductance. Because the induced current prefers to return through the lowest impedance path, the farthest lines usually directly couple to the powerlground boundary instead of the central victim. The saturation part actually indicates the inductance coupling region in design. If designers layout powerlground shielding lines along this region (i.e. every five or six in Fig. 7a case), crosstalkimmunity and chip area cost are optimized. ( match extra Single line RCef,fRLe,,Cerf netlist [Extra delay due to Lr8) l LCfLook-up Table Figure 6. Simulation flow for Leff and peak noise look-up table generation to match extra delay due to inductance effect. For each variable combination, line FUC parameters, including R, L,T, L,, C, and C,, are first extracted. Then by full latter circuit simulation, the delay difference between the RC and RLC cases is extracted. After that, the decoupled single line model is built and simulated with Ce8 and withlwithout L, C, equals to (Cg+2qCc) where the exact value of q depends on the technology. Lef is solved by iteration to match the extra delay purely from the inductance effect (in the single line model, i.e. Le8). A look- Number of Signal Lines N a. w=lpm, s=0.8pm, w~,,...,=loop~n, tde=50ps Number of Signal Lines N b. w=t.spm, s=1.6pm, whe,=loopm, &=Sops Figure 7. Effective loop inductance vs. number of signal lines N. 188

5 . More linear delay dependence on line length with inductance effect: Fig. 8 shows typical line delay vs. line length curves. With the RC model, line delay is approximately proportional to (length)2. Inclusion of inductance introduces additional flight time and signal propagation impedance for the output. So, the RLC line delay increases faster with increasing length. Additional neighboring lines worsen this problem. 400 i N=10 Multiple Signal Lines between power/ground Lines * Full RLC netlist Table Extrapolation /Interpolation for Lef value Worst Case Single Line RLt~C,tI Model for Cntical Path Line Length /(mm) Figure 8. Line delay vs. line length. (w=l.5*m, s=l.6*m, wd,,y.i=loo*m, tr,se=loops) 3. Repeater Insertion with Inductance Effect On global lines, repeaters are usually inserted between the source and sink to achieve optimal delay. Suitable repeater insertion can reduce the interconnect delay by as much as more than 50%. Thus, as modem design is moving to the Gigascale era with more than 30% extra delay introduced by inductance, it is crucial to clarify the repeater insertion map for RLC line. Although some analytical models have been reported to cope with this problem [15], it is still unclear for a realistic multiple line case. With Lefl table specifically targeting at delay in RLC multiple lines, we apply the following methodology, as shown in Fig. 9, to solve this problem. The number of repeaters and their position are optimized to realize minimum delay [16]. Starting from the full RLC circuit representation for multiple lines, we extrapolate/interpolate the L, table to find out the exact Lea value for our worst case single line on the critical path. After that, the complicated multiple line problem is simplified into a decoupled single line with the RL,,& model. In doing this, both computational efficiency and delay estimation accuracy are guaranteed. Then, repeaters will be inserted into the single line to divide it into several segments. Since effective loop inductance is non-linearly dependent on the line length, we need to interpolate with the table values for each segment. Total line delay can be estimated after the correct 15, value is acquired. Iteration with this dividinghnterpolation methodology, optimized number of repeaters and their positions can be obtained. source repeater sink Figure 9. Repeater insertion with L,, look-up table. Fig. 10 demonstrates this methodology with two examples. First, a single global line is investigated. Results are shown in Fig. loa. This is a lpm wide, 1 Imm long, top-level AI line where the power/ground is so far away from it that the signal line can be treated as being isolated. RC model gives a minimum delay of 0.431ns with two repeaters while the RL& model optimized delay is s with only one repeater. The smaller number of repeaters in RLC case can be explained by the linear dependence of the single RLC line delay on line length, as compared to the quadratic dependence in RC case [15]. Thus, RLC line delay drops faster than RC when the wire length is shortened by repeater insertion. Fig. 10b shows the repeater insertion result for multiple lines: five signals between power/ground lines, each with 2pm width and spacing. Similar to the first example, they are all 1 Imm long. Both the RC and RL& models optimize delay with one repeater. The RC result, ns, is smaller than that for RL,& s. This is quite different from the single line case, but it can be attributed to the delay dependence on line length. There are two major factors affecting total effective loop inductance. The larger the total loop inductance, the longer delay we usually will have. One factor is the number of coupling lines. As Fig. 7 proves, with increasing number of neighboring lines, effective loop inductance goes up proportionally to that. That is why in Fig. 8, the N=10 case generates a longer delay than N=7. The other factor is the coupling length between aggressors and the victim. The longer the coupling length, the more L, contributes to Le#. As Fig. 8 indicates, delay decreases dramatically with line length. With N=7, when wire length is smaller than 189

6 5mm, even though L, over unit length is large enough, the total Le8 is small. The delay performance then merges into the RC case. Similarly, in the N=5, llmm RLC line case, after one repeater inserted, the coupling length is reduced to about 5mm and Len is not large enough to differentiate its delay from pure RC one, as shown in Fig. 8. Therefore, we have same number for optimized repeater insertion, as demonstrated in Fig. 10b A Y Opt. # of rpt: RLC:l; i + RC.*-e--- RLC Number of Repeaters / a N=l, w=l.opm, I=11000pm, wd vc,=loopm, tnrr=80ps 0.40 Opt.#ofrpt: RC: 1; 0.35 RLC:l; E v ) Number of Repeaters b. N=5, w=2.0pm, s=2.0pm, I=11000pm, ww,.,=loopm, r,.=tops Figure 10. Optimal number of repeaters: single line case and multiple line case. 4. Summary and Conclusion In this work, we develop an efficient way to handle delay and noise estimation for multiple on-chip global wires. Effective loop inductance, instead of partial inductance, directly determines the electrical characteristics of the coupling interconnect and greatly reduces the number of elements for further modeling and estimation. Thus, accurate Lcfl modeling becomes the main target. To highlight the inductance effect for timing analysis, our model is focused on the extra delay introduced purely by inclusion of Le? By using the Le# look-up table, we studied the inductance effect on repeater insertion. For a single line, Lefl is the self inductance L,. Extra inductance for a single line causes a more linear dependence of a line delay on line length, which has a larger slope than the quadratic de- pendence in the RC case when line lenglh is small. As a result, fewer number of repeaters are needed for a single RLC line. For multiple lines, L, is smaller than L, and mostly affected by the mutual inductance, which depends on the number of coupling lines N and their coupling length 1. In the 0.18pm A1 technology we are studying, the same optimal number of repeaters is found for both RC and RLC models, unless Nor 1 is extremcly large (N>7 or segment length> 6 ). In the future, we will address an analytical approach for L, to further improve simulation efficiency. 5. References [ 13 Intemational Technology Roadmap for Semiconductors (ITRS), [2] H. B. Bakoglu, Circuits, Interconnections, and Packaging for VLSI, Addison-Wesley Pub. Co., [3] T. Sakurai, Approximation of Wiring Delay in MOSFET LSI, IEEE Jour. of Solid-State Circuits, vol. 18, pp , Aug [4] S. Nakagawa, D. Sylvester, J. G. McBride, and S. Y. Oh, On-Chip Cross Talk Noise Model for Deep-Submicrometer ULSl Interconnect, HP Journal, pp , Aug [5] A. Deutsch, et al., When are Transmission-Line Effects Important for On-Chip Interconnects?, IEEE Trans. on Microwave Theory Tech., vol. 45, pp , Oct [6] A. Deutsch, et al., The Importance of Inductance and Inductive Coupling for On-Chip Wiring, Proc. ofleee 6-rh Electrical Petformance of Electronic Packaging, pp , Oct [7] C. K. Cheng, J. Lillis, S. Lin, and N. Chang, Interconnect Analysis and Synthesis, John Wiley & Sons, Inc., [8] Frederick W. Grover, Inductance Calculations Working Formulas and Tables, Dover Publications, Inc., [9] S. Lin, N. Chang, and S. Nakagawa, Quick On-Chip Selfand Mutual-Inductance Screen, International Symposium of Quality Electronic Design (ISQED), Mar [10]B. Krauter and L. Pilleggi, Generation Sparse Partial Inductance Matrices with Guaranteed Stability, Proc. ofleee ICCAD, pp 45-52, NOV [11]A. Kahng, S. Muddu, and E. Sarto, On Switch Factor Based Analysis of Coupled RC Interconnects, Proc. of DAC, pp , Jun, [12]N. Chang, S. Lin, L. He, S. Nakagawa, and W. Xie, Clocktree RLC Extraction with Efficient Inductance Modeling, Prod. of DATE, [13]L. He, N. Chang, S. Lin, and O.S. Nakagawa, An Efficient Inductance Modeling for On-Chip Interconnects, P roc. of CICC, pp ,1999. [14]Y. Cao, X. Huang, D. Sylvester, N. Chang, and C. Hu, A New Analytical Model for On-Chip RLC Coupling Interconnect, to be published at IEDM, Dec [15]Y. 1. Ismail, and E. G. Friedman, Effects of Inductance on the Propagation Delay and Repeater Insertion in VLSI Circuits, Proc. ofdac, pp , Jun. 1!)99. [16]N. Chang, G. Zavagli, K. Rahmat, J. Ku, J. Wanek, and S.Y. Oh, Signal Net Optimization via Repeater Insertion and Transistor Sizing, HP Design Tech. Conf.,