OC-192 communications system block diagram

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1 OC-192 communications system block diagram 10 Gb/s Laser Mod Photo Diode 10 Gb/s TIA + Preamp 10 GHz 16 TX E O O E RX 16 Network Processor 622Mb/s 10 Gb/s 622Mb/s Network Processor 16 RX E O O E TX 16 OC-192 (10 Gb/s) transceiver 0.18 µm CMOS process EECS 270C / Spring 2014 Prof. M. Green / U.C. Irvine 1

2 Transceiver block diagram: 10 GHz 10 Gb/s EECS 270C / Spring 2014 Prof. M. Green / U.C. Irvine 2

3 Transmitter Block Diagram RESET FIFO Control OVF CLK16IP CLK16IN Write Pointer LVDS Parallel Input Bus DI0P DI0N DI15P DI15N INPUT REGISTER 16 X 10 FIFO Read Pointer 16:1 MUX Output Retime TSDP TSDN TSCKP TSCKN CML High- Speed Outputs LVPECL Ref. Clock SELFECB REF155EN REFCLKP REFCLKN 10/10.7 GHz CMU DIVIDE-BY-16 RB_LD CLK16OP CLK16ON LCKDET LVDS Output Clock IFSEL VCP VCN EECS 270C / Spring 2014 Prof. M. Green / U.C. Irvine 3

4 Low-Frequency Input signals Input clock Input data Input data aligned to input clock (usually jittery) Reference clock T Very low jitter (~10 ppm) reference clock; used in CMU to generate 10 GHz internal clock t sh Reference clock and input clock are not synchronized. Maximum allowable variation between Input clock & Reference clock is T t sh EECS 270C / Spring 2014 Prof. M. Green / U.C. Irvine 4

5 Illustration of Input Timing Regimes Reference clock High-frequency clock input clock :1 MUX input data Input clock timing domain Reference clock timing domain Connection could exhibit varying delay Variable phasing between input & reference clock domains can cause bit errors in MUX EECS 270C / Spring 2014 Prof. M. Green / U.C. Irvine 5

6 First-In/First-Out (FIFO) Circuit (1) 16:1 MUX We require an intermediate block to resolve timing variations between input & reference clock EECS 270C / Spring 2014 Prof. M. Green / U.C. Irvine 6

7 Read clock based on input clock Write clock based on reference clock First-In/First-Out Circuit (2) Read clock Write clock Din_0 k Dout_0 Ref clock Synchronized with input clock Read clock Write clock To serializer (signals synchronized with reference clock) Din_n k Dout_n Ref clock Since these signals have period k times longer than the input period, the circuit can tolerate k times larger variation between input & reference clocks. EECS 270C / Spring 2014 Prof. M. Green / U.C. Irvine 7

8 FIFO approach: Large amount of hardware (many latches) Significant power dissipation unless static CMOS is used Can handle arbitrarily large delay variations Appropriate phase chosen DLL approach: Less hardware Can handle modest delay variations Better choice for BJT or GaAs processes EECS 270C / Spring 2014 Prof. M. Green / U.C. Irvine 8

9 16:1 Multiplexer Tree Structure 5 Gb/s 10 Gb/s 1.25 Gb/s 2.5 Gb/s 1.25 GHz 2.5 GHz 5 GHz static CMOS CML EECS 270C / Spring 2014 Prof. M. Green / U.C. Irvine 9

10 2:1 MUX cell details D flip-flop with extra latch EECS 270C / Spring 2014 Prof. M. Green / U.C. Irvine 10

11 1 4 f 1 2 f 1 2 f f 10I SS 2I SS 5I SS I SS Total current: 18I SS Assume all blocks have: Tail current I SS Resistor R Diff pair transistor sizes W/L EECS 270C / Spring 2014 Prof. M. Green / U.C. Irvine 11

12 We can take advantage of gain/bandwidth tradeoff by appropriate scaling: W L W L W L W L Design parameters: I SS R W/L C L Idea: 1 2 f f f τ = 2RC g 1 2 I SS,2R, 1 2 W, 1 2 C g τ = RC g I SS,R,W,C g I SS,R,W,C g Lower bit rate allows lower power! EECS 270C / Spring 2014 Prof. M. Green / U.C. Irvine 12

13 1 4 f 1 2 f 1 2 f f MSCALE=1/8 MSCALE=1/2 MSCALE=1/2 MSCALE=1 1 8 I,8R, 1 SS 8 W τ = 4RC g 1 2 I,2R, 1 SS 2 W τ = 2RC g 1 2 I SS,2R, 1 2 W τ = 2RC g I SS,R,W τ = RC g C p 10 ff GSCALE=3 I SS = 1.2 ma I SS 8 I I SS I SS SS I total = 5.75I SS = 6.9 ma EECS 270C / Spring 2014 Prof. M. Green / U.C. Irvine 13

14 Clock Dividers The operation of real high-speed clock dividers is more complex EECS 270C / Spring 2014 Prof. M. Green / U.C. Irvine 14

15 Clock divider based on CML D flip-flop: & W # $!" % L D & W # $!" % L D & W # $!" % L L & W # $!" % L L & W # $!" % L D & W # $!" % L D & W # $!" % L L & W # $!" % L L & W # $!" % L C & W # $!" % L C & W # $!" % L C & W # $!" % L C Divider sensitivity curve: V min = minimum input clock amplitude required for correct operation. f so = self-oscillation frequency V max V max = maximum dc differential voltage that can be applied to the input clock for which the circuit self-oscillates. EECS 270C / Spring 2014 Prof. M. Green / U.C. Irvine 15

16 Sensitivity Curve Analysis Region I: Region II: Region III: Desired frequency divider operation Quasiperiodic operation Slew-rate limited operation EECS 270C / Spring 2014 Prof. M. Green / U.C. Irvine 16

17 Region II: Quasiperiodic behavior self-oscillating f in = 11GHz locked EECS 270C / Spring 2014 Prof. M. Green / U.C. Irvine 17

18 Region III: Slew-rate limited Behavior Sine-wave input Square-wave input EECS 270C / Spring 2014 Prof. M. Green / U.C. Irvine 18

19 Effect of Transistor Sizes on Sensitivity Curve Driver transistors Latch transistors Clock transistors EECS 270C / Spring 2014 Prof. M. Green / U.C. Irvine 19

20 Alternatives to DFF-Based Clock Dividers Latches present large capacitive load! slow EECS 270C / Spring 2014 Prof. M. Green / U.C. Irvine 20

21 At very high frequencies, latch transistors are not necessary and only add capacitance to the circuit: EECS 270C / Spring 2014 Prof. M. Green / U.C. Irvine 21

22 Ring-Oscillator-Based Divider Behaves like a 4-stage ring oscillator with injection of full-rate frequency. EECS 270C / Spring 2014 Prof. M. Green / U.C. Irvine 22

23 Comparison of Sensitivity Curves Conventional divider: Dynamic divider: Wider frequency range; lower self-oscillation frequency Narrow frequency range; higher self-oscillation frequency EECS 270C / Spring 2014 Prof. M. Green / U.C. Irvine 23

24 Effect of Non-Ideal Clock Signals I SS I 2 (t) 0 V DD I 1 (t) V out- (t) I 1 I 2 V DD I SS R V DD I SS (R+ΔR) V out+ (t) I SS R 0 I SS (R+ΔR) V out+ (t) V out- (t) Offset resistance causes deviation from 50% duty cycle in clock signal. EECS 270C / Spring 2014 Prof. M. Green / U.C. Irvine 24

25 Result of nonideal half-rate clock is Periodic Jitter. Half-rate clock with offset ideal MUX output with offset ideal EECS 270C / Spring 2014 Prof. M. Green / U.C. Irvine 25

26 Retimer eliminates this problem: 5 Gb/s 10 Gb/s data 10 Gb/s retimed data retimer 5 GHz 10 GHz clock retimed output Full-rate clock (could be non-50% duty cycle) EECS 270C / Spring 2014 Prof. M. Green / U.C. Irvine 26

27 Internal MUX Timing 5 Gb/s 10 Gb/s data output 2.5 Gb/s data input t p2 2.5 MHz 5 GHz 10 GHz clock t p1 t p1 & t p2 are clock-to-q delays. Because the clock & data flow in opposite directions, alignment between 5 Gb/s data & 5 GHz clock is determined by the sum: t p1 + t p2 (High sensitivity to processing / temp. corners) EECS 270C / Spring 2014 Prof. M. Green / U.C. Irvine 27

28 Serial Output 50Ω Line Driver 50Ω back termination used to reduce reflections. CML blocks scaled up so that last stage drives ac load of 25Ω. Shunt-peaking used in second stage. EECS 270C / Spring 2014 Prof. M. Green / U.C. Irvine 28

29 Receiver Block Diagram RB_LD LOS DETECT LOSB RXDOUT0P RDINP RDINN 9.953/ /10.664/ Gbps CML 1:16 DEMUX OUTPUT REGISTERS RXDOUT0N /644.54/666.51/ Mbps LVDS RXDOUT15P RXDOUT15N RXREFCLKP Divide-by-16 RXPOCLKP RXREFCLKN CDR RXPOCLKN RATESEL0/1 RESETB VCP VCN LCKREFB REF155ENB RXMCLKENB Divide-by-4 RXMCLKP RXMCLKN LCKDET 9.953/ /10.664/ G RSCLKP Test Only RSCLKN EECS 270C / Spring 2014 Prof. M. Green / U.C. Irvine 29

30 DMUX Architecture 1:2 2:4 4:8 8:16 10Gb/s Data 10GHz CLK D 1:2 A B D D 1:2 1:2 A B A B D D D D 1:2 1:2 1:2 1:2 A B A B A B A B 622Mb/s /2 /2 /2 /2 /2 311MHz CML Static CMOS 622MHz EECS 270C / Spring 2014 Prof. M. Green / U.C. Irvine 30

31 1:4 DMUX Tree Structure 10 Gb/s data input 5 Gb/s 2.5 Gb/s data outputs 10 GHz clock 5 GHz 2.5 GHz EECS 270C / Spring 2014 Prof. M. Green / U.C. Irvine 31

32 1:2 DMUX cell details: EECS 270C / Spring 2014 Prof. M. Green / U.C. Irvine 32

33 Internal DMUX Timing 10 Gb/s data input 5 Gb/s 2.5 Gb/s data output t p2 10 GHz clock 5 GHz 2.5 GHz t p1 & t p2 are clock-to-q delays. t p1 Because the clock & data flow in the same direction, alignment between 5 Gb/s data & 2.5 GHz clock is determined by the difference: t p1 t p2 (Low sensitivity to processing/temp. corners) EECS 270C / Spring 2014 Prof. M. Green / U.C. Irvine 33

34 Crosstalk in Transceivers f 1 f 2 Capacitive coupling between VCO s can cause frequency pulling Momentary differences in frequencies between 2 VCO s can give rise to additional jitter. EECS 270C / Spring 2014 Prof. M. Green / U.C. Irvine 34

35 Crosstalk Measurement CMU reference clock 10 GHz f ref = ( ) 16 Serial input data 10 Gb/s Low-frequency inputs/outputs Low-frequency inputs/outputs output clock 10 GHz + 100ppm recovered clock 10 GHz output data 10 Gb/s + 100ppm Jitter is measured at TX output clock (or data) and RX recovered clock. EECS 270C / Spring 2014 Prof. M. Green / U.C. Irvine 35

36 Techniques for Reducing Transceiver Crosstalk Sufficient physical separation between VCO s Separate supply connections to package for each block (e.g., CMU, CDR, MUX, DMUX, FIFO, etc.) Ample guard rings to minimize substrate coupling Very difficult to simulate & predict! EECS 270C / Spring 2014 Prof. M. Green / U.C. Irvine 36

37 SONET Jitter Specifications 1. Jitter Generation (transmitters) 2. Jitter Tolerance (receivers) 3. Jitter Transfer (repeaters) EECS 270C / Spring 2014 Prof. M. Green / U.C. Irvine 37

Jitter Generation (1) Wideband jitter (p-p or rms) can be measured directly from serial output data signal DJ always specified in peak-to-peak RJ rms jitter well-characterized RJ peak-to-peak jitter

38 Jitter Generation (1) Wideband jitter (p-p or rms) can be measured directly from serial output data signal DJ always specified in peak-to-peak RJ rms jitter well-characterized RJ peak-to-peak jitter dependent on measurement time (increases without bound) SONET: J PP usually measured over a specified frequency range. Gigabit Ethernet & Fiber Channel: Equivalent J PP determined by measured BER. EECS 270C / Spring 2014 Prof. M. Green / U.C. Irvine 38

39 Jitter Generation (2) SONET jitter generation is specified within a certain jitter frequency range. For OC-192: 50 khz 80 MHz To measure narrowband jitter generation, we can: A. Measure the recovered clock from a golden CDR: Ref. clock TX output data CDR (low jitter generation) 10 GHz recovered clock to jitter analyzer Should have jitter bandwidth > 80MHz SONET OC-192 bandpass filter EECS 270C / Spring 2014 Prof. M. Green / U.C. Irvine 39

40 Jitter Generation (3) B. Measure the TX output clock directly (assuming its jitter is the same as the data): Ref. clock TX output data TX output clock 10 GHz to jitter analyzer Note: ISI is usually measured separately (peak-to-peak only). EECS 270C / Spring 2014 Prof. M. Green / U.C. Irvine 40

Measured at output clock; 2 31-1 PRBS serial data applied to input Jitter Generation (4) 9.95328 GHz 10.

41 Measured at output clock; PRBS serial data applied to input Jitter Generation (4) GHz GHz Phase noise: MHz offset Jitter generation (SONET filter): 5.6mUI rms / 60mUI p-p Phase noise: MHz offset Jitter generation (SONET filter): 6.2mUI rms / 65mUI p-p EECS 270C / Spring 2014 Prof. M. Green / U.C. Irvine 41

Jitter Generation (5) Jitter measurements from clock: Jitter Generation (2 31-1 PRBS): 6.44 ps pp (wide band) 0.

42 Jitter Generation (5) Jitter measurements from clock: Jitter Generation ( PRBS): 6.44 ps pp (wide band) 0.38ps rms (within SONET band) Closed-loop VCO phase noise ( PRBS): MHz offset EECS 270C / Spring 2014 Prof. M. Green / U.C. Irvine 42

Jitter Generation (6) 2 31-1 PRBS input data applied:

2ps rms 10.6642Gb/s data Wideband jitter: 10.

43 Jitter Generation (6) PRBS input data applied: GHz clock Wideband jitter: 7.5ps p-p / 1.2ps rms Gb/s data Wideband jitter: 10.7ps p-p / 1.8ps rms EECS 270C / Spring 2014 Prof. M. Green / U.C. Irvine 43

44 Jitter Tolerance (1) Experiment: Apply serial data to CDR with jitter at a certain frequency. Increase the jitter amplitude until a bit error occurs. retimed data out Serial data in retimer recovered clock To DMUX T If data jitter & recovered clock jitter could perfectly track, then retiming would be error-free. Recovered clock t sh Data in EECS 270C / Spring 2014 Prof. M. Green / U.C. Irvine 44

45 Jitter Tolerance (2) Given CDR open-loop characteristic G( jω) = K pd F( jω) K vco ^ jω f data f clock φ clock = G φ data 1+G φ data φ clock φ data = 1 1+G φ data(max) (ω) = 1+G( jω) φ data φ clock max = 1+G( jω) 2π T t sh T % JTOL(ω) = 1+G( jω) 1 t sh ' & T ( * (expressed in UI) ) EECS 270C / Spring 2014 Prof. M. Green / U.C. Irvine 45

46 Jitter Tolerance (3) Jitter Tolerance [UIpp] Bit rate: 10.7Gb/s Bit rate: 10.7 Pattern: PRBS Pattern: BER 2 31 threshold: -1PRBS Data in: 50 mv pp BER threshold: K 10K 100K 1M 10M 100M Jitter Jitter Frequency (Hz)"[Hz] Jitter Tolerance > 40 ps pp at high frequency EECS 270C / Spring 2014 Prof. M. Green / U.C. Irvine 46

47 Jitter Transfer repeater O E RX TX E O H RX ( jω) H TX ( jω) [ ] n n repeaters: H jω RX ( ) H RX ( jω) Jitter peaking should be minimized. Jitter Transfer Mask: 0.1dB -20 db/decade f 0 EECS 270C / Spring 2014 Prof. M. Green / U.C. Irvine 47

48 Electrical-to-Optical Interfaces (1) Electrical to optical (TX): I L optical output power MUX laser driver T laser diode or Vertical Cavity Surface Emitting Laser (VCSEL) I th ~ 10mA I L EECS 270C / Spring 2014 Prof. M. Green / U.C. Irvine 48

49 Electrical-to-Optical Interfaces (2) Electroabsorption modulator P in P out P in V M P out Operates by making optical material more or less absorptive. swing ~ 3V M EECS 270C / Spring 2014 Prof. M. Green / U.C. Irvine 49

Electrical-to-Optical Interfaces (3) Mach-Zender interferometer: Mach-Zender modulator: P out P in Invented in 1890s Used to precisely measure optical phase shift

50 Electrical-to-Optical Interfaces (3) Mach-Zender interferometer: Mach-Zender modulator: P out P in Invented in 1890s Used to precisely measure optical phase shift of materials. By using constructive/destructive interference, can be used as a laser modulator. swing ~ 6V M EECS 270C / Spring 2014 Prof. M. Green / U.C. Irvine 50

51 Electrical-to-Optical Interfaces (4) Optical pulsewidth distortion commonly occurs due to: Unequal turn-on/turn-off times of laser diode Non-ideal bias voltage in modulators. Electrical signal (I L or V M ) Optical output Results in DCD Additional circuitry to correct pulsewidth is often added to system... EECS 270C / Spring 2014 Prof. M. Green / U.C. Irvine 51

52 Electrical-to-Optical Interfaces (5) Optical output control circuit: laser diode monitor diode V M I B V ref R Feedback sets I B = V ref R EECS 270C / Spring 2014 Prof. M. Green / U.C. Irvine 52

53 Optical Receiver Block Diagram O E TIA LA EQ CDR DMUX -18 dbm 10 µa 10 mv p-p 400 mv p-p EECS 270C / Spring 2014 Prof. M. Green / U.C. Irvine 53

54 Optical-to-Electrical Interfaces (1) p-i-n photodetector structure: circuit model: + resulting electrical current + n V R ~5V _ applied optical signal i p _ C D ρ = 0.6 ~ 0.9 A W C D ~ 400 ff I D = ρ P opt EECS 270C / Spring 2014 Prof. M. Green / U.C. Irvine 54

55 Optical-to-Electrical Interfaces (2) DCD & ISI are evident. Noise is higher at logic 1 than at logic 0. Photodetector noise: i n 2 = 4qρP opt Δf Eye diagram of PRBS resulting from 96 km of single-mode fiber and photodetector. EECS 270C / Spring 2014 Prof. M. Green / U.C. Irvine 55

56 Transimpedance Amplifier (TIA) Used to convert photodetector current into voltage. R A 0 V out I in C d from photodetector V ref low-impedance node maintains nearly constant detector voltage good linearity. EECS 270C / Spring 2014 Prof. M. Green / U.C. Irvine 56

57 Transimpedance Amplifier (2) R Transimpedance: Z T V out I in = R f A 0 I in C d C g A 0 V out Input impedance: Z in V I in = R f 1+ A 0 photodetector V ref Loop gain: A(s) f (s) = A 0 (1+ s p 1 ) (1+ s p 2 ) 1 1+ sr f (C d +C g ) additional pole limits closed-loop BW EECS 270C / Spring 2014 Prof. M. Green / U.C. Irvine 57

58 Transimpedance Amplifier (3) Noise analysis: i nr R v out Good sensitivity requires: Large R f Large C Tradeoff with BW g Large g m v ni 2 v out = v 2 ni + i 2 2 nr R f = i 2 2 eq R f i 2 eq = v 2 ni R + i 2 2 nr f v 2 ni = 4kTγ Δf + K f Δf g m C g f 2 i nr = 4kT R f Δf i 2 eq = 4kT % 1+ γ + K f ' R f & g m R f C g R f f ( * Δf ) EECS 270C / Spring 2014 Prof. M. Green / U.C. Irvine 58

59 Transimpedance Amplifier (4) C d R C d R L B C g C g C d decoupled from feedback network Common-gate device increases noise L B provides decoupling (series peaking); could be realized by bondwire. EECS 270C / Spring 2014 Prof. M. Green / U.C. Irvine 59

60 Limiting Amplifiers Requirements: Amplify input signal with variable amplitude (~10-30 mv) to a fixed-amplitude (~450 mv) output. Sufficiently high bandwidth Sufficiently low noise Low offset voltage + V in A(s) A(s) A(s) + V out n stages Single stage: A(s) = A 0 1+ s p n-stage amplifier: " A % A n (s) = $ 0 ' # 1+ s p& n Overall gain: Overall bandwidth: A 0 n p 2 1 n 1 EECS 270C / Spring 2014 Prof. M. Green / U.C. Irvine 60

61 7-Stage Limiting Amplifier Example (1) Each stage uses shunt-peaked CML buffer with: A 0 = 5.5 db BW = 10 GHz A( jω) (db) 7 th stage output 1 st stage output 100 MHz 1 GHz 10 GHz 100 GHz EECS 270C / Spring 2014 Prof. M. Green / U.C. Irvine 61

62 7-Stage Limiting Amplifier Example (2) 7 th stage output 6 th stage output 7 th stage output 6 th stage output 1 st stage output 1 st stage output Input amplitude = 20 mv p-p Input amplitude = 40 mv p-p EECS 270C / Spring 2014 Prof. M. Green / U.C. Irvine 62

63 7-Stage Limiting Amplifier Example (3) 7 th stage output 6 th stage output 1 st stage output Input amplitude = 20 mv p-p Input-referred offset of 5 mv applied V out A 0 n V OS Offset-cancellation circuitry required! EECS 270C / Spring 2014 Prof. M. Green / U.C. Irvine 63

64 Limiting Amplifier Offset Compensation R L R L n-stage amplifier core + V 1 + V out V OS + v in M 1 M 1 M 1 M 1 R F + V out R F offset compensation compensation circuit: V 1 = g m1 R [( v in +V OS ) V out ] V 1 = g m1 R V OS V out v 1 = g m1 R v in amplifier circuit: V out = A n 0 V 1 V out = A n 0 V 1 ( ) C F C F lowpass filter H.-Y. Huang et al., A 10-Gb/s inductorless CMOS limiting amplifier with third-order interleaving active feedback, JSSC, May 2007, pp V out = g RA n m g m1 RA V V n OS OS 0 v out = g m1 RA 0 n v in v out = A 0 n v 1 EECS 270C / Spring 2014 Prof. M. Green / U.C. Irvine 64

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